Commit | Line | Data |
---|---|---|
952cf6d7 JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV architectural definitions | |
7 | * | |
5f40f7d9 | 8 | * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. |
952cf6d7 JS |
9 | */ |
10 | ||
05e4d316 PA |
11 | #ifndef _ASM_X86_UV_UV_HUB_H |
12 | #define _ASM_X86_UV_UV_HUB_H | |
952cf6d7 | 13 | |
bc5d9940 | 14 | #ifdef CONFIG_X86_64 |
952cf6d7 JS |
15 | #include <linux/numa.h> |
16 | #include <linux/percpu.h> | |
c08b6acc | 17 | #include <linux/timer.h> |
8dc579e8 | 18 | #include <linux/io.h> |
906f3b20 | 19 | #include <linux/topology.h> |
952cf6d7 JS |
20 | #include <asm/types.h> |
21 | #include <asm/percpu.h> | |
66666e50 | 22 | #include <asm/uv/uv_mmrs.h> |
02dd0a06 RH |
23 | #include <asm/irq_vectors.h> |
24 | #include <asm/io_apic.h> | |
952cf6d7 JS |
25 | |
26 | ||
27 | /* | |
28 | * Addressing Terminology | |
29 | * | |
9f5314fb JS |
30 | * M - The low M bits of a physical address represent the offset |
31 | * into the blade local memory. RAM memory on a blade is physically | |
32 | * contiguous (although various IO spaces may punch holes in | |
33 | * it).. | |
952cf6d7 | 34 | * |
39d30770 MT |
35 | * N - Number of bits in the node portion of a socket physical |
36 | * address. | |
9f5314fb | 37 | * |
39d30770 MT |
38 | * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of |
39 | * routers always have low bit of 1, C/MBricks have low bit | |
40 | * equal to 0. Most addressing macros that target UV hub chips | |
41 | * right shift the NASID by 1 to exclude the always-zero bit. | |
42 | * NASIDs contain up to 15 bits. | |
9f5314fb JS |
43 | * |
44 | * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead | |
45 | * of nasids. | |
46 | * | |
39d30770 MT |
47 | * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant |
48 | * of the nasid for socket usage. | |
9f5314fb | 49 | * |
6a469e46 JS |
50 | * GPA - (global physical address) a socket physical address converted |
51 | * so that it can be used by the GRU as a global address. Socket | |
52 | * physical addresses 1) need additional NASID (node) bits added | |
53 | * to the high end of the address, and 2) unaliased if the | |
54 | * partition does not have a physical address 0. In addition, on | |
55 | * UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40. | |
56 | * | |
9f5314fb JS |
57 | * |
58 | * NumaLink Global Physical Address Format: | |
59 | * +--------------------------------+---------------------+ | |
60 | * |00..000| GNODE | NodeOffset | | |
61 | * +--------------------------------+---------------------+ | |
62 | * |<-------53 - M bits --->|<--------M bits -----> | |
63 | * | |
64 | * M - number of node offset bits (35 .. 40) | |
952cf6d7 JS |
65 | * |
66 | * | |
67 | * Memory/UV-HUB Processor Socket Address Format: | |
9f5314fb JS |
68 | * +----------------+---------------+---------------------+ |
69 | * |00..000000000000| PNODE | NodeOffset | | |
70 | * +----------------+---------------+---------------------+ | |
71 | * <--- N bits --->|<--------M bits -----> | |
952cf6d7 | 72 | * |
9f5314fb JS |
73 | * M - number of node offset bits (35 .. 40) |
74 | * N - number of PNODE bits (0 .. 10) | |
952cf6d7 JS |
75 | * |
76 | * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). | |
77 | * The actual values are configuration dependent and are set at | |
9f5314fb JS |
78 | * boot time. M & N values are set by the hardware/BIOS at boot. |
79 | * | |
952cf6d7 JS |
80 | * |
81 | * APICID format | |
39d30770 MT |
82 | * NOTE!!!!!! This is the current format of the APICID. However, code |
83 | * should assume that this will change in the future. Use functions | |
84 | * in this file for all APICID bit manipulations and conversion. | |
952cf6d7 | 85 | * |
39d30770 MT |
86 | * 1111110000000000 |
87 | * 5432109876543210 | |
2a919596 JS |
88 | * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg) |
89 | * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg) | |
90 | * pppppppppppcccch SandyBridge (15 bits in hdw reg) | |
952cf6d7 JS |
91 | * sssssssssss |
92 | * | |
9f5314fb | 93 | * p = pnode bits |
952cf6d7 JS |
94 | * l = socket number on board |
95 | * c = core | |
96 | * h = hyperthread | |
9f5314fb | 97 | * s = bits that are in the SOCKET_ID CSR |
952cf6d7 | 98 | * |
2a919596 | 99 | * Note: Processor may support fewer bits in the APICID register. The ACPI |
952cf6d7 JS |
100 | * tables hold all 16 bits. Software needs to be aware of this. |
101 | * | |
39d30770 MT |
102 | * Unless otherwise specified, all references to APICID refer to |
103 | * the FULL value contained in ACPI tables, not the subset in the | |
104 | * processor APICID register. | |
952cf6d7 JS |
105 | */ |
106 | ||
107 | ||
108 | /* | |
109 | * Maximum number of bricks in all partitions and in all coherency domains. | |
110 | * This is the total number of bricks accessible in the numalink fabric. It | |
111 | * includes all C & M bricks. Routers are NOT included. | |
112 | * | |
113 | * This value is also the value of the maximum number of non-router NASIDs | |
114 | * in the numalink fabric. | |
115 | * | |
9f5314fb | 116 | * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. |
952cf6d7 JS |
117 | */ |
118 | #define UV_MAX_NUMALINK_BLADES 16384 | |
119 | ||
120 | /* | |
121 | * Maximum number of C/Mbricks within a software SSI (hardware may support | |
122 | * more). | |
123 | */ | |
124 | #define UV_MAX_SSI_BLADES 256 | |
125 | ||
126 | /* | |
127 | * The largest possible NASID of a C or M brick (+ 2) | |
128 | */ | |
1d21e6e3 | 129 | #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) |
952cf6d7 | 130 | |
d38bb135 | 131 | /* System Controller Interface Reg info */ |
7f1baa06 MT |
132 | struct uv_scir_s { |
133 | struct timer_list timer; | |
134 | unsigned long offset; | |
135 | unsigned long last; | |
136 | unsigned long idle_on; | |
137 | unsigned long idle_off; | |
138 | unsigned char state; | |
139 | unsigned char enabled; | |
140 | }; | |
141 | ||
952cf6d7 JS |
142 | /* |
143 | * The following defines attributes of the HUB chip. These attributes are | |
0045ddd2 MT |
144 | * frequently referenced and are kept in a common per hub struct. |
145 | * After setup, the struct is read only, so it should be readily | |
146 | * available in the L3 cache on the cpu socket for the node. | |
952cf6d7 JS |
147 | */ |
148 | struct uv_hub_info_s { | |
69a72a0e | 149 | unsigned long global_mmr_base; |
1de329c1 | 150 | unsigned long global_mmr_shift; |
69a72a0e | 151 | unsigned long gpa_mask; |
1de329c1 MT |
152 | unsigned short min_socket; |
153 | unsigned short min_pnode; | |
2a919596 JS |
154 | unsigned char hub_revision; |
155 | unsigned char apic_pnode_shift; | |
1de329c1 | 156 | unsigned char gpa_shift; |
6a469e46 JS |
157 | unsigned char m_shift; |
158 | unsigned char n_lshift; | |
1de329c1 | 159 | unsigned int gnode_extra; |
69a72a0e MT |
160 | unsigned long gnode_upper; |
161 | unsigned long lowmem_remap_top; | |
162 | unsigned long lowmem_remap_base; | |
1de329c1 MT |
163 | unsigned long global_gru_base; |
164 | unsigned long global_gru_shift; | |
69a72a0e MT |
165 | unsigned short pnode; |
166 | unsigned short pnode_mask; | |
167 | unsigned short coherency_domain_number; | |
168 | unsigned short numa_blade_id; | |
69a72a0e MT |
169 | unsigned char m_val; |
170 | unsigned char n_val; | |
906f3b20 MT |
171 | unsigned short nr_possible_cpus; |
172 | unsigned short nr_online_cpus; | |
173 | short memory_nid; | |
952cf6d7 | 174 | }; |
7f1baa06 | 175 | |
0045ddd2 MT |
176 | /* CPU specific info with a pointer to the hub common info struct */ |
177 | struct uv_cpu_info_s { | |
178 | void *p_uv_hub_info; | |
179 | unsigned char blade_cpu_id; | |
180 | struct uv_scir_s scir; | |
181 | }; | |
182 | DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); | |
183 | ||
184 | #define uv_cpu_info this_cpu_ptr(&__uv_cpu_info) | |
185 | #define uv_cpu_info_per(cpu) (&per_cpu(__uv_cpu_info, cpu)) | |
186 | ||
d38bb135 MT |
187 | #define uv_scir_info (&uv_cpu_info->scir) |
188 | #define uv_cpu_scir_info(cpu) (&uv_cpu_info_per(cpu)->scir) | |
189 | ||
3edcf2ff MT |
190 | /* Node specific hub common info struct */ |
191 | extern void **__uv_hub_info_list; | |
192 | static inline struct uv_hub_info_s *uv_hub_info_list(int node) | |
193 | { | |
194 | return (struct uv_hub_info_s *)__uv_hub_info_list[node]; | |
195 | } | |
196 | ||
197 | static inline struct uv_hub_info_s *_uv_hub_info(void) | |
198 | { | |
199 | return (struct uv_hub_info_s *)uv_cpu_info->p_uv_hub_info; | |
200 | } | |
201 | #define uv_hub_info _uv_hub_info() | |
202 | ||
203 | static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu) | |
204 | { | |
205 | return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info; | |
206 | } | |
207 | ||
208 | #define UV_HUB_INFO_VERSION 0x7150 | |
209 | extern int uv_hub_info_version(void); | |
210 | static inline int uv_hub_info_check(int version) | |
211 | { | |
212 | if (uv_hub_info_version() == version) | |
213 | return 0; | |
214 | ||
215 | pr_crit("UV: uv_hub_info version(%x) mismatch, expecting(%x)\n", | |
216 | uv_hub_info_version(), version); | |
217 | ||
218 | BUG(); /* Catastrophic - cannot continue on unknown UV system */ | |
219 | } | |
220 | #define _uv_hub_info_check() uv_hub_info_check(UV_HUB_INFO_VERSION) | |
221 | ||
2a919596 | 222 | /* |
0045ddd2 | 223 | * HUB revision ranges for each UV HUB architecture. |
2a919596 JS |
224 | * This is a software convention - NOT the hardware revision numbers in |
225 | * the hub chip. | |
226 | */ | |
227 | #define UV1_HUB_REVISION_BASE 1 | |
228 | #define UV2_HUB_REVISION_BASE 3 | |
6edbd471 | 229 | #define UV3_HUB_REVISION_BASE 5 |
eb1e3461 | 230 | #define UV4_HUB_REVISION_BASE 7 |
2a919596 | 231 | |
e0ee1c97 | 232 | #ifdef UV1_HUB_IS_SUPPORTED |
2a919596 JS |
233 | static inline int is_uv1_hub(void) |
234 | { | |
235 | return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE; | |
236 | } | |
e0ee1c97 MT |
237 | #else |
238 | static inline int is_uv1_hub(void) | |
239 | { | |
240 | return 0; | |
241 | } | |
242 | #endif | |
2a919596 | 243 | |
e0ee1c97 | 244 | #ifdef UV2_HUB_IS_SUPPORTED |
2a919596 | 245 | static inline int is_uv2_hub(void) |
6edbd471 MT |
246 | { |
247 | return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) && | |
248 | (uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE)); | |
249 | } | |
e0ee1c97 MT |
250 | #else |
251 | static inline int is_uv2_hub(void) | |
252 | { | |
253 | return 0; | |
254 | } | |
255 | #endif | |
6edbd471 | 256 | |
e0ee1c97 | 257 | #ifdef UV3_HUB_IS_SUPPORTED |
6edbd471 MT |
258 | static inline int is_uv3_hub(void) |
259 | { | |
eb1e3461 MT |
260 | return ((uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE) && |
261 | (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)); | |
6edbd471 | 262 | } |
e0ee1c97 MT |
263 | #else |
264 | static inline int is_uv3_hub(void) | |
265 | { | |
266 | return 0; | |
267 | } | |
268 | #endif | |
6edbd471 | 269 | |
eb1e3461 MT |
270 | #ifdef UV4_HUB_IS_SUPPORTED |
271 | static inline int is_uv4_hub(void) | |
272 | { | |
273 | return uv_hub_info->hub_revision >= UV4_HUB_REVISION_BASE; | |
274 | } | |
275 | #else | |
276 | static inline int is_uv4_hub(void) | |
277 | { | |
278 | return 0; | |
279 | } | |
280 | #endif | |
281 | ||
e0ee1c97 | 282 | static inline int is_uvx_hub(void) |
6edbd471 | 283 | { |
e0ee1c97 MT |
284 | if (uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) |
285 | return uv_hub_info->hub_revision; | |
286 | ||
287 | return 0; | |
6edbd471 MT |
288 | } |
289 | ||
e0ee1c97 | 290 | static inline int is_uv_hub(void) |
2a919596 | 291 | { |
e0ee1c97 MT |
292 | #ifdef UV1_HUB_IS_SUPPORTED |
293 | return uv_hub_info->hub_revision; | |
294 | #endif | |
295 | return is_uvx_hub(); | |
2a919596 JS |
296 | } |
297 | ||
c8f730b1 RA |
298 | union uvh_apicid { |
299 | unsigned long v; | |
300 | struct uvh_apicid_s { | |
301 | unsigned long local_apic_mask : 24; | |
302 | unsigned long local_apic_shift : 5; | |
303 | unsigned long unused1 : 3; | |
304 | unsigned long pnode_mask : 24; | |
305 | unsigned long pnode_shift : 5; | |
306 | unsigned long unused2 : 3; | |
307 | } s; | |
308 | }; | |
309 | ||
952cf6d7 JS |
310 | /* |
311 | * Local & Global MMR space macros. | |
39d30770 MT |
312 | * Note: macros are intended to be used ONLY by inline functions |
313 | * in this file - not by other kernel code. | |
314 | * n - NASID (full 15-bit global nasid) | |
315 | * g - GNODE (full 15-bit global nasid, right shifted 1) | |
316 | * p - PNODE (local part of nsids, right shifted 1) | |
952cf6d7 | 317 | */ |
9f5314fb | 318 | #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) |
c4ed3f04 JS |
319 | #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) |
320 | #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) | |
952cf6d7 | 321 | |
2a919596 JS |
322 | #define UV1_LOCAL_MMR_BASE 0xf4000000UL |
323 | #define UV1_GLOBAL_MMR32_BASE 0xf8000000UL | |
324 | #define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024) | |
325 | #define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) | |
326 | ||
327 | #define UV2_LOCAL_MMR_BASE 0xfa000000UL | |
328 | #define UV2_GLOBAL_MMR32_BASE 0xfc000000UL | |
329 | #define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024) | |
330 | #define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) | |
331 | ||
6edbd471 MT |
332 | #define UV3_LOCAL_MMR_BASE 0xfa000000UL |
333 | #define UV3_GLOBAL_MMR32_BASE 0xfc000000UL | |
334 | #define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024) | |
335 | #define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) | |
336 | ||
eb1e3461 MT |
337 | #define UV4_LOCAL_MMR_BASE 0xfa000000UL |
338 | #define UV4_GLOBAL_MMR32_BASE 0xfc000000UL | |
339 | #define UV4_LOCAL_MMR_SIZE (32UL * 1024 * 1024) | |
340 | #define UV4_GLOBAL_MMR32_SIZE (16UL * 1024 * 1024) | |
341 | ||
342 | #define UV_LOCAL_MMR_BASE ( \ | |
343 | is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \ | |
344 | is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \ | |
345 | is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \ | |
346 | /*is_uv4_hub*/ UV4_LOCAL_MMR_BASE) | |
347 | ||
348 | #define UV_GLOBAL_MMR32_BASE ( \ | |
349 | is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \ | |
350 | is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \ | |
351 | is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \ | |
352 | /*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE) | |
353 | ||
354 | #define UV_LOCAL_MMR_SIZE ( \ | |
355 | is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \ | |
356 | is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \ | |
357 | is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \ | |
358 | /*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE) | |
359 | ||
360 | #define UV_GLOBAL_MMR32_SIZE ( \ | |
361 | is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \ | |
362 | is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \ | |
363 | is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \ | |
364 | /*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE) | |
365 | ||
952cf6d7 JS |
366 | #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) |
367 | ||
56abcf24 JS |
368 | #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 |
369 | ||
9f5314fb | 370 | #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 |
1de329c1 MT |
371 | #define _UV_GLOBAL_MMR64_PNODE_SHIFT 26 |
372 | #define UV_GLOBAL_MMR64_PNODE_SHIFT (uv_hub_info->global_mmr_shift) | |
952cf6d7 | 373 | |
9f5314fb | 374 | #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) |
952cf6d7 | 375 | |
9f5314fb | 376 | #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ |
67e83f30 | 377 | (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) |
9f5314fb | 378 | |
c8f730b1 | 379 | #define UVH_APICID 0x002D0E00L |
9f5314fb JS |
380 | #define UV_APIC_PNODE_SHIFT 6 |
381 | ||
8191c9f6 DS |
382 | #define UV_APICID_HIBIT_MASK 0xffff0000 |
383 | ||
7f1baa06 MT |
384 | /* Local Bus from cpu's perspective */ |
385 | #define LOCAL_BUS_BASE 0x1c00000 | |
386 | #define LOCAL_BUS_SIZE (4 * 1024 * 1024) | |
387 | ||
388 | /* | |
389 | * System Controller Interface Reg | |
390 | * | |
391 | * Note there are NO leds on a UV system. This register is only | |
392 | * used by the system controller to monitor system-wide operation. | |
393 | * There are 64 regs per node. With Nahelem cpus (2 cores per node, | |
394 | * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on | |
395 | * a node. | |
396 | * | |
397 | * The window is located at top of ACPI MMR space | |
398 | */ | |
399 | #define SCIR_WINDOW_COUNT 64 | |
400 | #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ | |
401 | LOCAL_BUS_SIZE - \ | |
402 | SCIR_WINDOW_COUNT) | |
403 | ||
404 | #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ | |
405 | #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ | |
406 | #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ | |
407 | ||
8661984f DS |
408 | /* Loop through all installed blades */ |
409 | #define for_each_possible_blade(bid) \ | |
410 | for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) | |
411 | ||
9f5314fb JS |
412 | /* |
413 | * Macros for converting between kernel virtual addresses, socket local physical | |
414 | * addresses, and UV global physical addresses. | |
39d30770 MT |
415 | * Note: use the standard __pa() & __va() macros for converting |
416 | * between socket virtual and socket physical addresses. | |
9f5314fb JS |
417 | */ |
418 | ||
419 | /* socket phys RAM --> UV global physical address */ | |
420 | static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) | |
421 | { | |
422 | if (paddr < uv_hub_info->lowmem_remap_top) | |
189f67c4 | 423 | paddr |= uv_hub_info->lowmem_remap_base; |
6a469e46 JS |
424 | paddr |= uv_hub_info->gnode_upper; |
425 | paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | | |
426 | ((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift); | |
427 | return paddr; | |
9f5314fb JS |
428 | } |
429 | ||
430 | ||
431 | /* socket virtual --> UV global physical address */ | |
432 | static inline unsigned long uv_gpa(void *v) | |
433 | { | |
189f67c4 | 434 | return uv_soc_phys_ram_to_gpa(__pa(v)); |
9f5314fb | 435 | } |
1d21e6e3 | 436 | |
fae419f2 RH |
437 | /* Top two bits indicate the requested address is in MMR space. */ |
438 | static inline int | |
439 | uv_gpa_in_mmr_space(unsigned long gpa) | |
440 | { | |
441 | return (gpa >> 62) == 0x3UL; | |
442 | } | |
443 | ||
729d69e6 RH |
444 | /* UV global physical address --> socket phys RAM */ |
445 | static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) | |
446 | { | |
5a51467b | 447 | unsigned long paddr; |
729d69e6 RH |
448 | unsigned long remap_base = uv_hub_info->lowmem_remap_base; |
449 | unsigned long remap_top = uv_hub_info->lowmem_remap_top; | |
450 | ||
6a469e46 JS |
451 | gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | |
452 | ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); | |
5a51467b | 453 | paddr = gpa & uv_hub_info->gpa_mask; |
729d69e6 RH |
454 | if (paddr >= remap_base && paddr < remap_base + remap_top) |
455 | paddr -= remap_base; | |
456 | return paddr; | |
457 | } | |
458 | ||
459 | ||
906f3b20 | 460 | /* gpa -> gnode */ |
1d21e6e3 RH |
461 | static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) |
462 | { | |
6a469e46 | 463 | return gpa >> uv_hub_info->n_lshift; |
1d21e6e3 RH |
464 | } |
465 | ||
466 | /* gpa -> pnode */ | |
467 | static inline int uv_gpa_to_pnode(unsigned long gpa) | |
468 | { | |
906f3b20 | 469 | return uv_gpa_to_gnode(gpa) & uv_hub_info->pnode_mask; |
1d21e6e3 | 470 | } |
9f5314fb | 471 | |
906f3b20 | 472 | /* gpa -> node offset */ |
6a469e46 JS |
473 | static inline unsigned long uv_gpa_to_offset(unsigned long gpa) |
474 | { | |
475 | return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift; | |
476 | } | |
477 | ||
9f5314fb JS |
478 | /* pnode, offset --> socket virtual */ |
479 | static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) | |
480 | { | |
481 | return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); | |
482 | } | |
952cf6d7 | 483 | |
906f3b20 | 484 | /* Extract a PNODE from an APICID (full apicid, not processor subset) */ |
9f5314fb | 485 | static inline int uv_apicid_to_pnode(int apicid) |
952cf6d7 | 486 | { |
c8f730b1 | 487 | return (apicid >> uv_hub_info->apic_pnode_shift); |
952cf6d7 JS |
488 | } |
489 | ||
906f3b20 | 490 | /* Convert an apicid to the socket number on the blade */ |
2a919596 JS |
491 | static inline int uv_apicid_to_socket(int apicid) |
492 | { | |
493 | if (is_uv1_hub()) | |
494 | return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1; | |
495 | else | |
496 | return 0; | |
497 | } | |
498 | ||
952cf6d7 JS |
499 | /* |
500 | * Access global MMRs using the low memory MMR32 space. This region supports | |
501 | * faster MMR access but not all MMRs are accessible in this space. | |
502 | */ | |
39d30770 | 503 | static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) |
952cf6d7 JS |
504 | { |
505 | return __va(UV_GLOBAL_MMR32_BASE | | |
9f5314fb | 506 | UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); |
952cf6d7 JS |
507 | } |
508 | ||
39d30770 | 509 | static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) |
952cf6d7 | 510 | { |
8dc579e8 | 511 | writeq(val, uv_global_mmr32_address(pnode, offset)); |
952cf6d7 JS |
512 | } |
513 | ||
39d30770 | 514 | static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) |
952cf6d7 | 515 | { |
8dc579e8 | 516 | return readq(uv_global_mmr32_address(pnode, offset)); |
952cf6d7 JS |
517 | } |
518 | ||
519 | /* | |
520 | * Access Global MMR space using the MMR space located at the top of physical | |
521 | * memory. | |
522 | */ | |
a289cc7c | 523 | static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) |
952cf6d7 JS |
524 | { |
525 | return __va(UV_GLOBAL_MMR64_BASE | | |
9f5314fb | 526 | UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); |
952cf6d7 JS |
527 | } |
528 | ||
39d30770 | 529 | static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) |
952cf6d7 | 530 | { |
8dc579e8 | 531 | writeq(val, uv_global_mmr64_address(pnode, offset)); |
952cf6d7 JS |
532 | } |
533 | ||
39d30770 | 534 | static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) |
952cf6d7 | 535 | { |
8dc579e8 | 536 | return readq(uv_global_mmr64_address(pnode, offset)); |
952cf6d7 JS |
537 | } |
538 | ||
56abcf24 JS |
539 | /* |
540 | * Global MMR space addresses when referenced by the GRU. (GRU does | |
541 | * NOT use socket addressing). | |
542 | */ | |
543 | static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset) | |
544 | { | |
e1e0138d JS |
545 | return UV_GLOBAL_GRU_MMR_BASE | offset | |
546 | ((unsigned long)pnode << uv_hub_info->m_val); | |
56abcf24 JS |
547 | } |
548 | ||
39d30770 MT |
549 | static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) |
550 | { | |
551 | writeb(val, uv_global_mmr64_address(pnode, offset)); | |
552 | } | |
553 | ||
554 | static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) | |
555 | { | |
556 | return readb(uv_global_mmr64_address(pnode, offset)); | |
557 | } | |
558 | ||
952cf6d7 | 559 | /* |
9f5314fb | 560 | * Access hub local MMRs. Faster than using global space but only local MMRs |
952cf6d7 JS |
561 | * are accessible. |
562 | */ | |
563 | static inline unsigned long *uv_local_mmr_address(unsigned long offset) | |
564 | { | |
565 | return __va(UV_LOCAL_MMR_BASE | offset); | |
566 | } | |
567 | ||
568 | static inline unsigned long uv_read_local_mmr(unsigned long offset) | |
569 | { | |
8dc579e8 | 570 | return readq(uv_local_mmr_address(offset)); |
952cf6d7 JS |
571 | } |
572 | ||
573 | static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) | |
574 | { | |
8dc579e8 | 575 | writeq(val, uv_local_mmr_address(offset)); |
952cf6d7 JS |
576 | } |
577 | ||
7f1baa06 MT |
578 | static inline unsigned char uv_read_local_mmr8(unsigned long offset) |
579 | { | |
8dc579e8 | 580 | return readb(uv_local_mmr_address(offset)); |
7f1baa06 MT |
581 | } |
582 | ||
583 | static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) | |
584 | { | |
8dc579e8 | 585 | writeb(val, uv_local_mmr_address(offset)); |
7f1baa06 MT |
586 | } |
587 | ||
8400def8 JS |
588 | /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ |
589 | static inline int uv_blade_processor_id(void) | |
590 | { | |
5627a825 | 591 | return uv_cpu_info->blade_cpu_id; |
8400def8 JS |
592 | } |
593 | ||
5627a825 MT |
594 | /* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */ |
595 | static inline int uv_cpu_blade_processor_id(int cpu) | |
596 | { | |
597 | return uv_cpu_info_per(cpu)->blade_cpu_id; | |
598 | } | |
599 | #define _uv_cpu_blade_processor_id 1 /* indicate function available */ | |
600 | ||
906f3b20 MT |
601 | /* Blade number to Node number (UV1..UV4 is 1:1) */ |
602 | static inline int uv_blade_to_node(int blade) | |
603 | { | |
604 | return blade; | |
605 | } | |
606 | ||
8400def8 JS |
607 | /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ |
608 | static inline int uv_numa_blade_id(void) | |
609 | { | |
610 | return uv_hub_info->numa_blade_id; | |
611 | } | |
612 | ||
906f3b20 MT |
613 | /* |
614 | * Convert linux node number to the UV blade number. | |
615 | * .. Currently for UV1 thru UV4 the node and the blade are identical. | |
616 | * .. If this changes then you MUST check references to this function! | |
617 | */ | |
618 | static inline int uv_node_to_blade_id(int nid) | |
8400def8 | 619 | { |
906f3b20 | 620 | return nid; |
8400def8 JS |
621 | } |
622 | ||
906f3b20 MT |
623 | /* Convert a cpu number to the the UV blade number */ |
624 | static inline int uv_cpu_to_blade_id(int cpu) | |
8400def8 | 625 | { |
906f3b20 | 626 | return uv_node_to_blade_id(cpu_to_node(cpu)); |
8400def8 JS |
627 | } |
628 | ||
9f5314fb JS |
629 | /* Convert a blade id to the PNODE of the blade */ |
630 | static inline int uv_blade_to_pnode(int bid) | |
8400def8 | 631 | { |
906f3b20 | 632 | return uv_hub_info_list(uv_blade_to_node(bid))->pnode; |
8400def8 JS |
633 | } |
634 | ||
6c7184b7 JS |
635 | /* Nid of memory node on blade. -1 if no blade-local memory */ |
636 | static inline int uv_blade_to_memory_nid(int bid) | |
637 | { | |
906f3b20 | 638 | return uv_hub_info_list(uv_blade_to_node(bid))->memory_nid; |
6c7184b7 JS |
639 | } |
640 | ||
8400def8 JS |
641 | /* Determine the number of possible cpus on a blade */ |
642 | static inline int uv_blade_nr_possible_cpus(int bid) | |
643 | { | |
906f3b20 | 644 | return uv_hub_info_list(uv_blade_to_node(bid))->nr_possible_cpus; |
8400def8 JS |
645 | } |
646 | ||
647 | /* Determine the number of online cpus on a blade */ | |
648 | static inline int uv_blade_nr_online_cpus(int bid) | |
649 | { | |
906f3b20 | 650 | return uv_hub_info_list(uv_blade_to_node(bid))->nr_online_cpus; |
8400def8 JS |
651 | } |
652 | ||
9f5314fb JS |
653 | /* Convert a cpu id to the PNODE of the blade containing the cpu */ |
654 | static inline int uv_cpu_to_pnode(int cpu) | |
8400def8 | 655 | { |
906f3b20 | 656 | return uv_cpu_hub_info(cpu)->pnode; |
8400def8 JS |
657 | } |
658 | ||
9f5314fb JS |
659 | /* Convert a linux node number to the PNODE of the blade */ |
660 | static inline int uv_node_to_pnode(int nid) | |
8400def8 | 661 | { |
906f3b20 | 662 | return uv_hub_info_list(nid)->pnode; |
8400def8 JS |
663 | } |
664 | ||
665 | /* Maximum possible number of blades */ | |
906f3b20 | 666 | extern short uv_possible_blades; |
8400def8 JS |
667 | static inline int uv_num_possible_blades(void) |
668 | { | |
669 | return uv_possible_blades; | |
670 | } | |
671 | ||
0d12ef0c MT |
672 | /* Per Hub NMI support */ |
673 | extern void uv_nmi_setup(void); | |
674 | ||
675 | /* BMC sets a bit this MMR non-zero before sending an NMI */ | |
676 | #define UVH_NMI_MMR UVH_SCRATCH5 | |
677 | #define UVH_NMI_MMR_CLEAR UVH_SCRATCH5_ALIAS | |
678 | #define UVH_NMI_MMR_SHIFT 63 | |
679 | #define UVH_NMI_MMR_TYPE "SCRATCH5" | |
680 | ||
681 | /* Newer SMM NMI handler, not present in all systems */ | |
682 | #define UVH_NMI_MMRX UVH_EVENT_OCCURRED0 | |
683 | #define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS | |
c443c03d | 684 | #define UVH_NMI_MMRX_SHIFT UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT |
0d12ef0c MT |
685 | #define UVH_NMI_MMRX_TYPE "EXTIO_INT0" |
686 | ||
687 | /* Non-zero indicates newer SMM NMI handler present */ | |
688 | #define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST | |
689 | ||
690 | /* Indicates to BIOS that we want to use the newer SMM NMI handler */ | |
691 | #define UVH_NMI_MMRX_REQ UVH_SCRATCH5_ALIAS_2 | |
692 | #define UVH_NMI_MMRX_REQ_SHIFT 62 | |
693 | ||
694 | struct uv_hub_nmi_s { | |
695 | raw_spinlock_t nmi_lock; | |
696 | atomic_t in_nmi; /* flag this node in UV NMI IRQ */ | |
697 | atomic_t cpu_owner; /* last locker of this struct */ | |
698 | atomic_t read_mmr_count; /* count of MMR reads */ | |
699 | atomic_t nmi_count; /* count of true UV NMIs */ | |
700 | unsigned long nmi_value; /* last value read from NMI MMR */ | |
701 | }; | |
702 | ||
703 | struct uv_cpu_nmi_s { | |
704 | struct uv_hub_nmi_s *hub; | |
e1632170 CL |
705 | int state; |
706 | int pinging; | |
0d12ef0c MT |
707 | int queries; |
708 | int pings; | |
709 | }; | |
710 | ||
e1632170 CL |
711 | DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi); |
712 | ||
7c52198b | 713 | #define uv_hub_nmi this_cpu_read(uv_cpu_nmi.hub) |
e1632170 | 714 | #define uv_cpu_nmi_per(cpu) (per_cpu(uv_cpu_nmi, cpu)) |
0d12ef0c MT |
715 | #define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub) |
716 | ||
717 | /* uv_cpu_nmi_states */ | |
718 | #define UV_NMI_STATE_OUT 0 | |
719 | #define UV_NMI_STATE_IN 1 | |
720 | #define UV_NMI_STATE_DUMP 2 | |
721 | #define UV_NMI_STATE_DUMP_DONE 3 | |
722 | ||
7f1baa06 MT |
723 | /* Update SCIR state */ |
724 | static inline void uv_set_scir_bits(unsigned char value) | |
725 | { | |
d38bb135 MT |
726 | if (uv_scir_info->state != value) { |
727 | uv_scir_info->state = value; | |
728 | uv_write_local_mmr8(uv_scir_info->offset, value); | |
7f1baa06 MT |
729 | } |
730 | } | |
66666e50 | 731 | |
39d30770 MT |
732 | static inline unsigned long uv_scir_offset(int apicid) |
733 | { | |
734 | return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f); | |
735 | } | |
736 | ||
7f1baa06 MT |
737 | static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) |
738 | { | |
d38bb135 | 739 | if (uv_cpu_scir_info(cpu)->state != value) { |
39d30770 | 740 | uv_write_global_mmr8(uv_cpu_to_pnode(cpu), |
d38bb135 MT |
741 | uv_cpu_scir_info(cpu)->offset, value); |
742 | uv_cpu_scir_info(cpu)->state = value; | |
7f1baa06 MT |
743 | } |
744 | } | |
952cf6d7 | 745 | |
8191c9f6 | 746 | extern unsigned int uv_apicid_hibits; |
56abcf24 JS |
747 | static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode) |
748 | { | |
8191c9f6 | 749 | apicid |= uv_apicid_hibits; |
56abcf24 JS |
750 | return (1UL << UVH_IPI_INT_SEND_SHFT) | |
751 | ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | | |
752 | (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | | |
753 | (vector << UVH_IPI_INT_VECTOR_SHFT); | |
754 | } | |
755 | ||
66666e50 JS |
756 | static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) |
757 | { | |
758 | unsigned long val; | |
02dd0a06 RH |
759 | unsigned long dmode = dest_Fixed; |
760 | ||
761 | if (vector == NMI_VECTOR) | |
762 | dmode = dest_NMI; | |
66666e50 | 763 | |
56abcf24 | 764 | val = uv_hub_ipi_value(apicid, vector, dmode); |
66666e50 JS |
765 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
766 | } | |
767 | ||
7a1110e8 JS |
768 | /* |
769 | * Get the minimum revision number of the hub chips within the partition. | |
eb1e3461 | 770 | * (See UVx_HUB_REVISION_BASE above for specific values.) |
7a1110e8 JS |
771 | */ |
772 | static inline int uv_get_min_hub_revision_id(void) | |
773 | { | |
2a919596 | 774 | return uv_hub_info->hub_revision; |
7a1110e8 JS |
775 | } |
776 | ||
bc5d9940 | 777 | #endif /* CONFIG_X86_64 */ |
7f1baa06 | 778 | #endif /* _ASM_X86_UV_UV_HUB_H */ |