Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc
[linux-2.6-block.git] / arch / x86 / include / asm / rwsem.h
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1da177e4
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1/* rwsem.h: R/W semaphores implemented using XADD/CMPXCHG for i486+
2 *
3 * Written by David Howells (dhowells@redhat.com).
4 *
99122a3f 5 * Derived from asm-x86/semaphore.h
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6 *
7 *
8 * The MSW of the count is the negated number of active writers and waiting
9 * lockers, and the LSW is the total number of active locks
10 *
11 * The lock count is initialized to 0 (no active and no waiting lockers).
12 *
13 * When a writer subtracts WRITE_BIAS, it'll get 0xffff0001 for the case of an
14 * uncontended lock. This can be determined because XADD returns the old value.
15 * Readers increment by 1 and see a positive value when uncontended, negative
16 * if there are writers (and maybe) readers waiting (in which case it goes to
17 * sleep).
18 *
19 * The value of WAITING_BIAS supports up to 32766 waiting processes. This can
20 * be extended to 65534 by manually checking the whole MSW rather than relying
21 * on the S flag.
22 *
23 * The value of ACTIVE_BIAS supports up to 65535 active processes.
24 *
25 * This should be totally fair - if anything is waiting, a process that wants a
26 * lock will go to the back of the queue. When the currently active lock is
27 * released, if there's a writer at the front of the queue, then that and only
6a6256f9 28 * that will be woken up; if there's a bunch of consecutive readers at the
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29 * front, then they'll all be woken up, but no other readers will be.
30 */
31
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32#ifndef _ASM_X86_RWSEM_H
33#define _ASM_X86_RWSEM_H
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34
35#ifndef _LINUX_RWSEM_H
36#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
37#endif
38
39#ifdef __KERNEL__
1838ef1d 40#include <asm/asm.h>
1da177e4 41
1da177e4 42/*
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43 * The bias values and the counter type limits the number of
44 * potential readers/writers to 32767 for 32 bits and 2147483647
45 * for 64 bits.
1da177e4 46 */
6e5609a9 47
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48#ifdef CONFIG_X86_64
49# define RWSEM_ACTIVE_MASK 0xffffffffL
50#else
51# define RWSEM_ACTIVE_MASK 0x0000ffffL
52#endif
53
54#define RWSEM_UNLOCKED_VALUE 0x00000000L
55#define RWSEM_ACTIVE_BIAS 0x00000001L
56#define RWSEM_WAITING_BIAS (-RWSEM_ACTIVE_MASK-1)
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57#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
58#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
6e5609a9 59
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60/*
61 * lock for reading
62 */
63static inline void __down_read(struct rw_semaphore *sem)
64{
6e5609a9 65 asm volatile("# beginning down_read\n\t"
1838ef1d 66 LOCK_PREFIX _ASM_INC "(%1)\n\t"
b4bcb4c2 67 /* adds 0x00000001 */
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68 " jns 1f\n"
69 " call call_rwsem_down_read_failed\n"
70 "1:\n\t"
71 "# ending down_read\n\t"
72 : "+m" (sem->count)
73 : "a" (sem)
74 : "memory", "cc");
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75}
76
77/*
78 * trylock for reading -- returns 1 if successful, 0 if contention
79 */
80static inline int __down_read_trylock(struct rw_semaphore *sem)
81{
bde11efb 82 long result, tmp;
6e5609a9 83 asm volatile("# beginning __down_read_trylock\n\t"
59c33fa7 84 " mov %0,%1\n\t"
6e5609a9 85 "1:\n\t"
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86 " mov %1,%2\n\t"
87 " add %3,%2\n\t"
6e5609a9 88 " jle 2f\n\t"
59c33fa7 89 LOCK_PREFIX " cmpxchg %2,%0\n\t"
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90 " jnz 1b\n\t"
91 "2:\n\t"
92 "# ending __down_read_trylock\n\t"
93 : "+m" (sem->count), "=&a" (result), "=&r" (tmp)
94 : "i" (RWSEM_ACTIVE_READ_BIAS)
95 : "memory", "cc");
96 return result >= 0 ? 1 : 0;
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97}
98
99/*
100 * lock for writing
101 */
4ea2176d 102static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
1da177e4 103{
bde11efb 104 long tmp;
6e5609a9 105 asm volatile("# beginning down_write\n\t"
59c33fa7 106 LOCK_PREFIX " xadd %1,(%2)\n\t"
b4bcb4c2 107 /* adds 0xffff0001, returns the old value */
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108 " test " __ASM_SEL(%w1,%k1) "," __ASM_SEL(%w1,%k1) "\n\t"
109 /* was the active mask 0 before? */
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110 " jz 1f\n"
111 " call call_rwsem_down_write_failed\n"
112 "1:\n"
113 "# ending down_write"
114 : "+m" (sem->count), "=d" (tmp)
b4bcb4c2 115 : "a" (sem), "1" (RWSEM_ACTIVE_WRITE_BIAS)
6e5609a9 116 : "memory", "cc");
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117}
118
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119static inline void __down_write(struct rw_semaphore *sem)
120{
121 __down_write_nested(sem, 0);
122}
123
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124/*
125 * trylock for writing -- returns 1 if successful, 0 if contention
126 */
127static inline int __down_write_trylock(struct rw_semaphore *sem)
128{
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129 long result, tmp;
130 asm volatile("# beginning __down_write_trylock\n\t"
131 " mov %0,%1\n\t"
132 "1:\n\t"
133 " test " __ASM_SEL(%w1,%k1) "," __ASM_SEL(%w1,%k1) "\n\t"
134 /* was the active mask 0 before? */
135 " jnz 2f\n\t"
136 " mov %1,%2\n\t"
137 " add %3,%2\n\t"
138 LOCK_PREFIX " cmpxchg %2,%0\n\t"
139 " jnz 1b\n\t"
140 "2:\n\t"
141 " sete %b1\n\t"
142 " movzbl %b1, %k1\n\t"
143 "# ending __down_write_trylock\n\t"
144 : "+m" (sem->count), "=&a" (result), "=&r" (tmp)
145 : "er" (RWSEM_ACTIVE_WRITE_BIAS)
146 : "memory", "cc");
147 return result;
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148}
149
150/*
151 * unlock after reading
152 */
153static inline void __up_read(struct rw_semaphore *sem)
154{
bde11efb 155 long tmp;
6e5609a9 156 asm volatile("# beginning __up_read\n\t"
59c33fa7 157 LOCK_PREFIX " xadd %1,(%2)\n\t"
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158 /* subtracts 1, returns the old value */
159 " jns 1f\n\t"
b4bcb4c2 160 " call call_rwsem_wake\n" /* expects old value in %edx */
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161 "1:\n"
162 "# ending __up_read\n"
163 : "+m" (sem->count), "=d" (tmp)
b4bcb4c2 164 : "a" (sem), "1" (-RWSEM_ACTIVE_READ_BIAS)
6e5609a9 165 : "memory", "cc");
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166}
167
168/*
169 * unlock after writing
170 */
171static inline void __up_write(struct rw_semaphore *sem)
172{
bde11efb 173 long tmp;
6e5609a9 174 asm volatile("# beginning __up_write\n\t"
59c33fa7 175 LOCK_PREFIX " xadd %1,(%2)\n\t"
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176 /* subtracts 0xffff0001, returns the old value */
177 " jns 1f\n\t"
b4bcb4c2 178 " call call_rwsem_wake\n" /* expects old value in %edx */
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179 "1:\n\t"
180 "# ending __up_write\n"
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181 : "+m" (sem->count), "=d" (tmp)
182 : "a" (sem), "1" (-RWSEM_ACTIVE_WRITE_BIAS)
183 : "memory", "cc");
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184}
185
186/*
187 * downgrade write lock to read lock
188 */
189static inline void __downgrade_write(struct rw_semaphore *sem)
190{
6e5609a9 191 asm volatile("# beginning __downgrade_write\n\t"
1838ef1d 192 LOCK_PREFIX _ASM_ADD "%2,(%1)\n\t"
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193 /*
194 * transitions 0xZZZZ0001 -> 0xYYYY0001 (i386)
195 * 0xZZZZZZZZ00000001 -> 0xYYYYYYYY00000001 (x86_64)
196 */
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197 " jns 1f\n\t"
198 " call call_rwsem_downgrade_wake\n"
199 "1:\n\t"
200 "# ending __downgrade_write\n"
201 : "+m" (sem->count)
0d1622d7 202 : "a" (sem), "er" (-RWSEM_WAITING_BIAS)
6e5609a9 203 : "memory", "cc");
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204}
205
206/*
207 * implement atomic add functionality
208 */
bde11efb 209static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
1da177e4 210{
1838ef1d 211 asm volatile(LOCK_PREFIX _ASM_ADD "%1,%0"
6e5609a9 212 : "+m" (sem->count)
1838ef1d 213 : "er" (delta));
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214}
215
216/*
217 * implement exchange and add functionality
218 */
bde11efb 219static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
1da177e4 220{
8b8bc2f7 221 return delta + xadd(&sem->count, delta);
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222}
223
224#endif /* __KERNEL__ */
1965aae3 225#endif /* _ASM_X86_RWSEM_H */