projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 1965aae3 PA |
1 | #ifndef _ASM_X86_KVM_H |
| 2 | #define _ASM_X86_KVM_H | |
| f6a40e3b JY |
3 | |
| 4 | /* | |
| 5 | * KVM x86 specific structures and definitions | |
| 6 | * | |
| 7 | */ | |
| 8 | ||
| cef37678 | 9 | #include <linux/types.h> |
| f6a40e3b JY |
10 | #include <linux/ioctl.h> |
| 11 | ||
| 7a0eb196 AK |
12 | /* Select x86 specific features in <linux/kvm.h> */ |
| 13 | #define __KVM_HAVE_PIT | |
| 14 | #define __KVM_HAVE_IOAPIC | |
| 15 | #define __KVM_HAVE_DEVICE_ASSIGNMENT | |
| 16 | #define __KVM_HAVE_MSI | |
| 17 | #define __KVM_HAVE_USER_NMI | |
| 91b2ae77 | 18 | #define __KVM_HAVE_GUEST_DEBUG |
| d510d6cc | 19 | #define __KVM_HAVE_MSIX |
| 890ca9ae | 20 | #define __KVM_HAVE_MCE |
| e9f42757 | 21 | #define __KVM_HAVE_PIT_STATE2 |
| 7a0eb196 | 22 | |
| 244d57ec JY |
23 | /* Architectural interrupt line count. */ |
| 24 | #define KVM_NR_INTERRUPTS 256 | |
| 25 | ||
| f6a40e3b JY |
26 | struct kvm_memory_alias { |
| 27 | __u32 slot; /* this has a different namespace than memory slots */ | |
| 28 | __u32 flags; | |
| 29 | __u64 guest_phys_addr; | |
| 30 | __u64 memory_size; | |
| 31 | __u64 target_phys_addr; | |
| 32 | }; | |
| 33 | ||
| da1386a5 JY |
34 | /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */ |
| 35 | struct kvm_pic_state { | |
| 36 | __u8 last_irr; /* edge detection */ | |
| 37 | __u8 irr; /* interrupt request register */ | |
| 38 | __u8 imr; /* interrupt mask register */ | |
| 39 | __u8 isr; /* interrupt service register */ | |
| 40 | __u8 priority_add; /* highest irq priority */ | |
| 41 | __u8 irq_base; | |
| 42 | __u8 read_reg_select; | |
| 43 | __u8 poll; | |
| 44 | __u8 special_mask; | |
| 45 | __u8 init_state; | |
| 46 | __u8 auto_eoi; | |
| 47 | __u8 rotate_on_auto_eoi; | |
| 48 | __u8 special_fully_nested_mode; | |
| 49 | __u8 init4; /* true if 4 byte init */ | |
| 50 | __u8 elcr; /* PIIX edge/trigger selection */ | |
| 51 | __u8 elcr_mask; | |
| 52 | }; | |
| 53 | ||
| 54 | #define KVM_IOAPIC_NUM_PINS 24 | |
| 55 | struct kvm_ioapic_state { | |
| 56 | __u64 base_address; | |
| 57 | __u32 ioregsel; | |
| 58 | __u32 id; | |
| 59 | __u32 irr; | |
| 60 | __u32 pad; | |
| 61 | union { | |
| 62 | __u64 bits; | |
| 63 | struct { | |
| 64 | __u8 vector; | |
| 65 | __u8 delivery_mode:3; | |
| 66 | __u8 dest_mode:1; | |
| 67 | __u8 delivery_status:1; | |
| 68 | __u8 polarity:1; | |
| 69 | __u8 remote_irr:1; | |
| 70 | __u8 trig_mode:1; | |
| 71 | __u8 mask:1; | |
| 72 | __u8 reserve:7; | |
| 73 | __u8 reserved[4]; | |
| 74 | __u8 dest_id; | |
| 75 | } fields; | |
| 76 | } redirtbl[KVM_IOAPIC_NUM_PINS]; | |
| 77 | }; | |
| 78 | ||
| 79 | #define KVM_IRQCHIP_PIC_MASTER 0 | |
| 80 | #define KVM_IRQCHIP_PIC_SLAVE 1 | |
| 81 | #define KVM_IRQCHIP_IOAPIC 2 | |
| 3e71f88b | 82 | #define KVM_NR_IRQCHIPS 3 |
| da1386a5 | 83 | |
| 19d30b16 JY |
84 | /* for KVM_GET_REGS and KVM_SET_REGS */ |
| 85 | struct kvm_regs { | |
| 86 | /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ | |
| 87 | __u64 rax, rbx, rcx, rdx; | |
| 88 | __u64 rsi, rdi, rsp, rbp; | |
| 89 | __u64 r8, r9, r10, r11; | |
| 90 | __u64 r12, r13, r14, r15; | |
| 91 | __u64 rip, rflags; | |
| 92 | }; | |
| 93 | ||
| d9ecf928 JY |
94 | /* for KVM_GET_LAPIC and KVM_SET_LAPIC */ |
| 95 | #define KVM_APIC_REG_SIZE 0x400 | |
| 96 | struct kvm_lapic_state { | |
| 97 | char regs[KVM_APIC_REG_SIZE]; | |
| 98 | }; | |
| 99 | ||
| 3a56b201 JY |
100 | struct kvm_segment { |
| 101 | __u64 base; | |
| 102 | __u32 limit; | |
| 103 | __u16 selector; | |
| 104 | __u8 type; | |
| 105 | __u8 present, dpl, db, s, l, g, avl; | |
| 106 | __u8 unusable; | |
| 107 | __u8 padding; | |
| 108 | }; | |
| 109 | ||
| 110 | struct kvm_dtable { | |
| 111 | __u64 base; | |
| 112 | __u16 limit; | |
| 113 | __u16 padding[3]; | |
| 114 | }; | |
| 115 | ||
| 116 | ||
| 244d57ec JY |
117 | /* for KVM_GET_SREGS and KVM_SET_SREGS */ |
| 118 | struct kvm_sregs { | |
| 119 | /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */ | |
| 120 | struct kvm_segment cs, ds, es, fs, gs, ss; | |
| 121 | struct kvm_segment tr, ldt; | |
| 122 | struct kvm_dtable gdt, idt; | |
| 123 | __u64 cr0, cr2, cr3, cr4, cr8; | |
| 124 | __u64 efer; | |
| 125 | __u64 apic_base; | |
| 126 | __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64]; | |
| 127 | }; | |
| 128 | ||
| 6f723c79 CE |
129 | /* for KVM_GET_FPU and KVM_SET_FPU */ |
| 130 | struct kvm_fpu { | |
| 131 | __u8 fpr[8][16]; | |
| 132 | __u16 fcw; | |
| 133 | __u16 fsw; | |
| 134 | __u8 ftwx; /* in fxsave format */ | |
| 135 | __u8 pad1; | |
| 136 | __u16 last_opcode; | |
| 137 | __u64 last_ip; | |
| 138 | __u64 last_dp; | |
| 139 | __u8 xmm[16][16]; | |
| 140 | __u32 mxcsr; | |
| 141 | __u32 pad2; | |
| 142 | }; | |
| 143 | ||
| 244d57ec JY |
144 | struct kvm_msr_entry { |
| 145 | __u32 index; | |
| 146 | __u32 reserved; | |
| 147 | __u64 data; | |
| 148 | }; | |
| 149 | ||
| 150 | /* for KVM_GET_MSRS and KVM_SET_MSRS */ | |
| 151 | struct kvm_msrs { | |
| 152 | __u32 nmsrs; /* number of msrs in entries */ | |
| 153 | __u32 pad; | |
| 154 | ||
| 155 | struct kvm_msr_entry entries[0]; | |
| 156 | }; | |
| 157 | ||
| 158 | /* for KVM_GET_MSR_INDEX_LIST */ | |
| 159 | struct kvm_msr_list { | |
| 160 | __u32 nmsrs; /* number of msrs in entries */ | |
| 161 | __u32 indices[0]; | |
| 162 | }; | |
| 163 | ||
| 164 | ||
| a162dd58 JY |
165 | struct kvm_cpuid_entry { |
| 166 | __u32 function; | |
| 167 | __u32 eax; | |
| 168 | __u32 ebx; | |
| 169 | __u32 ecx; | |
| 170 | __u32 edx; | |
| 171 | __u32 padding; | |
| 172 | }; | |
| 173 | ||
| 174 | /* for KVM_SET_CPUID */ | |
| 175 | struct kvm_cpuid { | |
| 176 | __u32 nent; | |
| 177 | __u32 padding; | |
| 178 | struct kvm_cpuid_entry entries[0]; | |
| 179 | }; | |
| 180 | ||
| 07716717 DK |
181 | struct kvm_cpuid_entry2 { |
| 182 | __u32 function; | |
| 183 | __u32 index; | |
| 184 | __u32 flags; | |
| 185 | __u32 eax; | |
| 186 | __u32 ebx; | |
| 187 | __u32 ecx; | |
| 188 | __u32 edx; | |
| 189 | __u32 padding[3]; | |
| 190 | }; | |
| 191 | ||
| 192 | #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1 | |
| 193 | #define KVM_CPUID_FLAG_STATEFUL_FUNC 2 | |
| 194 | #define KVM_CPUID_FLAG_STATE_READ_NEXT 4 | |
| 195 | ||
| 196 | /* for KVM_SET_CPUID2 */ | |
| 197 | struct kvm_cpuid2 { | |
| 198 | __u32 nent; | |
| 199 | __u32 padding; | |
| 200 | struct kvm_cpuid_entry2 entries[0]; | |
| 201 | }; | |
| a162dd58 | 202 | |
| e0f63cb9 SY |
203 | /* for KVM_GET_PIT and KVM_SET_PIT */ |
| 204 | struct kvm_pit_channel_state { | |
| 205 | __u32 count; /* can be 65536 */ | |
| 206 | __u16 latched_count; | |
| 207 | __u8 count_latched; | |
| 208 | __u8 status_latched; | |
| 209 | __u8 status; | |
| 210 | __u8 read_state; | |
| 211 | __u8 write_state; | |
| 212 | __u8 write_latch; | |
| 213 | __u8 rw_mode; | |
| 214 | __u8 mode; | |
| 215 | __u8 bcd; | |
| 216 | __u8 gate; | |
| 217 | __s64 count_load_time; | |
| 218 | }; | |
| 219 | ||
| d0bfb940 JK |
220 | struct kvm_debug_exit_arch { |
| 221 | __u32 exception; | |
| 222 | __u32 pad; | |
| 223 | __u64 pc; | |
| 224 | __u64 dr6; | |
| 225 | __u64 dr7; | |
| 226 | }; | |
| 227 | ||
| 228 | #define KVM_GUESTDBG_USE_SW_BP 0x00010000 | |
| 229 | #define KVM_GUESTDBG_USE_HW_BP 0x00020000 | |
| 230 | #define KVM_GUESTDBG_INJECT_DB 0x00040000 | |
| 231 | #define KVM_GUESTDBG_INJECT_BP 0x00080000 | |
| 232 | ||
| 233 | /* for KVM_SET_GUEST_DEBUG */ | |
| 234 | struct kvm_guest_debug_arch { | |
| 235 | __u64 debugreg[8]; | |
| 236 | }; | |
| 237 | ||
| e0f63cb9 SY |
238 | struct kvm_pit_state { |
| 239 | struct kvm_pit_channel_state channels[3]; | |
| 240 | }; | |
| 52d939a0 | 241 | |
| e9f42757 BK |
242 | #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001 |
| 243 | ||
| 244 | struct kvm_pit_state2 { | |
| 245 | struct kvm_pit_channel_state channels[3]; | |
| 246 | __u32 flags; | |
| 247 | __u32 reserved[9]; | |
| 248 | }; | |
| 249 | ||
| 52d939a0 MT |
250 | struct kvm_reinject_control { |
| 251 | __u8 pit_reinject; | |
| 252 | __u8 reserved[31]; | |
| 253 | }; | |
| 1965aae3 | 254 | #endif /* _ASM_X86_KVM_H */ |