[linux-2.6-block.git] / arch / x86 / include / asm / cpufeature.h

#ifndef _ASM_X86_CPUFEATURE_H
#define _ASM_X86_CPUFEATURE_H

#include <asm/processor.h>

#if defined(__KERNEL__) && !defined(__ASSEMBLY__)

#include <asm/asm.h>
#include <linux/bitops.h>

enum cpuid_leafs
{
	CPUID_1_EDX		= 0,
	CPUID_8000_0001_EDX,
	CPUID_8086_0001_EDX,
	CPUID_LNX_1,
	CPUID_1_ECX,
	CPUID_C000_0001_EDX,
	CPUID_8000_0001_ECX,
	CPUID_LNX_2,
	CPUID_LNX_3,
	CPUID_7_0_EBX,
	CPUID_D_1_EAX,
	CPUID_F_0_EDX,
	CPUID_F_1_EDX,
	CPUID_8000_0008_EBX,
	CPUID_6_EAX,
	CPUID_8000_000A_EDX,
	CPUID_7_ECX,
};

#ifdef CONFIG_X86_FEATURE_NAMES
extern const char * const x86_cap_flags[NCAPINTS*32];
extern const char * const x86_power_flags[32];
#define X86_CAP_FMT "%s"
#define x86_cap_flag(flag) x86_cap_flags[flag]
#else
#define X86_CAP_FMT "%d:%d"
#define x86_cap_flag(flag) ((flag) >> 5), ((flag) & 31)
#endif

/*
 * In order to save room, we index into this array by doing
 * X86_BUG_<name> - NCAPINTS*32.
 */
extern const char * const x86_bug_flags[NBUGINTS*32];

#define test_cpu_cap(c, bit)						\
	 test_bit(bit, (unsigned long *)((c)->x86_capability))

#define REQUIRED_MASK_BIT_SET(bit)					\
	 ( (((bit)>>5)==0  && (1UL<<((bit)&31) & REQUIRED_MASK0 )) ||	\
	   (((bit)>>5)==1  && (1UL<<((bit)&31) & REQUIRED_MASK1 )) ||	\
	   (((bit)>>5)==2  && (1UL<<((bit)&31) & REQUIRED_MASK2 )) ||	\
	   (((bit)>>5)==3  && (1UL<<((bit)&31) & REQUIRED_MASK3 )) ||	\
	   (((bit)>>5)==4  && (1UL<<((bit)&31) & REQUIRED_MASK4 )) ||	\
	   (((bit)>>5)==5  && (1UL<<((bit)&31) & REQUIRED_MASK5 )) ||	\
	   (((bit)>>5)==6  && (1UL<<((bit)&31) & REQUIRED_MASK6 )) ||	\
	   (((bit)>>5)==7  && (1UL<<((bit)&31) & REQUIRED_MASK7 )) ||	\
	   (((bit)>>5)==8  && (1UL<<((bit)&31) & REQUIRED_MASK8 )) ||	\
	   (((bit)>>5)==9  && (1UL<<((bit)&31) & REQUIRED_MASK9 )) ||	\
	   (((bit)>>5)==10 && (1UL<<((bit)&31) & REQUIRED_MASK10)) ||	\
	   (((bit)>>5)==11 && (1UL<<((bit)&31) & REQUIRED_MASK11)) ||	\
	   (((bit)>>5)==12 && (1UL<<((bit)&31) & REQUIRED_MASK12)) ||	\
	   (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK13)) ||	\
	   (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK14)) ||	\
	   (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK15)) ||	\
	   (((bit)>>5)==14 && (1UL<<((bit)&31) & REQUIRED_MASK16)) )

#define DISABLED_MASK_BIT_SET(bit)					\
	 ( (((bit)>>5)==0  && (1UL<<((bit)&31) & DISABLED_MASK0 )) ||	\
	   (((bit)>>5)==1  && (1UL<<((bit)&31) & DISABLED_MASK1 )) ||	\
	   (((bit)>>5)==2  && (1UL<<((bit)&31) & DISABLED_MASK2 )) ||	\
	   (((bit)>>5)==3  && (1UL<<((bit)&31) & DISABLED_MASK3 )) ||	\
	   (((bit)>>5)==4  && (1UL<<((bit)&31) & DISABLED_MASK4 )) ||	\
	   (((bit)>>5)==5  && (1UL<<((bit)&31) & DISABLED_MASK5 )) ||	\
	   (((bit)>>5)==6  && (1UL<<((bit)&31) & DISABLED_MASK6 )) ||	\
	   (((bit)>>5)==7  && (1UL<<((bit)&31) & DISABLED_MASK7 )) ||	\
	   (((bit)>>5)==8  && (1UL<<((bit)&31) & DISABLED_MASK8 )) ||	\
	   (((bit)>>5)==9  && (1UL<<((bit)&31) & DISABLED_MASK9 )) ||	\
	   (((bit)>>5)==10 && (1UL<<((bit)&31) & DISABLED_MASK10)) ||	\
	   (((bit)>>5)==11 && (1UL<<((bit)&31) & DISABLED_MASK11)) ||	\
	   (((bit)>>5)==12 && (1UL<<((bit)&31) & DISABLED_MASK12)) ||	\
	   (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK13)) ||	\
	   (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK14)) ||	\
	   (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK15)) ||	\
	   (((bit)>>5)==14 && (1UL<<((bit)&31) & DISABLED_MASK16)) )

#define cpu_has(c, bit)							\
	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :	\
	 test_cpu_cap(c, bit))

#define this_cpu_has(bit)						\
	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : 	\
	 x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability))

/*
 * This macro is for detection of features which need kernel
 * infrastructure to be used.  It may *not* directly test the CPU
 * itself.  Use the cpu_has() family if you want true runtime
 * testing of CPU features, like in hypervisor code where you are
 * supporting a possible guest feature where host support for it
 * is not relevant.
 */
#define cpu_feature_enabled(bit)	\
	(__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : static_cpu_has(bit))

#define boot_cpu_has(bit)	cpu_has(&boot_cpu_data, bit)

#define set_cpu_cap(c, bit)	set_bit(bit, (unsigned long *)((c)->x86_capability))
#define clear_cpu_cap(c, bit)	clear_bit(bit, (unsigned long *)((c)->x86_capability))
#define setup_clear_cpu_cap(bit) do { \
	clear_cpu_cap(&boot_cpu_data, bit);	\
	set_bit(bit, (unsigned long *)cpu_caps_cleared); \
} while (0)
#define setup_force_cpu_cap(bit) do { \
	set_cpu_cap(&boot_cpu_data, bit);	\
	set_bit(bit, (unsigned long *)cpu_caps_set);	\
} while (0)

#define cpu_has_fpu		boot_cpu_has(X86_FEATURE_FPU)
#define cpu_has_pse		boot_cpu_has(X86_FEATURE_PSE)
#define cpu_has_tsc		boot_cpu_has(X86_FEATURE_TSC)
#define cpu_has_pge		boot_cpu_has(X86_FEATURE_PGE)
#define cpu_has_apic		boot_cpu_has(X86_FEATURE_APIC)
#define cpu_has_fxsr		boot_cpu_has(X86_FEATURE_FXSR)
#define cpu_has_xmm		boot_cpu_has(X86_FEATURE_XMM)
#define cpu_has_xmm2		boot_cpu_has(X86_FEATURE_XMM2)
#define cpu_has_aes		boot_cpu_has(X86_FEATURE_AES)
#define cpu_has_avx		boot_cpu_has(X86_FEATURE_AVX)
#define cpu_has_avx2		boot_cpu_has(X86_FEATURE_AVX2)
#define cpu_has_clflush		boot_cpu_has(X86_FEATURE_CLFLUSH)
#define cpu_has_gbpages		boot_cpu_has(X86_FEATURE_GBPAGES)
#define cpu_has_arch_perfmon	boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
#define cpu_has_pat		boot_cpu_has(X86_FEATURE_PAT)
#define cpu_has_x2apic		boot_cpu_has(X86_FEATURE_X2APIC)
#define cpu_has_xsave		boot_cpu_has(X86_FEATURE_XSAVE)
#define cpu_has_xsaves		boot_cpu_has(X86_FEATURE_XSAVES)
#define cpu_has_osxsave		boot_cpu_has(X86_FEATURE_OSXSAVE)
#define cpu_has_hypervisor	boot_cpu_has(X86_FEATURE_HYPERVISOR)
/*
 * Do not add any more of those clumsy macros - use static_cpu_has() for
 * fast paths and boot_cpu_has() otherwise!
 */

#if defined(CC_HAVE_ASM_GOTO) && defined(CONFIG_X86_FAST_FEATURE_TESTS)
/*
 * Static testing of CPU features.  Used the same as boot_cpu_has().
 * These will statically patch the target code for additional
 * performance.
 */
static __always_inline __pure bool _static_cpu_has(u16 bit)
{
		asm_volatile_goto("1: jmp 6f\n"
			 "2:\n"
			 ".skip -(((5f-4f) - (2b-1b)) > 0) * "
			         "((5f-4f) - (2b-1b)),0x90\n"
			 "3:\n"
			 ".section .altinstructions,\"a\"\n"
			 " .long 1b - .\n"		/* src offset */
			 " .long 4f - .\n"		/* repl offset */
			 " .word %P1\n"			/* always replace */
			 " .byte 3b - 1b\n"		/* src len */
			 " .byte 5f - 4f\n"		/* repl len */
			 " .byte 3b - 2b\n"		/* pad len */
			 ".previous\n"
			 ".section .altinstr_replacement,\"ax\"\n"
			 "4: jmp %l[t_no]\n"
			 "5:\n"
			 ".previous\n"
			 ".section .altinstructions,\"a\"\n"
			 " .long 1b - .\n"		/* src offset */
			 " .long 0\n"			/* no replacement */
			 " .word %P0\n"			/* feature bit */
			 " .byte 3b - 1b\n"		/* src len */
			 " .byte 0\n"			/* repl len */
			 " .byte 0\n"			/* pad len */
			 ".previous\n"
			 ".section .altinstr_aux,\"ax\"\n"
			 "6:\n"
			 " testb %[bitnum],%[cap_byte]\n"
			 " jnz %l[t_yes]\n"
			 " jmp %l[t_no]\n"
			 ".previous\n"
			 : : "i" (bit), "i" (X86_FEATURE_ALWAYS),
			     [bitnum] "i" (1 << (bit & 7)),
			     [cap_byte] "m" (((const char *)boot_cpu_data.x86_capability)[bit >> 3])
			 : : t_yes, t_no);
	t_yes:
		return true;
	t_no:
		return false;
}

#define static_cpu_has(bit)					\
(								\
	__builtin_constant_p(boot_cpu_has(bit)) ?		\
		boot_cpu_has(bit) :				\
		_static_cpu_has(bit)				\
)
#else
/*
 * Fall back to dynamic for gcc versions which don't support asm goto. Should be
 * a minority now anyway.
 */
#define static_cpu_has(bit)		boot_cpu_has(bit)
#endif

#define cpu_has_bug(c, bit)		cpu_has(c, (bit))
#define set_cpu_bug(c, bit)		set_cpu_cap(c, (bit))
#define clear_cpu_bug(c, bit)		clear_cpu_cap(c, (bit))

#define static_cpu_has_bug(bit)		static_cpu_has((bit))
#define boot_cpu_has_bug(bit)		cpu_has_bug(&boot_cpu_data, (bit))

#define MAX_CPU_FEATURES		(NCAPINTS * 32)
#define cpu_have_feature		boot_cpu_has

#define CPU_FEATURE_TYPEFMT		"x86,ven%04Xfam%04Xmod%04X"
#define CPU_FEATURE_TYPEVAL		boot_cpu_data.x86_vendor, boot_cpu_data.x86, \
					boot_cpu_data.x86_model

#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
#endif /* _ASM_X86_CPUFEATURE_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_CPUFEATURE_H
1965aae3 PA	2	#define _ASM_X86_CPUFEATURE_H
7b11fb51	3
cd4d09ec	4	#include <asm/processor.h>
e2604b49	5
fa1408e4 PA	6	#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
fa1408e4 PA	7
a3c8acd0	8	#include <asm/asm.h>
fa1408e4 PA	9	#include <linux/bitops.h>
fa1408e4 PA	10
39c06df4 BP	11	enum cpuid_leafs
	12	{
	13	CPUID_1_EDX = 0,
	14	CPUID_8000_0001_EDX,
	15	CPUID_8086_0001_EDX,
	16	CPUID_LNX_1,
	17	CPUID_1_ECX,
	18	CPUID_C000_0001_EDX,
	19	CPUID_8000_0001_ECX,
	20	CPUID_LNX_2,
	21	CPUID_LNX_3,
	22	CPUID_7_0_EBX,
	23	CPUID_D_1_EAX,
	24	CPUID_F_0_EDX,
	25	CPUID_F_1_EDX,
	26	CPUID_8000_0008_EBX,
	27	CPUID_6_EAX,
	28	CPUID_8000_000A_EDX,
dfb4a70f	29	CPUID_7_ECX,
39c06df4 BP	30	};
39c06df4 BP	31
9def39be	32	#ifdef CONFIG_X86_FEATURE_NAMES
fa1408e4 PA	33	extern const char * const x86_cap_flags[NCAPINTS*32];
fa1408e4 PA	34	extern const char * const x86_power_flags[32];
9def39be JT	35	#define X86_CAP_FMT "%s"
	36	#define x86_cap_flag(flag) x86_cap_flags[flag]
	37	#else
	38	#define X86_CAP_FMT "%d:%d"
	39	#define x86_cap_flag(flag) ((flag) >> 5), ((flag) & 31)
	40	#endif
fa1408e4	41
80a208bd BP	42	/*
	43	* In order to save room, we index into this array by doing
	44	* X86_BUG_<name> - NCAPINTS*32.
	45	*/
	46	extern const char * const x86_bug_flags[NBUGINTS*32];
	47
0f8d2b92 IM	48	#define test_cpu_cap(c, bit) \
	49	test_bit(bit, (unsigned long *)((c)->x86_capability))
	50
349c004e	51	#define REQUIRED_MASK_BIT_SET(bit) \
dfb4a70f DH	52	( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0 )) \|\| \
	53	(((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1 )) \|\| \
	54	(((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2 )) \|\| \
	55	(((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3 )) \|\| \
	56	(((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4 )) \|\| \
	57	(((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5 )) \|\| \
	58	(((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6 )) \|\| \
	59	(((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7 )) \|\| \
	60	(((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8 )) \|\| \
	61	(((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9 )) \|\| \
	62	(((bit)>>5)==10 && (1UL<<((bit)&31) & REQUIRED_MASK10)) \|\| \
	63	(((bit)>>5)==11 && (1UL<<((bit)&31) & REQUIRED_MASK11)) \|\| \
	64	(((bit)>>5)==12 && (1UL<<((bit)&31) & REQUIRED_MASK12)) \|\| \
	65	(((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK13)) \|\| \
	66	(((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK14)) \|\| \
	67	(((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK15)) \|\| \
	68	(((bit)>>5)==14 && (1UL<<((bit)&31) & REQUIRED_MASK16)) )
349c004e	69
381aa07a	70	#define DISABLED_MASK_BIT_SET(bit) \
dfb4a70f DH	71	( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0 )) \|\| \
	72	(((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1 )) \|\| \
	73	(((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2 )) \|\| \
	74	(((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3 )) \|\| \
	75	(((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4 )) \|\| \
	76	(((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5 )) \|\| \
	77	(((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6 )) \|\| \
	78	(((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7 )) \|\| \
	79	(((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8 )) \|\| \
	80	(((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9 )) \|\| \
	81	(((bit)>>5)==10 && (1UL<<((bit)&31) & DISABLED_MASK10)) \|\| \
	82	(((bit)>>5)==11 && (1UL<<((bit)&31) & DISABLED_MASK11)) \|\| \
	83	(((bit)>>5)==12 && (1UL<<((bit)&31) & DISABLED_MASK12)) \|\| \
	84	(((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK13)) \|\| \
	85	(((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK14)) \|\| \
	86	(((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK15)) \|\| \
	87	(((bit)>>5)==14 && (1UL<<((bit)&31) & DISABLED_MASK16)) )
381aa07a	88
349c004e CL	89	#define cpu_has(c, bit) \
349c004e CL	90	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
0f8d2b92 IM	91	test_cpu_cap(c, bit))
0f8d2b92 IM	92
349c004e CL	93	#define this_cpu_has(bit) \
	94	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
	95	x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability))
	96
381aa07a DH	97	/*
	98	* This macro is for detection of features which need kernel
	99	* infrastructure to be used. It may not directly test the CPU
	100	* itself. Use the cpu_has() family if you want true runtime
	101	* testing of CPU features, like in hypervisor code where you are
	102	* supporting a possible guest feature where host support for it
	103	* is not relevant.
	104	*/
	105	#define cpu_feature_enabled(bit) \
f2cc8e07	106	(__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : static_cpu_has(bit))
381aa07a	107
7b11fb51 PA	108	#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
7b11fb51 PA	109
53756d37 JF	110	#define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability))
53756d37 JF	111	#define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability))
7d851c8d AK	112	#define setup_clear_cpu_cap(bit) do { \
7d851c8d AK	113	clear_cpu_cap(&boot_cpu_data, bit); \
3e0c3737	114	set_bit(bit, (unsigned long *)cpu_caps_cleared); \
7d851c8d	115	} while (0)
404ee5b1 AK	116	#define setup_force_cpu_cap(bit) do { \
404ee5b1 AK	117	set_cpu_cap(&boot_cpu_data, bit); \
3e0c3737	118	set_bit(bit, (unsigned long *)cpu_caps_set); \
404ee5b1	119	} while (0)
53756d37	120
7b11fb51	121	#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)
7b11fb51 PA	122	#define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE)
7b11fb51 PA	123	#define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC)
7b11fb51 PA	124	#define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE)
7b11fb51 PA	125	#define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
7b11fb51 PA	126	#define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR)
	127	#define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
	128	#define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2)
54b6a1bd	129	#define cpu_has_aes boot_cpu_has(X86_FEATURE_AES)
66be8951	130	#define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX)
60488010	131	#define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2)
840d2830	132	#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH)
019c3e7c	133	#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
86975101	134	#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
2e5d9c85	135	#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
32e1d0a0	136	#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
f1240c00	137	#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
6229ad27	138	#define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES)
66be8951	139	#define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE)
49ab56ac	140	#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
362f924b	141	/*
bc696ca0	142	* Do not add any more of those clumsy macros - use static_cpu_has() for
362f924b BP	143	* fast paths and boot_cpu_has() otherwise!
362f924b BP	144	*/
7b11fb51	145
a362bf9f	146	#if defined(CC_HAVE_ASM_GOTO) && defined(CONFIG_X86_FAST_FEATURE_TESTS)
a3c8acd0 PA	147	/*
a3c8acd0 PA	148	* Static testing of CPU features. Used the same as boot_cpu_has().
a362bf9f BP	149	* These will statically patch the target code for additional
a362bf9f BP	150	* performance.
a3c8acd0	151	*/
bc696ca0	152	static __always_inline __pure bool _static_cpu_has(u16 bit)
4a90a99c	153	{
2476f2fa	154	asm_volatile_goto("1: jmp 6f\n"
4a90a99c	155	"2:\n"
4332195c BP	156	".skip -(((5f-4f) - (2b-1b)) > 0) * "
	157	"((5f-4f) - (2b-1b)),0x90\n"
	158	"3:\n"
4a90a99c BP	159	".section .altinstructions,\"a\"\n"
4a90a99c BP	160	" .long 1b - .\n" /* src offset */
4332195c	161	" .long 4f - .\n" /* repl offset */
4a90a99c	162	" .word %P1\n" /* always replace */
4332195c BP	163	" .byte 3b - 1b\n" /* src len */
	164	" .byte 5f - 4f\n" /* repl len */
	165	" .byte 3b - 2b\n" /* pad len */
4a90a99c BP	166	".previous\n"
4a90a99c BP	167	".section .altinstr_replacement,\"ax\"\n"
48c7a250	168	"4: jmp %l[t_no]\n"
4332195c	169	"5:\n"
4a90a99c BP	170	".previous\n"
	171	".section .altinstructions,\"a\"\n"
	172	" .long 1b - .\n" /* src offset */
	173	" .long 0\n" /* no replacement */
	174	" .word %P0\n" /* feature bit */
4332195c	175	" .byte 3b - 1b\n" /* src len */
4a90a99c	176	" .byte 0\n" /* repl len */
4332195c	177	" .byte 0\n" /* pad len */
4a90a99c	178	".previous\n"
2476f2fa BG	179	".section .altinstr_aux,\"ax\"\n"
	180	"6:\n"
	181	" testb %[bitnum],%[cap_byte]\n"
	182	" jnz %l[t_yes]\n"
	183	" jmp %l[t_no]\n"
	184	".previous\n"
	185	: : "i" (bit), "i" (X86_FEATURE_ALWAYS),
	186	[bitnum] "i" (1 << (bit & 7)),
	187	[cap_byte] "m" (((const char *)boot_cpu_data.x86_capability)[bit >> 3])
	188	: : t_yes, t_no);
	189	t_yes:
4a90a99c BP	190	return true;
	191	t_no:
	192	return false;
4a90a99c BP	193	}
4a90a99c BP	194
bc696ca0	195	#define static_cpu_has(bit) \
4a90a99c BP	196	( \
	197	__builtin_constant_p(boot_cpu_has(bit)) ? \
	198	boot_cpu_has(bit) : \
bc696ca0	199	_static_cpu_has(bit) \
4a90a99c	200	)
1ba4f22c PA	201	#else
1ba4f22c PA	202	/*
a362bf9f BP	203	* Fall back to dynamic for gcc versions which don't support asm goto. Should be
a362bf9f BP	204	* a minority now anyway.
1ba4f22c	205	*/
4a90a99c	206	#define static_cpu_has(bit) boot_cpu_has(bit)
1ba4f22c	207	#endif
a3c8acd0	208
9b13a93d BP	209	#define cpu_has_bug(c, bit) cpu_has(c, (bit))
	210	#define set_cpu_bug(c, bit) set_cpu_cap(c, (bit))
	211	#define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit))
65fc985b	212
9b13a93d	213	#define static_cpu_has_bug(bit) static_cpu_has((bit))
9b13a93d	214	#define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit))
65fc985b	215
9b13a93d BP	216	#define MAX_CPU_FEATURES (NCAPINTS * 32)
9b13a93d BP	217	#define cpu_have_feature boot_cpu_has
2b9c1f03	218
9b13a93d BP	219	#define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X"
	220	#define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \
	221	boot_cpu_data.x86_model
2b9c1f03	222
fa1408e4	223	#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
1965aae3	224	#endif /* _ASM_X86_CPUFEATURE_H */