[linux-2.6-block.git] / arch / x86 / events / msr.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/perf_event.h>
#include <linux/sysfs.h>
#include <linux/nospec.h>
#include <asm/cpu_device_id.h>
#include "probe.h"

enum perf_msr_id {
	PERF_MSR_TSC			= 0,
	PERF_MSR_APERF			= 1,
	PERF_MSR_MPERF			= 2,
	PERF_MSR_PPERF			= 3,
	PERF_MSR_SMI			= 4,
	PERF_MSR_PTSC			= 5,
	PERF_MSR_IRPERF			= 6,
	PERF_MSR_THERM			= 7,
	PERF_MSR_EVENT_MAX,
};

static bool test_aperfmperf(int idx, void *data)
{
	return boot_cpu_has(X86_FEATURE_APERFMPERF);
}

static bool test_ptsc(int idx, void *data)
{
	return boot_cpu_has(X86_FEATURE_PTSC);
}

static bool test_irperf(int idx, void *data)
{
	return boot_cpu_has(X86_FEATURE_IRPERF);
}

static bool test_therm_status(int idx, void *data)
{
	return boot_cpu_has(X86_FEATURE_DTHERM);
}

static bool test_intel(int idx, void *data)
{
	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
	    boot_cpu_data.x86 != 6)
		return false;

	switch (boot_cpu_data.x86_vfm) {
	case INTEL_NEHALEM:
	case INTEL_NEHALEM_G:
	case INTEL_NEHALEM_EP:
	case INTEL_NEHALEM_EX:

	case INTEL_WESTMERE:
	case INTEL_WESTMERE_EP:
	case INTEL_WESTMERE_EX:

	case INTEL_SANDYBRIDGE:
	case INTEL_SANDYBRIDGE_X:

	case INTEL_IVYBRIDGE:
	case INTEL_IVYBRIDGE_X:

	case INTEL_HASWELL:
	case INTEL_HASWELL_X:
	case INTEL_HASWELL_L:
	case INTEL_HASWELL_G:

	case INTEL_BROADWELL:
	case INTEL_BROADWELL_D:
	case INTEL_BROADWELL_G:
	case INTEL_BROADWELL_X:
	case INTEL_SAPPHIRERAPIDS_X:
	case INTEL_EMERALDRAPIDS_X:
	case INTEL_GRANITERAPIDS_X:
	case INTEL_GRANITERAPIDS_D:

	case INTEL_ATOM_SILVERMONT:
	case INTEL_ATOM_SILVERMONT_D:
	case INTEL_ATOM_AIRMONT:

	case INTEL_ATOM_GOLDMONT:
	case INTEL_ATOM_GOLDMONT_D:
	case INTEL_ATOM_GOLDMONT_PLUS:
	case INTEL_ATOM_TREMONT_D:
	case INTEL_ATOM_TREMONT:
	case INTEL_ATOM_TREMONT_L:

	case INTEL_XEON_PHI_KNL:
	case INTEL_XEON_PHI_KNM:
		if (idx == PERF_MSR_SMI)
			return true;
		break;

	case INTEL_SKYLAKE_L:
	case INTEL_SKYLAKE:
	case INTEL_SKYLAKE_X:
	case INTEL_KABYLAKE_L:
	case INTEL_KABYLAKE:
	case INTEL_COMETLAKE_L:
	case INTEL_COMETLAKE:
	case INTEL_ICELAKE_L:
	case INTEL_ICELAKE:
	case INTEL_ICELAKE_X:
	case INTEL_ICELAKE_D:
	case INTEL_TIGERLAKE_L:
	case INTEL_TIGERLAKE:
	case INTEL_ROCKETLAKE:
	case INTEL_ALDERLAKE:
	case INTEL_ALDERLAKE_L:
	case INTEL_ATOM_GRACEMONT:
	case INTEL_RAPTORLAKE:
	case INTEL_RAPTORLAKE_P:
	case INTEL_RAPTORLAKE_S:
	case INTEL_METEORLAKE:
	case INTEL_METEORLAKE_L:
		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
			return true;
		break;
	}

	return false;
}

PMU_EVENT_ATTR_STRING(tsc,				attr_tsc,		"event=0x00"	);
PMU_EVENT_ATTR_STRING(aperf,				attr_aperf,		"event=0x01"	);
PMU_EVENT_ATTR_STRING(mperf,				attr_mperf,		"event=0x02"	);
PMU_EVENT_ATTR_STRING(pperf,				attr_pperf,		"event=0x03"	);
PMU_EVENT_ATTR_STRING(smi,				attr_smi,		"event=0x04"	);
PMU_EVENT_ATTR_STRING(ptsc,				attr_ptsc,		"event=0x05"	);
PMU_EVENT_ATTR_STRING(irperf,				attr_irperf,		"event=0x06"	);
PMU_EVENT_ATTR_STRING(cpu_thermal_margin,		attr_therm,		"event=0x07"	);
PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot,	attr_therm_snap,	"1"		);
PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit,		attr_therm_unit,	"C"		);

static unsigned long msr_mask;

PMU_EVENT_GROUP(events, aperf);
PMU_EVENT_GROUP(events, mperf);
PMU_EVENT_GROUP(events, pperf);
PMU_EVENT_GROUP(events, smi);
PMU_EVENT_GROUP(events, ptsc);
PMU_EVENT_GROUP(events, irperf);

static struct attribute *attrs_therm[] = {
	&attr_therm.attr.attr,
	&attr_therm_snap.attr.attr,
	&attr_therm_unit.attr.attr,
	NULL,
};

static struct attribute_group group_therm = {
	.name  = "events",
	.attrs = attrs_therm,
};

static struct perf_msr msr[] = {
	[PERF_MSR_TSC]		= { .no_check = true,								},
	[PERF_MSR_APERF]	= { MSR_IA32_APERF,		&group_aperf,		test_aperfmperf,	},
	[PERF_MSR_MPERF]	= { MSR_IA32_MPERF,		&group_mperf,		test_aperfmperf,	},
	[PERF_MSR_PPERF]	= { MSR_PPERF,			&group_pperf,		test_intel,		},
	[PERF_MSR_SMI]		= { MSR_SMI_COUNT,		&group_smi,		test_intel,		},
	[PERF_MSR_PTSC]		= { MSR_F15H_PTSC,		&group_ptsc,		test_ptsc,		},
	[PERF_MSR_IRPERF]	= { MSR_F17H_IRPERF,		&group_irperf,		test_irperf,		},
	[PERF_MSR_THERM]	= { MSR_IA32_THERM_STATUS,	&group_therm,		test_therm_status,	},
};

static struct attribute *events_attrs[] = {
	&attr_tsc.attr.attr,
	NULL,
};

static struct attribute_group events_attr_group = {
	.name = "events",
	.attrs = events_attrs,
};

PMU_FORMAT_ATTR(event, "config:0-63");
static struct attribute *format_attrs[] = {
	&format_attr_event.attr,
	NULL,
};
static struct attribute_group format_attr_group = {
	.name = "format",
	.attrs = format_attrs,
};

static const struct attribute_group *attr_groups[] = {
	&events_attr_group,
	&format_attr_group,
	NULL,
};

static const struct attribute_group *attr_update[] = {
	&group_aperf,
	&group_mperf,
	&group_pperf,
	&group_smi,
	&group_ptsc,
	&group_irperf,
	&group_therm,
	NULL,
};

static int msr_event_init(struct perf_event *event)
{
	u64 cfg = event->attr.config;

	if (event->attr.type != event->pmu->type)
		return -ENOENT;

	/* unsupported modes and filters */
	if (event->attr.sample_period) /* no sampling */
		return -EINVAL;

	if (cfg >= PERF_MSR_EVENT_MAX)
		return -EINVAL;

	cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX);

	if (!(msr_mask & (1 << cfg)))
		return -EINVAL;

	event->hw.idx		= -1;
	event->hw.event_base	= msr[cfg].msr;
	event->hw.config	= cfg;

	return 0;
}

static inline u64 msr_read_counter(struct perf_event *event)
{
	u64 now;

	if (event->hw.event_base)
		rdmsrl(event->hw.event_base, now);
	else
		now = rdtsc_ordered();

	return now;
}

static void msr_event_update(struct perf_event *event)
{
	u64 prev, now;
	s64 delta;

	/* Careful, an NMI might modify the previous event value: */
	prev = local64_read(&event->hw.prev_count);
	do {
		now = msr_read_counter(event);
	} while (!local64_try_cmpxchg(&event->hw.prev_count, &prev, now));

	delta = now - prev;
	if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
		delta = sign_extend64(delta, 31);
		local64_add(delta, &event->count);
	} else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) {
		/* If valid, extract digital readout, otherwise set to -1: */
		now = now & (1ULL << 31) ? (now >> 16) & 0x3f :  -1;
		local64_set(&event->count, now);
	} else {
		local64_add(delta, &event->count);
	}
}

static void msr_event_start(struct perf_event *event, int flags)
{
	u64 now = msr_read_counter(event);

	local64_set(&event->hw.prev_count, now);
}

static void msr_event_stop(struct perf_event *event, int flags)
{
	msr_event_update(event);
}

static void msr_event_del(struct perf_event *event, int flags)
{
	msr_event_stop(event, PERF_EF_UPDATE);
}

static int msr_event_add(struct perf_event *event, int flags)
{
	if (flags & PERF_EF_START)
		msr_event_start(event, flags);

	return 0;
}

static struct pmu pmu_msr = {
	.task_ctx_nr	= perf_sw_context,
	.attr_groups	= attr_groups,
	.event_init	= msr_event_init,
	.add		= msr_event_add,
	.del		= msr_event_del,
	.start		= msr_event_start,
	.stop		= msr_event_stop,
	.read		= msr_event_update,
	.capabilities	= PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
	.attr_update	= attr_update,
};

static int __init msr_init(void)
{
	if (!boot_cpu_has(X86_FEATURE_TSC)) {
		pr_cont("no MSR PMU driver.\n");
		return 0;
	}

	msr_mask = perf_msr_probe(msr, PERF_MSR_EVENT_MAX, true, NULL);

	perf_pmu_register(&pmu_msr, "msr", -1);

	return 0;
}
device_initcall(msr_init);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
b7b7c782	2	#include <linux/perf_event.h>
dde5e720	3	#include <linux/sysfs.h>
06ce6e9b	4	#include <linux/nospec.h>
add69475	5	#include <asm/cpu_device_id.h>
dde5e720	6	#include "probe.h"
b7b7c782 AL	7
	8	enum perf_msr_id {
	9	PERF_MSR_TSC = 0,
	10	PERF_MSR_APERF = 1,
	11	PERF_MSR_MPERF = 2,
	12	PERF_MSR_PPERF = 3,
	13	PERF_MSR_SMI = 4,
8a224261	14	PERF_MSR_PTSC = 5,
aaf24884	15	PERF_MSR_IRPERF = 6,
9ae21dd6	16	PERF_MSR_THERM = 7,
b7b7c782 AL	17	PERF_MSR_EVENT_MAX,
	18	};
	19
dde5e720	20	static bool test_aperfmperf(int idx, void *data)
19b3340c PZ	21	{
	22	return boot_cpu_has(X86_FEATURE_APERFMPERF);
	23	}
	24
dde5e720	25	static bool test_ptsc(int idx, void *data)
8a224261 HR	26	{
	27	return boot_cpu_has(X86_FEATURE_PTSC);
	28	}
	29
dde5e720	30	static bool test_irperf(int idx, void *data)
aaf24884 HR	31	{
	32	return boot_cpu_has(X86_FEATURE_IRPERF);
	33	}
	34
dde5e720	35	static bool test_therm_status(int idx, void *data)
9ae21dd6 SE	36	{
	37	return boot_cpu_has(X86_FEATURE_DTHERM);
	38	}
	39
dde5e720	40	static bool test_intel(int idx, void *data)
19b3340c PZ	41	{
	42	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL \|\|
	43	boot_cpu_data.x86 != 6)
	44	return false;
	45
add69475 TL	46	switch (boot_cpu_data.x86_vfm) {
	47	case INTEL_NEHALEM:
	48	case INTEL_NEHALEM_G:
	49	case INTEL_NEHALEM_EP:
	50	case INTEL_NEHALEM_EX:
	51
	52	case INTEL_WESTMERE:
	53	case INTEL_WESTMERE_EP:
	54	case INTEL_WESTMERE_EX:
	55
	56	case INTEL_SANDYBRIDGE:
	57	case INTEL_SANDYBRIDGE_X:
	58
	59	case INTEL_IVYBRIDGE:
	60	case INTEL_IVYBRIDGE_X:
	61
	62	case INTEL_HASWELL:
	63	case INTEL_HASWELL_X:
	64	case INTEL_HASWELL_L:
	65	case INTEL_HASWELL_G:
	66
	67	case INTEL_BROADWELL:
	68	case INTEL_BROADWELL_D:
	69	case INTEL_BROADWELL_G:
	70	case INTEL_BROADWELL_X:
	71	case INTEL_SAPPHIRERAPIDS_X:
	72	case INTEL_EMERALDRAPIDS_X:
	73	case INTEL_GRANITERAPIDS_X:
	74	case INTEL_GRANITERAPIDS_D:
	75
	76	case INTEL_ATOM_SILVERMONT:
	77	case INTEL_ATOM_SILVERMONT_D:
	78	case INTEL_ATOM_AIRMONT:
	79
	80	case INTEL_ATOM_GOLDMONT:
	81	case INTEL_ATOM_GOLDMONT_D:
	82	case INTEL_ATOM_GOLDMONT_PLUS:
	83	case INTEL_ATOM_TREMONT_D:
	84	case INTEL_ATOM_TREMONT:
	85	case INTEL_ATOM_TREMONT_L:
	86
	87	case INTEL_XEON_PHI_KNL:
	88	case INTEL_XEON_PHI_KNM:
19b3340c PZ	89	if (idx == PERF_MSR_SMI)
	90	return true;
	91	break;
	92
add69475 TL	93	case INTEL_SKYLAKE_L:
	94	case INTEL_SKYLAKE:
	95	case INTEL_SKYLAKE_X:
	96	case INTEL_KABYLAKE_L:
	97	case INTEL_KABYLAKE:
	98	case INTEL_COMETLAKE_L:
	99	case INTEL_COMETLAKE:
	100	case INTEL_ICELAKE_L:
	101	case INTEL_ICELAKE:
	102	case INTEL_ICELAKE_X:
	103	case INTEL_ICELAKE_D:
	104	case INTEL_TIGERLAKE_L:
	105	case INTEL_TIGERLAKE:
	106	case INTEL_ROCKETLAKE:
	107	case INTEL_ALDERLAKE:
	108	case INTEL_ALDERLAKE_L:
	109	case INTEL_ATOM_GRACEMONT:
	110	case INTEL_RAPTORLAKE:
	111	case INTEL_RAPTORLAKE_P:
	112	case INTEL_RAPTORLAKE_S:
	113	case INTEL_METEORLAKE:
	114	case INTEL_METEORLAKE_L:
19b3340c PZ	115	if (idx == PERF_MSR_SMI \|\| idx == PERF_MSR_PPERF)
	116	return true;
	117	break;
	118	}
	119
	120	return false;
	121	}
	122
dde5e720 JO	123	PMU_EVENT_ATTR_STRING(tsc, attr_tsc, "event=0x00" );
	124	PMU_EVENT_ATTR_STRING(aperf, attr_aperf, "event=0x01" );
	125	PMU_EVENT_ATTR_STRING(mperf, attr_mperf, "event=0x02" );
	126	PMU_EVENT_ATTR_STRING(pperf, attr_pperf, "event=0x03" );
	127	PMU_EVENT_ATTR_STRING(smi, attr_smi, "event=0x04" );
	128	PMU_EVENT_ATTR_STRING(ptsc, attr_ptsc, "event=0x05" );
	129	PMU_EVENT_ATTR_STRING(irperf, attr_irperf, "event=0x06" );
	130	PMU_EVENT_ATTR_STRING(cpu_thermal_margin, attr_therm, "event=0x07" );
	131	PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot, attr_therm_snap, "1" );
	132	PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit, attr_therm_unit, "C" );
	133
	134	static unsigned long msr_mask;
	135
	136	PMU_EVENT_GROUP(events, aperf);
	137	PMU_EVENT_GROUP(events, mperf);
	138	PMU_EVENT_GROUP(events, pperf);
	139	PMU_EVENT_GROUP(events, smi);
	140	PMU_EVENT_GROUP(events, ptsc);
	141	PMU_EVENT_GROUP(events, irperf);
	142
	143	static struct attribute *attrs_therm[] = {
	144	&attr_therm.attr.attr,
	145	&attr_therm_snap.attr.attr,
	146	&attr_therm_unit.attr.attr,
	147	NULL,
b7b7c782 AL	148	};
b7b7c782 AL	149
dde5e720 JO	150	static struct attribute_group group_therm = {
	151	.name = "events",
	152	.attrs = attrs_therm,
	153	};
b7b7c782	154
19b3340c	155	static struct perf_msr msr[] = {
dde5e720 JO	156	[PERF_MSR_TSC] = { .no_check = true, },
	157	[PERF_MSR_APERF] = { MSR_IA32_APERF, &group_aperf, test_aperfmperf, },
	158	[PERF_MSR_MPERF] = { MSR_IA32_MPERF, &group_mperf, test_aperfmperf, },
	159	[PERF_MSR_PPERF] = { MSR_PPERF, &group_pperf, test_intel, },
	160	[PERF_MSR_SMI] = { MSR_SMI_COUNT, &group_smi, test_intel, },
	161	[PERF_MSR_PTSC] = { MSR_F15H_PTSC, &group_ptsc, test_ptsc, },
	162	[PERF_MSR_IRPERF] = { MSR_F17H_IRPERF, &group_irperf, test_irperf, },
	163	[PERF_MSR_THERM] = { MSR_IA32_THERM_STATUS, &group_therm, test_therm_status, },
19b3340c PZ	164	};
19b3340c PZ	165
dde5e720 JO	166	static struct attribute *events_attrs[] = {
dde5e720 JO	167	&attr_tsc.attr.attr,
19b3340c	168	NULL,
b7b7c782 AL	169	};
	170
	171	static struct attribute_group events_attr_group = {
	172	.name = "events",
	173	.attrs = events_attrs,
	174	};
	175
	176	PMU_FORMAT_ATTR(event, "config:0-63");
	177	static struct attribute *format_attrs[] = {
	178	&format_attr_event.attr,
	179	NULL,
	180	};
	181	static struct attribute_group format_attr_group = {
	182	.name = "format",
	183	.attrs = format_attrs,
	184	};
	185
	186	static const struct attribute_group *attr_groups[] = {
	187	&events_attr_group,
	188	&format_attr_group,
	189	NULL,
	190	};
	191
d9f3b450	192	static const struct attribute_group *attr_update[] = {
dde5e720 JO	193	&group_aperf,
	194	&group_mperf,
	195	&group_pperf,
	196	&group_smi,
	197	&group_ptsc,
	198	&group_irperf,
	199	&group_therm,
	200	NULL,
	201	};
	202
b7b7c782 AL	203	static int msr_event_init(struct perf_event *event)
	204	{
	205	u64 cfg = event->attr.config;
	206
	207	if (event->attr.type != event->pmu->type)
	208	return -ENOENT;
	209
b7b7c782	210	/* unsupported modes and filters */
2ff40250	211	if (event->attr.sample_period) /* no sampling */
b7b7c782 AL	212	return -EINVAL;
b7b7c782 AL	213
06ce6e9b PZ	214	if (cfg >= PERF_MSR_EVENT_MAX)
	215	return -EINVAL;
	216
	217	cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX);
	218
dde5e720	219	if (!(msr_mask & (1 << cfg)))
19b3340c PZ	220	return -EINVAL;
19b3340c PZ	221
9128d3ed IM	222	event->hw.idx = -1;
	223	event->hw.event_base = msr[cfg].msr;
	224	event->hw.config = cfg;
b7b7c782 AL	225
	226	return 0;
	227	}
	228
	229	static inline u64 msr_read_counter(struct perf_event *event)
	230	{
	231	u64 now;
	232
	233	if (event->hw.event_base)
	234	rdmsrl(event->hw.event_base, now);
	235	else
ea89c065	236	now = rdtsc_ordered();
b7b7c782 AL	237
	238	return now;
	239	}
ea89c065	240
b7b7c782 AL	241	static void msr_event_update(struct perf_event *event)
	242	{
	243	u64 prev, now;
	244	s64 delta;
	245
9128d3ed	246	/* Careful, an NMI might modify the previous event value: */
b7b7c782	247	prev = local64_read(&event->hw.prev_count);
4c1c9dea UB	248	do {
	249	now = msr_read_counter(event);
	250	} while (!local64_try_cmpxchg(&event->hw.prev_count, &prev, now));
b7b7c782 AL	251
b7b7c782 AL	252	delta = now - prev;
9ae21dd6	253	if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
78e3c795	254	delta = sign_extend64(delta, 31);
9ae21dd6 SE	255	local64_add(delta, &event->count);
9ae21dd6 SE	256	} else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) {
9128d3ed	257	/* If valid, extract digital readout, otherwise set to -1: */
9ae21dd6 SE	258	now = now & (1ULL << 31) ? (now >> 16) & 0x3f : -1;
9ae21dd6 SE	259	local64_set(&event->count, now);
9128d3ed	260	} else {
9ae21dd6	261	local64_add(delta, &event->count);
9128d3ed	262	}
b7b7c782 AL	263	}
	264
	265	static void msr_event_start(struct perf_event *event, int flags)
	266	{
9128d3ed	267	u64 now = msr_read_counter(event);
b7b7c782	268
b7b7c782 AL	269	local64_set(&event->hw.prev_count, now);
	270	}
	271
	272	static void msr_event_stop(struct perf_event *event, int flags)
	273	{
	274	msr_event_update(event);
	275	}
	276
	277	static void msr_event_del(struct perf_event *event, int flags)
	278	{
	279	msr_event_stop(event, PERF_EF_UPDATE);
	280	}
	281
	282	static int msr_event_add(struct perf_event *event, int flags)
	283	{
	284	if (flags & PERF_EF_START)
	285	msr_event_start(event, flags);
	286
	287	return 0;
	288	}
	289
	290	static struct pmu pmu_msr = {
	291	.task_ctx_nr = perf_sw_context,
	292	.attr_groups = attr_groups,
	293	.event_init = msr_event_init,
	294	.add = msr_event_add,
	295	.del = msr_event_del,
	296	.start = msr_event_start,
	297	.stop = msr_event_stop,
	298	.read = msr_event_update,
2ff40250	299	.capabilities = PERF_PMU_CAP_NO_INTERRUPT \| PERF_PMU_CAP_NO_EXCLUDE,
dde5e720	300	.attr_update = attr_update,
b7b7c782 AL	301	};
b7b7c782 AL	302
b7b7c782 AL	303	static int __init msr_init(void)
b7b7c782 AL	304	{
19b3340c PZ	305	if (!boot_cpu_has(X86_FEATURE_TSC)) {
	306	pr_cont("no MSR PMU driver.\n");
	307	return 0;
b7b7c782 AL	308	}
b7b7c782 AL	309
dde5e720	310	msr_mask = perf_msr_probe(msr, PERF_MSR_EVENT_MAX, true, NULL);
b7b7c782 AL	311
	312	perf_pmu_register(&pmu_msr, "msr", -1);
	313
	314	return 0;
	315	}
	316	device_initcall(msr_init);