[linux-2.6-block.git] / arch / x86 / events / intel / pt.h

/*
 * Intel(R) Processor Trace PMU driver for perf
 * Copyright (c) 2013-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * Intel PT is specified in the Intel Architecture Instruction Set Extensions
 * Programming Reference:
 * http://software.intel.com/en-us/intel-isa-extensions
 */

#ifndef __INTEL_PT_H__
#define __INTEL_PT_H__

/*
 * PT MSR bit definitions
 */
#define RTIT_CTL_TRACEEN		BIT(0)
#define RTIT_CTL_CYCLEACC		BIT(1)
#define RTIT_CTL_OS			BIT(2)
#define RTIT_CTL_USR			BIT(3)
#define RTIT_CTL_CR3EN			BIT(7)
#define RTIT_CTL_TOPA			BIT(8)
#define RTIT_CTL_MTC_EN			BIT(9)
#define RTIT_CTL_TSC_EN			BIT(10)
#define RTIT_CTL_DISRETC		BIT(11)
#define RTIT_CTL_BRANCH_EN		BIT(13)
#define RTIT_CTL_MTC_RANGE_OFFSET	14
#define RTIT_CTL_MTC_RANGE		(0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
#define RTIT_CTL_CYC_THRESH_OFFSET	19
#define RTIT_CTL_CYC_THRESH		(0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
#define RTIT_CTL_PSB_FREQ_OFFSET	24
#define RTIT_CTL_PSB_FREQ      		(0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
#define RTIT_CTL_ADDR0_OFFSET		32
#define RTIT_CTL_ADDR0      		(0x0full << RTIT_CTL_ADDR0_OFFSET)
#define RTIT_CTL_ADDR1_OFFSET		36
#define RTIT_CTL_ADDR1      		(0x0full << RTIT_CTL_ADDR1_OFFSET)
#define RTIT_CTL_ADDR2_OFFSET		40
#define RTIT_CTL_ADDR2      		(0x0full << RTIT_CTL_ADDR2_OFFSET)
#define RTIT_CTL_ADDR3_OFFSET		44
#define RTIT_CTL_ADDR3      		(0x0full << RTIT_CTL_ADDR3_OFFSET)
#define RTIT_STATUS_FILTEREN		BIT(0)
#define RTIT_STATUS_CONTEXTEN		BIT(1)
#define RTIT_STATUS_TRIGGEREN		BIT(2)
#define RTIT_STATUS_BUFFOVF		BIT(3)
#define RTIT_STATUS_ERROR		BIT(4)
#define RTIT_STATUS_STOPPED		BIT(5)

/*
 * Single-entry ToPA: when this close to region boundary, switch
 * buffers to avoid losing data.
 */
#define TOPA_PMI_MARGIN 512

#define TOPA_SHIFT 12

static inline unsigned int sizes(unsigned int tsz)
{
	return 1 << (tsz + TOPA_SHIFT);
};

struct topa_entry {
	u64	end	: 1;
	u64	rsvd0	: 1;
	u64	intr	: 1;
	u64	rsvd1	: 1;
	u64	stop	: 1;
	u64	rsvd2	: 1;
	u64	size	: 4;
	u64	rsvd3	: 2;
	u64	base	: 36;
	u64	rsvd4	: 16;
};

#define PT_CPUID_LEAVES		2
#define PT_CPUID_REGS_NUM	4 /* number of regsters (eax, ebx, ecx, edx) */

/* TSC to Core Crystal Clock Ratio */
#define CPUID_TSC_LEAF		0x15

enum pt_capabilities {
	PT_CAP_max_subleaf = 0,
	PT_CAP_cr3_filtering,
	PT_CAP_psb_cyc,
	PT_CAP_ip_filtering,
	PT_CAP_mtc,
	PT_CAP_topa_output,
	PT_CAP_topa_multiple_entries,
	PT_CAP_single_range_output,
	PT_CAP_payloads_lip,
	PT_CAP_num_address_ranges,
	PT_CAP_mtc_periods,
	PT_CAP_cycle_thresholds,
	PT_CAP_psb_periods,
};

struct pt_pmu {
	struct pmu		pmu;
	u32			caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
	bool			vmx;
	unsigned long		max_nonturbo_ratio;
	unsigned int		tsc_art_num;
	unsigned int		tsc_art_den;
};

/**
 * struct pt_buffer - buffer configuration; one buffer per task_struct or
 *		cpu, depending on perf event configuration
 * @cpu:	cpu for per-cpu allocation
 * @tables:	list of ToPA tables in this buffer
 * @first:	shorthand for first topa table
 * @last:	shorthand for last topa table
 * @cur:	current topa table
 * @nr_pages:	buffer size in pages
 * @cur_idx:	current output region's index within @cur table
 * @output_off:	offset within the current output region
 * @data_size:	running total of the amount of data in this buffer
 * @lost:	if data was lost/truncated
 * @head:	logical write offset inside the buffer
 * @snapshot:	if this is for a snapshot/overwrite counter
 * @stop_pos:	STOP topa entry in the buffer
 * @intr_pos:	INT topa entry in the buffer
 * @data_pages:	array of pages from perf
 * @topa_index:	table of topa entries indexed by page offset
 */
struct pt_buffer {
	int			cpu;
	struct list_head	tables;
	struct topa		*first, *last, *cur;
	unsigned int		cur_idx;
	size_t			output_off;
	unsigned long		nr_pages;
	local_t			data_size;
	local_t			lost;
	local64_t		head;
	bool			snapshot;
	unsigned long		stop_pos, intr_pos;
	void			**data_pages;
	struct topa_entry	*topa_index[0];
};

#define PT_FILTERS_NUM	4

/**
 * struct pt_filter - IP range filter configuration
 * @msr_a:	range start, goes to RTIT_ADDRn_A
 * @msr_b:	range end, goes to RTIT_ADDRn_B
 * @config:	4-bit field in RTIT_CTL
 */
struct pt_filter {
	unsigned long	msr_a;
	unsigned long	msr_b;
	unsigned long	config;
};

/**
 * struct pt_filters - IP range filtering context
 * @filter:	filters defined for this context
 * @nr_filters:	number of defined filters in the @filter array
 */
struct pt_filters {
	struct pt_filter	filter[PT_FILTERS_NUM];
	unsigned int		nr_filters;
};

/**
 * struct pt - per-cpu pt context
 * @handle:	perf output handle
 * @filters:		last configured filters
 * @handle_nmi:	do handle PT PMI on this cpu, there's an active event
 * @vmx_on:	1 if VMX is ON on this cpu
 */
struct pt {
	struct perf_output_handle handle;
	struct pt_filters	filters;
	int			handle_nmi;
	int			vmx_on;
};

#endif /* __INTEL_PT_H__ */
Commit	Line	Data
52ca9ced AS	1	/*
	2	* Intel(R) Processor Trace PMU driver for perf
	3	* Copyright (c) 2013-2014, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* Intel PT is specified in the Intel Architecture Instruction Set Extensions
	15	* Programming Reference:
	16	* http://software.intel.com/en-us/intel-isa-extensions
	17	*/
	18
	19	#ifndef __INTEL_PT_H__
	20	#define __INTEL_PT_H__
	21
0dd28e2c AS	22	/*
	23	* PT MSR bit definitions
	24	*/
	25	#define RTIT_CTL_TRACEEN BIT(0)
	26	#define RTIT_CTL_CYCLEACC BIT(1)
	27	#define RTIT_CTL_OS BIT(2)
	28	#define RTIT_CTL_USR BIT(3)
	29	#define RTIT_CTL_CR3EN BIT(7)
	30	#define RTIT_CTL_TOPA BIT(8)
	31	#define RTIT_CTL_MTC_EN BIT(9)
	32	#define RTIT_CTL_TSC_EN BIT(10)
	33	#define RTIT_CTL_DISRETC BIT(11)
	34	#define RTIT_CTL_BRANCH_EN BIT(13)
	35	#define RTIT_CTL_MTC_RANGE_OFFSET 14
	36	#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
	37	#define RTIT_CTL_CYC_THRESH_OFFSET 19
	38	#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
	39	#define RTIT_CTL_PSB_FREQ_OFFSET 24
	40	#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
f127fa09 AS	41	#define RTIT_CTL_ADDR0_OFFSET 32
	42	#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
	43	#define RTIT_CTL_ADDR1_OFFSET 36
	44	#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
	45	#define RTIT_CTL_ADDR2_OFFSET 40
	46	#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
	47	#define RTIT_CTL_ADDR3_OFFSET 44
	48	#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
	49	#define RTIT_STATUS_FILTEREN BIT(0)
0dd28e2c AS	50	#define RTIT_STATUS_CONTEXTEN BIT(1)
0dd28e2c AS	51	#define RTIT_STATUS_TRIGGEREN BIT(2)
f127fa09	52	#define RTIT_STATUS_BUFFOVF BIT(3)
0dd28e2c AS	53	#define RTIT_STATUS_ERROR BIT(4)
	54	#define RTIT_STATUS_STOPPED BIT(5)
	55
52ca9ced AS	56	/*
	57	* Single-entry ToPA: when this close to region boundary, switch
	58	* buffers to avoid losing data.
	59	*/
	60	#define TOPA_PMI_MARGIN 512
	61
709bc871	62	#define TOPA_SHIFT 12
52ca9ced	63
709bc871	64	static inline unsigned int sizes(unsigned int tsz)
52ca9ced	65	{
709bc871	66	return 1 << (tsz + TOPA_SHIFT);
52ca9ced AS	67	};
	68
	69	struct topa_entry {
	70	u64 end : 1;
	71	u64 rsvd0 : 1;
	72	u64 intr : 1;
	73	u64 rsvd1 : 1;
	74	u64 stop : 1;
	75	u64 rsvd2 : 1;
	76	u64 size : 4;
	77	u64 rsvd3 : 2;
	78	u64 base : 36;
	79	u64 rsvd4 : 16;
	80	};
	81
709bc871 TI	82	#define PT_CPUID_LEAVES 2
709bc871 TI	83	#define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */
52ca9ced	84
65c7e6f1 AS	85	/* TSC to Core Crystal Clock Ratio */
	86	#define CPUID_TSC_LEAF 0x15
	87
52ca9ced AS	88	enum pt_capabilities {
	89	PT_CAP_max_subleaf = 0,
	90	PT_CAP_cr3_filtering,
b1bf72d6	91	PT_CAP_psb_cyc,
f127fa09	92	PT_CAP_ip_filtering,
b1bf72d6	93	PT_CAP_mtc,
52ca9ced AS	94	PT_CAP_topa_output,
52ca9ced AS	95	PT_CAP_topa_multiple_entries,
b1bf72d6	96	PT_CAP_single_range_output,
52ca9ced	97	PT_CAP_payloads_lip,
f127fa09	98	PT_CAP_num_address_ranges,
b1bf72d6 AS	99	PT_CAP_mtc_periods,
	100	PT_CAP_cycle_thresholds,
	101	PT_CAP_psb_periods,
52ca9ced AS	102	};
	103
	104	struct pt_pmu {
	105	struct pmu pmu;
709bc871	106	u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
1c5ac21a	107	bool vmx;
65c7e6f1 AS	108	unsigned long max_nonturbo_ratio;
	109	unsigned int tsc_art_num;
	110	unsigned int tsc_art_den;
52ca9ced AS	111	};
	112
	113	/**
	114	* struct pt_buffer - buffer configuration; one buffer per task_struct or
	115	* cpu, depending on perf event configuration
	116	* @cpu: cpu for per-cpu allocation
	117	* @tables: list of ToPA tables in this buffer
	118	* @first: shorthand for first topa table
	119	* @last: shorthand for last topa table
	120	* @cur: current topa table
	121	* @nr_pages: buffer size in pages
	122	* @cur_idx: current output region's index within @cur table
	123	* @output_off: offset within the current output region
	124	* @data_size: running total of the amount of data in this buffer
	125	* @lost: if data was lost/truncated
	126	* @head: logical write offset inside the buffer
	127	* @snapshot: if this is for a snapshot/overwrite counter
	128	* @stop_pos: STOP topa entry in the buffer
	129	* @intr_pos: INT topa entry in the buffer
	130	* @data_pages: array of pages from perf
	131	* @topa_index: table of topa entries indexed by page offset
	132	*/
	133	struct pt_buffer {
	134	int cpu;
	135	struct list_head tables;
	136	struct topa first, last, *cur;
	137	unsigned int cur_idx;
	138	size_t output_off;
	139	unsigned long nr_pages;
	140	local_t data_size;
	141	local_t lost;
	142	local64_t head;
	143	bool snapshot;
	144	unsigned long stop_pos, intr_pos;
	145	void **data_pages;
	146	struct topa_entry *topa_index[0];
	147	};
	148
eadf48ca AS	149	#define PT_FILTERS_NUM 4
	150
	151	/**
	152	* struct pt_filter - IP range filter configuration
	153	* @msr_a: range start, goes to RTIT_ADDRn_A
	154	* @msr_b: range end, goes to RTIT_ADDRn_B
	155	* @config: 4-bit field in RTIT_CTL
	156	*/
	157	struct pt_filter {
	158	unsigned long msr_a;
	159	unsigned long msr_b;
	160	unsigned long config;
	161	};
	162
	163	/**
	164	* struct pt_filters - IP range filtering context
	165	* @filter: filters defined for this context
	166	* @nr_filters: number of defined filters in the @filter array
	167	*/
	168	struct pt_filters {
	169	struct pt_filter filter[PT_FILTERS_NUM];
	170	unsigned int nr_filters;
	171	};
	172
52ca9ced AS	173	/**
	174	* struct pt - per-cpu pt context
	175	* @handle: perf output handle
eadf48ca	176	* @filters: last configured filters
52ca9ced	177	* @handle_nmi: do handle PT PMI on this cpu, there's an active event
1c5ac21a	178	* @vmx_on: 1 if VMX is ON on this cpu
52ca9ced AS	179	*/
	180	struct pt {
	181	struct perf_output_handle handle;
eadf48ca	182	struct pt_filters filters;
52ca9ced	183	int handle_nmi;
1c5ac21a	184	int vmx_on;
52ca9ced AS	185	};
	186
	187	#endif /* __INTEL_PT_H__ */