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perf/x86/intel: Add definition for PT PMI bit
[linux-2.6-block.git] / arch / x86 / events / intel / core.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
aacfbe6a 15#include <linux/nmi.h>
de0428a7 16
3a632cb2 17#include <asm/cpufeature.h>
de0428a7
KW		 18#include <asm/hardirq.h>
19#include <asm/apic.h>
20
27f6d22b 21#include "../perf_event.h"
a7e3ed1e 22
f22f54f4 23/*
b622d644 24 * Intel PerfMon, used on Core and later.
f22f54f4 25 */
ec75a716 26static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 27{
c3b7cdf1
PE		 28 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
29 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
30 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
31 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
32 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
33 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
34 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
35 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 36};
37
5c543e3c 38static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 39{
40 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
41 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
42 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
43 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
44 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
45 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
46 EVENT_CONSTRAINT_END
47};
48
5c543e3c 49static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 50{
b622d644
PZ		 51 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
52 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 53 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 54 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
55 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
56 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
57 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
58 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
59 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
60 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
61 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 62 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 63 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
64 EVENT_CONSTRAINT_END
65};
66
5c543e3c 67static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 68{
b622d644
PZ		 69 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
70 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 71 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 72 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
73 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
74 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
75 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
76 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
77 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
78 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
79 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
80 EVENT_CONSTRAINT_END
81};
82
5c543e3c 83static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 84{
53ad0447
YZ		 85 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
86 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 87 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 88 EVENT_EXTRA_END
89};
90
5c543e3c 91static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 92{
b622d644
PZ		 93 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
94 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 95 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 96 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
97 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
98 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 99 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 100 EVENT_CONSTRAINT_END
101};
102
5c543e3c 103static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 104{
105 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
106 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 107 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 108 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
109 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
110 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
111 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 112 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 113 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
114 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
f8378f52
AK		 115 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
93fcf72c
MD		 117
118 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
119 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
120 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
121 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
122
b06b3d49
LM		 123 EVENT_CONSTRAINT_END
124};
125
69943182
SE		 126static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
127{
128 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
129 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
130 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
131 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
132 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
133 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
6113af14 134 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
69943182
SE		 135 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
136 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
138 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
139 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
93fcf72c
MD		 141
142 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
143 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
144 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
145 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
146
69943182
SE		 147 EVENT_CONSTRAINT_END
148};
149
5c543e3c 150static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 151{
53ad0447
YZ		 152 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
153 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
154 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 155 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 156 EVENT_EXTRA_END
157};
158
0af3ac1f
AK		 159static struct event_constraint intel_v1_event_constraints[] __read_mostly =
160{
161 EVENT_CONSTRAINT_END
162};
163
5c543e3c 164static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 165{
b622d644
PZ		 166 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
167 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 168 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 169 EVENT_CONSTRAINT_END
170};
171
1fa64180
YZ		 172static struct event_constraint intel_slm_event_constraints[] __read_mostly =
173{
174 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
175 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
1fa64180
YZ		 176 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
177 EVENT_CONSTRAINT_END
178};
179
9a92e16f
AK		 180struct event_constraint intel_skl_event_constraints[] = {
181 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
182 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
183 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
184 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
185 EVENT_CONSTRAINT_END
186};
187
1e7b9390
HC		 188static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
189 INTEL_UEVENT_EXTRA_REG(0x01b7,
190 MSR_OFFCORE_RSP_0, 0x7f9ffbffffull, RSP_0),
191 INTEL_UEVENT_EXTRA_REG(0x02b7,
192 MSR_OFFCORE_RSP_1, 0x3f9ffbffffull, RSP_1),
193 EVENT_EXTRA_END
194};
195
ee89cbc2 196static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
53ad0447
YZ		 197 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
198 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
199 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
f20093ee 200 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
f1923820
SE		 201 EVENT_EXTRA_END
202};
203
204static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
53ad0447
YZ		 205 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
206 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
207 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
f1a52789 208 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 209 EVENT_EXTRA_END
210};
211
9a92e16f
AK		 212static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
213 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
214 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
215 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
dfe1f3cb
AK		 216 /*
217 * Note the low 8 bits eventsel code is not a continuous field, containing
218 * some #GPing bits. These are masked out.
219 */
220 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
9a92e16f
AK		 221 EVENT_EXTRA_END
222};
223
7f2ee91f
IM		 224EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
225EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
226EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
f20093ee
SE		 227
228struct attribute *nhm_events_attrs[] = {
229 EVENT_PTR(mem_ld_nhm),
230 NULL,
231};
232
233struct attribute *snb_events_attrs[] = {
234 EVENT_PTR(mem_ld_snb),
9ad64c0f 235 EVENT_PTR(mem_st_snb),
f20093ee
SE		 236 NULL,
237};
238
3a632cb2
AK		 239static struct event_constraint intel_hsw_event_constraints[] = {
240 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
241 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
242 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
e0fbac1c 243 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
3a632cb2
AK		 244 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
245 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
246 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
c420f19b 247 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
3a632cb2 248 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
c420f19b 249 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
3a632cb2 250 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
c420f19b 251 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
93fcf72c
MD		 252
253 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
254 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
255 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
256 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
257
3a632cb2
AK		 258 EVENT_CONSTRAINT_END
259};
260
91f1b705
AK		 261struct event_constraint intel_bdw_event_constraints[] = {
262 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
263 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
264 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
265 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
b7883a1c 266 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
91f1b705
AK		 267 EVENT_CONSTRAINT_END
268};
269
f22f54f4
PZ		 270static u64 intel_pmu_event_map(int hw_event)
271{
272 return intel_perfmon_event_map[hw_event];
273}
274
9a92e16f
AK		 275/*
276 * Notes on the events:
277 * - data reads do not include code reads (comparable to earlier tables)
278 * - data counts include speculative execution (except L1 write, dtlb, bpu)
279 * - remote node access includes remote memory, remote cache, remote mmio.
280 * - prefetches are not included in the counts.
281 * - icache miss does not include decoded icache
282 */
283
284#define SKL_DEMAND_DATA_RD BIT_ULL(0)
285#define SKL_DEMAND_RFO BIT_ULL(1)
286#define SKL_ANY_RESPONSE BIT_ULL(16)
287#define SKL_SUPPLIER_NONE BIT_ULL(17)
288#define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
289#define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
290#define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
291#define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
292#define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
293 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
294 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
295 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
296#define SKL_SPL_HIT BIT_ULL(30)
297#define SKL_SNOOP_NONE BIT_ULL(31)
298#define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
299#define SKL_SNOOP_MISS BIT_ULL(33)
300#define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
301#define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
302#define SKL_SNOOP_HITM BIT_ULL(36)
303#define SKL_SNOOP_NON_DRAM BIT_ULL(37)
304#define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
305 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
306 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
307 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
308#define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
309#define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
310 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
311 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
312 SKL_SNOOP_HITM|SKL_SPL_HIT)
313#define SKL_DEMAND_WRITE SKL_DEMAND_RFO
314#define SKL_LLC_ACCESS SKL_ANY_RESPONSE
315#define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
316 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
317 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
318
319static __initconst const u64 skl_hw_cache_event_ids
320 [PERF_COUNT_HW_CACHE_MAX]
321 [PERF_COUNT_HW_CACHE_OP_MAX]
322 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
323{
324 [ C(L1D ) ] = {
325 [ C(OP_READ) ] = {
326 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
327 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
328 },
329 [ C(OP_WRITE) ] = {
330 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
331 [ C(RESULT_MISS) ] = 0x0,
332 },
333 [ C(OP_PREFETCH) ] = {
334 [ C(RESULT_ACCESS) ] = 0x0,
335 [ C(RESULT_MISS) ] = 0x0,
336 },
337 },
338 [ C(L1I ) ] = {
339 [ C(OP_READ) ] = {
340 [ C(RESULT_ACCESS) ] = 0x0,
341 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
342 },
343 [ C(OP_WRITE) ] = {
344 [ C(RESULT_ACCESS) ] = -1,
345 [ C(RESULT_MISS) ] = -1,
346 },
347 [ C(OP_PREFETCH) ] = {
348 [ C(RESULT_ACCESS) ] = 0x0,
349 [ C(RESULT_MISS) ] = 0x0,
350 },
351 },
352 [ C(LL ) ] = {
353 [ C(OP_READ) ] = {
354 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
355 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
356 },
357 [ C(OP_WRITE) ] = {
358 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
359 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
360 },
361 [ C(OP_PREFETCH) ] = {
362 [ C(RESULT_ACCESS) ] = 0x0,
363 [ C(RESULT_MISS) ] = 0x0,
364 },
365 },
366 [ C(DTLB) ] = {
367 [ C(OP_READ) ] = {
368 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
369 [ C(RESULT_MISS) ] = 0x608, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
370 },
371 [ C(OP_WRITE) ] = {
372 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
373 [ C(RESULT_MISS) ] = 0x649, /* DTLB_STORE_MISSES.WALK_COMPLETED */
374 },
375 [ C(OP_PREFETCH) ] = {
376 [ C(RESULT_ACCESS) ] = 0x0,
377 [ C(RESULT_MISS) ] = 0x0,
378 },
379 },
380 [ C(ITLB) ] = {
381 [ C(OP_READ) ] = {
382 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
383 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
384 },
385 [ C(OP_WRITE) ] = {
386 [ C(RESULT_ACCESS) ] = -1,
387 [ C(RESULT_MISS) ] = -1,
388 },
389 [ C(OP_PREFETCH) ] = {
390 [ C(RESULT_ACCESS) ] = -1,
391 [ C(RESULT_MISS) ] = -1,
392 },
393 },
394 [ C(BPU ) ] = {
395 [ C(OP_READ) ] = {
396 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
397 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
398 },
399 [ C(OP_WRITE) ] = {
400 [ C(RESULT_ACCESS) ] = -1,
401 [ C(RESULT_MISS) ] = -1,
402 },
403 [ C(OP_PREFETCH) ] = {
404 [ C(RESULT_ACCESS) ] = -1,
405 [ C(RESULT_MISS) ] = -1,
406 },
407 },
408 [ C(NODE) ] = {
409 [ C(OP_READ) ] = {
410 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
411 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
412 },
413 [ C(OP_WRITE) ] = {
414 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
415 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
416 },
417 [ C(OP_PREFETCH) ] = {
418 [ C(RESULT_ACCESS) ] = 0x0,
419 [ C(RESULT_MISS) ] = 0x0,
420 },
421 },
422};
423
424static __initconst const u64 skl_hw_cache_extra_regs
425 [PERF_COUNT_HW_CACHE_MAX]
426 [PERF_COUNT_HW_CACHE_OP_MAX]
427 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
428{
429 [ C(LL ) ] = {
430 [ C(OP_READ) ] = {
431 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
432 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
433 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
434 SKL_L3_MISS|SKL_ANY_SNOOP|
435 SKL_SUPPLIER_NONE,
436 },
437 [ C(OP_WRITE) ] = {
438 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
439 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
440 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
441 SKL_L3_MISS|SKL_ANY_SNOOP|
442 SKL_SUPPLIER_NONE,
443 },
444 [ C(OP_PREFETCH) ] = {
445 [ C(RESULT_ACCESS) ] = 0x0,
446 [ C(RESULT_MISS) ] = 0x0,
447 },
448 },
449 [ C(NODE) ] = {
450 [ C(OP_READ) ] = {
451 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
452 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
453 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
454 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
455 },
456 [ C(OP_WRITE) ] = {
457 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
458 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
459 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
460 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
461 },
462 [ C(OP_PREFETCH) ] = {
463 [ C(RESULT_ACCESS) ] = 0x0,
464 [ C(RESULT_MISS) ] = 0x0,
465 },
466 },
467};
468
74e6543f
YZ		 469#define SNB_DMND_DATA_RD (1ULL << 0)
470#define SNB_DMND_RFO (1ULL << 1)
471#define SNB_DMND_IFETCH (1ULL << 2)
472#define SNB_DMND_WB (1ULL << 3)
473#define SNB_PF_DATA_RD (1ULL << 4)
474#define SNB_PF_RFO (1ULL << 5)
475#define SNB_PF_IFETCH (1ULL << 6)
476#define SNB_LLC_DATA_RD (1ULL << 7)
477#define SNB_LLC_RFO (1ULL << 8)
478#define SNB_LLC_IFETCH (1ULL << 9)
479#define SNB_BUS_LOCKS (1ULL << 10)
480#define SNB_STRM_ST (1ULL << 11)
481#define SNB_OTHER (1ULL << 15)
482#define SNB_RESP_ANY (1ULL << 16)
483#define SNB_NO_SUPP (1ULL << 17)
484#define SNB_LLC_HITM (1ULL << 18)
485#define SNB_LLC_HITE (1ULL << 19)
486#define SNB_LLC_HITS (1ULL << 20)
487#define SNB_LLC_HITF (1ULL << 21)
488#define SNB_LOCAL (1ULL << 22)
489#define SNB_REMOTE (0xffULL << 23)
490#define SNB_SNP_NONE (1ULL << 31)
491#define SNB_SNP_NOT_NEEDED (1ULL << 32)
492#define SNB_SNP_MISS (1ULL << 33)
493#define SNB_NO_FWD (1ULL << 34)
494#define SNB_SNP_FWD (1ULL << 35)
495#define SNB_HITM (1ULL << 36)
496#define SNB_NON_DRAM (1ULL << 37)
497
498#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
499#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
500#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
501
502#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
503 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
504 SNB_HITM)
505
506#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
507#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
508
509#define SNB_L3_ACCESS SNB_RESP_ANY
510#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
511
512static __initconst const u64 snb_hw_cache_extra_regs
513 [PERF_COUNT_HW_CACHE_MAX]
514 [PERF_COUNT_HW_CACHE_OP_MAX]
515 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
516{
517 [ C(LL ) ] = {
518 [ C(OP_READ) ] = {
519 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
520 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
521 },
522 [ C(OP_WRITE) ] = {
523 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
524 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
525 },
526 [ C(OP_PREFETCH) ] = {
527 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
528 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
529 },
530 },
531 [ C(NODE) ] = {
532 [ C(OP_READ) ] = {
533 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
534 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
535 },
536 [ C(OP_WRITE) ] = {
537 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
538 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
539 },
540 [ C(OP_PREFETCH) ] = {
541 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
542 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
543 },
544 },
545};
546
b06b3d49
LM		 547static __initconst const u64 snb_hw_cache_event_ids
548 [PERF_COUNT_HW_CACHE_MAX]
549 [PERF_COUNT_HW_CACHE_OP_MAX]
550 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
551{
552 [ C(L1D) ] = {
553 [ C(OP_READ) ] = {
554 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
555 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
556 },
557 [ C(OP_WRITE) ] = {
558 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
559 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
560 },
561 [ C(OP_PREFETCH) ] = {
562 [ C(RESULT_ACCESS) ] = 0x0,
563 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
564 },
565 },
566 [ C(L1I ) ] = {
567 [ C(OP_READ) ] = {
568 [ C(RESULT_ACCESS) ] = 0x0,
569 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
570 },
571 [ C(OP_WRITE) ] = {
572 [ C(RESULT_ACCESS) ] = -1,
573 [ C(RESULT_MISS) ] = -1,
574 },
575 [ C(OP_PREFETCH) ] = {
576 [ C(RESULT_ACCESS) ] = 0x0,
577 [ C(RESULT_MISS) ] = 0x0,
578 },
579 },
580 [ C(LL ) ] = {
b06b3d49 581 [ C(OP_READ) ] = {
63b6a675 582 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 583 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 584 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
585 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 586 },
587 [ C(OP_WRITE) ] = {
63b6a675 588 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 589 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 590 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
591 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 592 },
593 [ C(OP_PREFETCH) ] = {
63b6a675 594 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 595 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 596 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
597 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 598 },
599 },
600 [ C(DTLB) ] = {
601 [ C(OP_READ) ] = {
602 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
603 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
604 },
605 [ C(OP_WRITE) ] = {
606 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
607 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
608 },
609 [ C(OP_PREFETCH) ] = {
610 [ C(RESULT_ACCESS) ] = 0x0,
611 [ C(RESULT_MISS) ] = 0x0,
612 },
613 },
614 [ C(ITLB) ] = {
615 [ C(OP_READ) ] = {
616 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
617 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
618 },
619 [ C(OP_WRITE) ] = {
620 [ C(RESULT_ACCESS) ] = -1,
621 [ C(RESULT_MISS) ] = -1,
622 },
623 [ C(OP_PREFETCH) ] = {
624 [ C(RESULT_ACCESS) ] = -1,
625 [ C(RESULT_MISS) ] = -1,
626 },
627 },
628 [ C(BPU ) ] = {
629 [ C(OP_READ) ] = {
630 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
631 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
632 },
633 [ C(OP_WRITE) ] = {
634 [ C(RESULT_ACCESS) ] = -1,
635 [ C(RESULT_MISS) ] = -1,
636 },
637 [ C(OP_PREFETCH) ] = {
638 [ C(RESULT_ACCESS) ] = -1,
639 [ C(RESULT_MISS) ] = -1,
640 },
641 },
89d6c0b5
PZ		 642 [ C(NODE) ] = {
643 [ C(OP_READ) ] = {
74e6543f
YZ		 644 [ C(RESULT_ACCESS) ] = 0x01b7,
645 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 646 },
647 [ C(OP_WRITE) ] = {
74e6543f
YZ		 648 [ C(RESULT_ACCESS) ] = 0x01b7,
649 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 650 },
651 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 652 [ C(RESULT_ACCESS) ] = 0x01b7,
653 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 654 },
655 },
656
b06b3d49
LM		 657};
658
0f1b5ca2
AK		 659/*
660 * Notes on the events:
661 * - data reads do not include code reads (comparable to earlier tables)
662 * - data counts include speculative execution (except L1 write, dtlb, bpu)
663 * - remote node access includes remote memory, remote cache, remote mmio.
664 * - prefetches are not included in the counts because they are not
665 * reliably counted.
666 */
667
668#define HSW_DEMAND_DATA_RD BIT_ULL(0)
669#define HSW_DEMAND_RFO BIT_ULL(1)
670#define HSW_ANY_RESPONSE BIT_ULL(16)
671#define HSW_SUPPLIER_NONE BIT_ULL(17)
672#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
673#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
674#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
675#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
676#define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
677 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
678 HSW_L3_MISS_REMOTE_HOP2P)
679#define HSW_SNOOP_NONE BIT_ULL(31)
680#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
681#define HSW_SNOOP_MISS BIT_ULL(33)
682#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
683#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
684#define HSW_SNOOP_HITM BIT_ULL(36)
685#define HSW_SNOOP_NON_DRAM BIT_ULL(37)
686#define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
687 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
688 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
689 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
690#define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
691#define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
692#define HSW_DEMAND_WRITE HSW_DEMAND_RFO
693#define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
694 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
695#define HSW_LLC_ACCESS HSW_ANY_RESPONSE
696
91f1b705
AK		 697#define BDW_L3_MISS_LOCAL BIT(26)
698#define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
699 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
700 HSW_L3_MISS_REMOTE_HOP2P)
701
702
0f1b5ca2
AK		 703static __initconst const u64 hsw_hw_cache_event_ids
704 [PERF_COUNT_HW_CACHE_MAX]
705 [PERF_COUNT_HW_CACHE_OP_MAX]
706 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
707{
708 [ C(L1D ) ] = {
709 [ C(OP_READ) ] = {
710 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
711 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
712 },
713 [ C(OP_WRITE) ] = {
714 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
715 [ C(RESULT_MISS) ] = 0x0,
716 },
717 [ C(OP_PREFETCH) ] = {
718 [ C(RESULT_ACCESS) ] = 0x0,
719 [ C(RESULT_MISS) ] = 0x0,
720 },
721 },
722 [ C(L1I ) ] = {
723 [ C(OP_READ) ] = {
724 [ C(RESULT_ACCESS) ] = 0x0,
725 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
726 },
727 [ C(OP_WRITE) ] = {
728 [ C(RESULT_ACCESS) ] = -1,
729 [ C(RESULT_MISS) ] = -1,
730 },
731 [ C(OP_PREFETCH) ] = {
732 [ C(RESULT_ACCESS) ] = 0x0,
733 [ C(RESULT_MISS) ] = 0x0,
734 },
735 },
736 [ C(LL ) ] = {
737 [ C(OP_READ) ] = {
738 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
739 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
740 },
741 [ C(OP_WRITE) ] = {
742 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
743 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
744 },
745 [ C(OP_PREFETCH) ] = {
746 [ C(RESULT_ACCESS) ] = 0x0,
747 [ C(RESULT_MISS) ] = 0x0,
748 },
749 },
750 [ C(DTLB) ] = {
751 [ C(OP_READ) ] = {
752 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
753 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
754 },
755 [ C(OP_WRITE) ] = {
756 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
757 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
758 },
759 [ C(OP_PREFETCH) ] = {
760 [ C(RESULT_ACCESS) ] = 0x0,
761 [ C(RESULT_MISS) ] = 0x0,
762 },
763 },
764 [ C(ITLB) ] = {
765 [ C(OP_READ) ] = {
766 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
767 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
768 },
769 [ C(OP_WRITE) ] = {
770 [ C(RESULT_ACCESS) ] = -1,
771 [ C(RESULT_MISS) ] = -1,
772 },
773 [ C(OP_PREFETCH) ] = {
774 [ C(RESULT_ACCESS) ] = -1,
775 [ C(RESULT_MISS) ] = -1,
776 },
777 },
778 [ C(BPU ) ] = {
779 [ C(OP_READ) ] = {
780 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
781 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
782 },
783 [ C(OP_WRITE) ] = {
784 [ C(RESULT_ACCESS) ] = -1,
785 [ C(RESULT_MISS) ] = -1,
786 },
787 [ C(OP_PREFETCH) ] = {
788 [ C(RESULT_ACCESS) ] = -1,
789 [ C(RESULT_MISS) ] = -1,
790 },
791 },
792 [ C(NODE) ] = {
793 [ C(OP_READ) ] = {
794 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
795 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
796 },
797 [ C(OP_WRITE) ] = {
798 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
799 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
800 },
801 [ C(OP_PREFETCH) ] = {
802 [ C(RESULT_ACCESS) ] = 0x0,
803 [ C(RESULT_MISS) ] = 0x0,
804 },
805 },
806};
807
808static __initconst const u64 hsw_hw_cache_extra_regs
809 [PERF_COUNT_HW_CACHE_MAX]
810 [PERF_COUNT_HW_CACHE_OP_MAX]
811 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
812{
813 [ C(LL ) ] = {
814 [ C(OP_READ) ] = {
815 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
816 HSW_LLC_ACCESS,
817 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
818 HSW_L3_MISS|HSW_ANY_SNOOP,
819 },
820 [ C(OP_WRITE) ] = {
821 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
822 HSW_LLC_ACCESS,
823 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
824 HSW_L3_MISS|HSW_ANY_SNOOP,
825 },
826 [ C(OP_PREFETCH) ] = {
827 [ C(RESULT_ACCESS) ] = 0x0,
828 [ C(RESULT_MISS) ] = 0x0,
829 },
830 },
831 [ C(NODE) ] = {
832 [ C(OP_READ) ] = {
833 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
834 HSW_L3_MISS_LOCAL_DRAM|
835 HSW_SNOOP_DRAM,
836 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
837 HSW_L3_MISS_REMOTE|
838 HSW_SNOOP_DRAM,
839 },
840 [ C(OP_WRITE) ] = {
841 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
842 HSW_L3_MISS_LOCAL_DRAM|
843 HSW_SNOOP_DRAM,
844 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
845 HSW_L3_MISS_REMOTE|
846 HSW_SNOOP_DRAM,
847 },
848 [ C(OP_PREFETCH) ] = {
849 [ C(RESULT_ACCESS) ] = 0x0,
850 [ C(RESULT_MISS) ] = 0x0,
851 },
852 },
853};
854
caaa8be3 855static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 856 [PERF_COUNT_HW_CACHE_MAX]
857 [PERF_COUNT_HW_CACHE_OP_MAX]
858 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
859{
860 [ C(L1D) ] = {
861 [ C(OP_READ) ] = {
862 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
863 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
864 },
865 [ C(OP_WRITE) ] = {
866 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
867 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
868 },
869 [ C(OP_PREFETCH) ] = {
870 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
871 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
872 },
873 },
874 [ C(L1I ) ] = {
875 [ C(OP_READ) ] = {
876 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
877 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
878 },
879 [ C(OP_WRITE) ] = {
880 [ C(RESULT_ACCESS) ] = -1,
881 [ C(RESULT_MISS) ] = -1,
882 },
883 [ C(OP_PREFETCH) ] = {
884 [ C(RESULT_ACCESS) ] = 0x0,
885 [ C(RESULT_MISS) ] = 0x0,
886 },
887 },
888 [ C(LL ) ] = {
889 [ C(OP_READ) ] = {
63b6a675 890 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 891 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 892 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
893 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 894 },
e994d7d2
AK		 895 /*
896 * Use RFO, not WRITEBACK, because a write miss would typically occur
897 * on RFO.
898 */
f22f54f4 899 [ C(OP_WRITE) ] = {
63b6a675
PZ		 900 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
901 [ C(RESULT_ACCESS) ] = 0x01b7,
902 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 903 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 904 },
905 [ C(OP_PREFETCH) ] = {
63b6a675 906 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 907 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 908 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
909 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 910 },
911 },
912 [ C(DTLB) ] = {
913 [ C(OP_READ) ] = {
914 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
915 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
916 },
917 [ C(OP_WRITE) ] = {
918 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
919 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
920 },
921 [ C(OP_PREFETCH) ] = {
922 [ C(RESULT_ACCESS) ] = 0x0,
923 [ C(RESULT_MISS) ] = 0x0,
924 },
925 },
926 [ C(ITLB) ] = {
927 [ C(OP_READ) ] = {
928 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
929 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
930 },
931 [ C(OP_WRITE) ] = {
932 [ C(RESULT_ACCESS) ] = -1,
933 [ C(RESULT_MISS) ] = -1,
934 },
935 [ C(OP_PREFETCH) ] = {
936 [ C(RESULT_ACCESS) ] = -1,
937 [ C(RESULT_MISS) ] = -1,
938 },
939 },
940 [ C(BPU ) ] = {
941 [ C(OP_READ) ] = {
942 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
943 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
944 },
945 [ C(OP_WRITE) ] = {
946 [ C(RESULT_ACCESS) ] = -1,
947 [ C(RESULT_MISS) ] = -1,
948 },
949 [ C(OP_PREFETCH) ] = {
950 [ C(RESULT_ACCESS) ] = -1,
951 [ C(RESULT_MISS) ] = -1,
952 },
953 },
89d6c0b5
PZ		 954 [ C(NODE) ] = {
955 [ C(OP_READ) ] = {
956 [ C(RESULT_ACCESS) ] = 0x01b7,
957 [ C(RESULT_MISS) ] = 0x01b7,
958 },
959 [ C(OP_WRITE) ] = {
960 [ C(RESULT_ACCESS) ] = 0x01b7,
961 [ C(RESULT_MISS) ] = 0x01b7,
962 },
963 [ C(OP_PREFETCH) ] = {
964 [ C(RESULT_ACCESS) ] = 0x01b7,
965 [ C(RESULT_MISS) ] = 0x01b7,
966 },
967 },
f22f54f4
PZ		 968};
969
e994d7d2 970/*
63b6a675
PZ		 971 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
972 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 973 */
974
63b6a675
PZ		 975#define NHM_DMND_DATA_RD (1 << 0)
976#define NHM_DMND_RFO (1 << 1)
977#define NHM_DMND_IFETCH (1 << 2)
978#define NHM_DMND_WB (1 << 3)
979#define NHM_PF_DATA_RD (1 << 4)
980#define NHM_PF_DATA_RFO (1 << 5)
981#define NHM_PF_IFETCH (1 << 6)
982#define NHM_OFFCORE_OTHER (1 << 7)
983#define NHM_UNCORE_HIT (1 << 8)
984#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
985#define NHM_OTHER_CORE_HITM (1 << 10)
986 /* reserved */
987#define NHM_REMOTE_CACHE_FWD (1 << 12)
988#define NHM_REMOTE_DRAM (1 << 13)
989#define NHM_LOCAL_DRAM (1 << 14)
990#define NHM_NON_DRAM (1 << 15)
991
87e24f4b
PZ		 992#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
993#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 994
995#define NHM_DMND_READ (NHM_DMND_DATA_RD)
996#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
997#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
998
999#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 1000#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 1001#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 1002
1003static __initconst const u64 nehalem_hw_cache_extra_regs
1004 [PERF_COUNT_HW_CACHE_MAX]
1005 [PERF_COUNT_HW_CACHE_OP_MAX]
1006 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1007{
1008 [ C(LL ) ] = {
1009 [ C(OP_READ) ] = {
63b6a675
PZ		 1010 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1011 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 1012 },
1013 [ C(OP_WRITE) ] = {
63b6a675
PZ		 1014 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1015 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 1016 },
1017 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 1018 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1019 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 1020 },
89d6c0b5
PZ		 1021 },
1022 [ C(NODE) ] = {
1023 [ C(OP_READ) ] = {
87e24f4b
PZ		 1024 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1025 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 1026 },
1027 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 1028 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1029 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 1030 },
1031 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 1032 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1033 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 1034 },
1035 },
e994d7d2
AK		 1036};
1037
caaa8be3 1038static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 1039 [PERF_COUNT_HW_CACHE_MAX]
1040 [PERF_COUNT_HW_CACHE_OP_MAX]
1041 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1042{
1043 [ C(L1D) ] = {
1044 [ C(OP_READ) ] = {
f4929bd3
PZ		 1045 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1046 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 1047 },
1048 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 1049 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1050 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 1051 },
1052 [ C(OP_PREFETCH) ] = {
1053 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1054 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1055 },
1056 },
1057 [ C(L1I ) ] = {
1058 [ C(OP_READ) ] = {
1059 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1060 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1061 },
1062 [ C(OP_WRITE) ] = {
1063 [ C(RESULT_ACCESS) ] = -1,
1064 [ C(RESULT_MISS) ] = -1,
1065 },
1066 [ C(OP_PREFETCH) ] = {
1067 [ C(RESULT_ACCESS) ] = 0x0,
1068 [ C(RESULT_MISS) ] = 0x0,
1069 },
1070 },
1071 [ C(LL ) ] = {
1072 [ C(OP_READ) ] = {
e994d7d2
AK		 1073 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1074 [ C(RESULT_ACCESS) ] = 0x01b7,
1075 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1076 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 1077 },
e994d7d2
AK		 1078 /*
1079 * Use RFO, not WRITEBACK, because a write miss would typically occur
1080 * on RFO.
1081 */
f22f54f4 1082 [ C(OP_WRITE) ] = {
e994d7d2
AK		 1083 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1084 [ C(RESULT_ACCESS) ] = 0x01b7,
1085 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1086 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 1087 },
1088 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 1089 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1090 [ C(RESULT_ACCESS) ] = 0x01b7,
1091 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1092 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 1093 },
1094 },
1095 [ C(DTLB) ] = {
1096 [ C(OP_READ) ] = {
1097 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1098 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1099 },
1100 [ C(OP_WRITE) ] = {
1101 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1102 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1103 },
1104 [ C(OP_PREFETCH) ] = {
1105 [ C(RESULT_ACCESS) ] = 0x0,
1106 [ C(RESULT_MISS) ] = 0x0,
1107 },
1108 },
1109 [ C(ITLB) ] = {
1110 [ C(OP_READ) ] = {
1111 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1112 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1113 },
1114 [ C(OP_WRITE) ] = {
1115 [ C(RESULT_ACCESS) ] = -1,
1116 [ C(RESULT_MISS) ] = -1,
1117 },
1118 [ C(OP_PREFETCH) ] = {
1119 [ C(RESULT_ACCESS) ] = -1,
1120 [ C(RESULT_MISS) ] = -1,
1121 },
1122 },
1123 [ C(BPU ) ] = {
1124 [ C(OP_READ) ] = {
1125 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1126 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1127 },
1128 [ C(OP_WRITE) ] = {
1129 [ C(RESULT_ACCESS) ] = -1,
1130 [ C(RESULT_MISS) ] = -1,
1131 },
1132 [ C(OP_PREFETCH) ] = {
1133 [ C(RESULT_ACCESS) ] = -1,
1134 [ C(RESULT_MISS) ] = -1,
1135 },
1136 },
89d6c0b5
PZ		 1137 [ C(NODE) ] = {
1138 [ C(OP_READ) ] = {
1139 [ C(RESULT_ACCESS) ] = 0x01b7,
1140 [ C(RESULT_MISS) ] = 0x01b7,
1141 },
1142 [ C(OP_WRITE) ] = {
1143 [ C(RESULT_ACCESS) ] = 0x01b7,
1144 [ C(RESULT_MISS) ] = 0x01b7,
1145 },
1146 [ C(OP_PREFETCH) ] = {
1147 [ C(RESULT_ACCESS) ] = 0x01b7,
1148 [ C(RESULT_MISS) ] = 0x01b7,
1149 },
1150 },
f22f54f4
PZ		 1151};
1152
caaa8be3 1153static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 1154 [PERF_COUNT_HW_CACHE_MAX]
1155 [PERF_COUNT_HW_CACHE_OP_MAX]
1156 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1157{
1158 [ C(L1D) ] = {
1159 [ C(OP_READ) ] = {
1160 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1161 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1162 },
1163 [ C(OP_WRITE) ] = {
1164 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1165 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1166 },
1167 [ C(OP_PREFETCH) ] = {
1168 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1169 [ C(RESULT_MISS) ] = 0,
1170 },
1171 },
1172 [ C(L1I ) ] = {
1173 [ C(OP_READ) ] = {
1174 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1175 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1176 },
1177 [ C(OP_WRITE) ] = {
1178 [ C(RESULT_ACCESS) ] = -1,
1179 [ C(RESULT_MISS) ] = -1,
1180 },
1181 [ C(OP_PREFETCH) ] = {
1182 [ C(RESULT_ACCESS) ] = 0,
1183 [ C(RESULT_MISS) ] = 0,
1184 },
1185 },
1186 [ C(LL ) ] = {
1187 [ C(OP_READ) ] = {
1188 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1189 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1190 },
1191 [ C(OP_WRITE) ] = {
1192 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1193 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1194 },
1195 [ C(OP_PREFETCH) ] = {
1196 [ C(RESULT_ACCESS) ] = 0,
1197 [ C(RESULT_MISS) ] = 0,
1198 },
1199 },
1200 [ C(DTLB) ] = {
1201 [ C(OP_READ) ] = {
1202 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1203 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1204 },
1205 [ C(OP_WRITE) ] = {
1206 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1207 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1208 },
1209 [ C(OP_PREFETCH) ] = {
1210 [ C(RESULT_ACCESS) ] = 0,
1211 [ C(RESULT_MISS) ] = 0,
1212 },
1213 },
1214 [ C(ITLB) ] = {
1215 [ C(OP_READ) ] = {
1216 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1217 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1218 },
1219 [ C(OP_WRITE) ] = {
1220 [ C(RESULT_ACCESS) ] = -1,
1221 [ C(RESULT_MISS) ] = -1,
1222 },
1223 [ C(OP_PREFETCH) ] = {
1224 [ C(RESULT_ACCESS) ] = -1,
1225 [ C(RESULT_MISS) ] = -1,
1226 },
1227 },
1228 [ C(BPU ) ] = {
1229 [ C(OP_READ) ] = {
1230 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1231 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1232 },
1233 [ C(OP_WRITE) ] = {
1234 [ C(RESULT_ACCESS) ] = -1,
1235 [ C(RESULT_MISS) ] = -1,
1236 },
1237 [ C(OP_PREFETCH) ] = {
1238 [ C(RESULT_ACCESS) ] = -1,
1239 [ C(RESULT_MISS) ] = -1,
1240 },
1241 },
1242};
1243
caaa8be3 1244static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 1245 [PERF_COUNT_HW_CACHE_MAX]
1246 [PERF_COUNT_HW_CACHE_OP_MAX]
1247 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1248{
1249 [ C(L1D) ] = {
1250 [ C(OP_READ) ] = {
1251 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1252 [ C(RESULT_MISS) ] = 0,
1253 },
1254 [ C(OP_WRITE) ] = {
1255 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1256 [ C(RESULT_MISS) ] = 0,
1257 },
1258 [ C(OP_PREFETCH) ] = {
1259 [ C(RESULT_ACCESS) ] = 0x0,
1260 [ C(RESULT_MISS) ] = 0,
1261 },
1262 },
1263 [ C(L1I ) ] = {
1264 [ C(OP_READ) ] = {
1265 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1266 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1267 },
1268 [ C(OP_WRITE) ] = {
1269 [ C(RESULT_ACCESS) ] = -1,
1270 [ C(RESULT_MISS) ] = -1,
1271 },
1272 [ C(OP_PREFETCH) ] = {
1273 [ C(RESULT_ACCESS) ] = 0,
1274 [ C(RESULT_MISS) ] = 0,
1275 },
1276 },
1277 [ C(LL ) ] = {
1278 [ C(OP_READ) ] = {
1279 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1280 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1281 },
1282 [ C(OP_WRITE) ] = {
1283 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1284 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1285 },
1286 [ C(OP_PREFETCH) ] = {
1287 [ C(RESULT_ACCESS) ] = 0,
1288 [ C(RESULT_MISS) ] = 0,
1289 },
1290 },
1291 [ C(DTLB) ] = {
1292 [ C(OP_READ) ] = {
1293 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1294 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1295 },
1296 [ C(OP_WRITE) ] = {
1297 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1298 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1299 },
1300 [ C(OP_PREFETCH) ] = {
1301 [ C(RESULT_ACCESS) ] = 0,
1302 [ C(RESULT_MISS) ] = 0,
1303 },
1304 },
1305 [ C(ITLB) ] = {
1306 [ C(OP_READ) ] = {
1307 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1308 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1309 },
1310 [ C(OP_WRITE) ] = {
1311 [ C(RESULT_ACCESS) ] = -1,
1312 [ C(RESULT_MISS) ] = -1,
1313 },
1314 [ C(OP_PREFETCH) ] = {
1315 [ C(RESULT_ACCESS) ] = -1,
1316 [ C(RESULT_MISS) ] = -1,
1317 },
1318 },
1319 [ C(BPU ) ] = {
1320 [ C(OP_READ) ] = {
1321 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1322 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1323 },
1324 [ C(OP_WRITE) ] = {
1325 [ C(RESULT_ACCESS) ] = -1,
1326 [ C(RESULT_MISS) ] = -1,
1327 },
1328 [ C(OP_PREFETCH) ] = {
1329 [ C(RESULT_ACCESS) ] = -1,
1330 [ C(RESULT_MISS) ] = -1,
1331 },
1332 },
1333};
1334
1fa64180
YZ		 1335static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1336{
1337 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
06c939c1 1338 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
ae3f011f 1339 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1fa64180
YZ		 1340 EVENT_EXTRA_END
1341};
1342
1343#define SLM_DMND_READ SNB_DMND_DATA_RD
1344#define SLM_DMND_WRITE SNB_DMND_RFO
1345#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1346
1347#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1348#define SLM_LLC_ACCESS SNB_RESP_ANY
1349#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1350
1351static __initconst const u64 slm_hw_cache_extra_regs
1352 [PERF_COUNT_HW_CACHE_MAX]
1353 [PERF_COUNT_HW_CACHE_OP_MAX]
1354 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1355{
1356 [ C(LL ) ] = {
1357 [ C(OP_READ) ] = {
1358 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
6d374056 1359 [ C(RESULT_MISS) ] = 0,
1fa64180
YZ		 1360 },
1361 [ C(OP_WRITE) ] = {
1362 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1363 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1364 },
1365 [ C(OP_PREFETCH) ] = {
1366 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1367 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1368 },
1369 },
1370};
1371
1372static __initconst const u64 slm_hw_cache_event_ids
1373 [PERF_COUNT_HW_CACHE_MAX]
1374 [PERF_COUNT_HW_CACHE_OP_MAX]
1375 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1376{
1377 [ C(L1D) ] = {
1378 [ C(OP_READ) ] = {
1379 [ C(RESULT_ACCESS) ] = 0,
1380 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1381 },
1382 [ C(OP_WRITE) ] = {
1383 [ C(RESULT_ACCESS) ] = 0,
1384 [ C(RESULT_MISS) ] = 0,
1385 },
1386 [ C(OP_PREFETCH) ] = {
1387 [ C(RESULT_ACCESS) ] = 0,
1388 [ C(RESULT_MISS) ] = 0,
1389 },
1390 },
1391 [ C(L1I ) ] = {
1392 [ C(OP_READ) ] = {
1393 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1394 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1395 },
1396 [ C(OP_WRITE) ] = {
1397 [ C(RESULT_ACCESS) ] = -1,
1398 [ C(RESULT_MISS) ] = -1,
1399 },
1400 [ C(OP_PREFETCH) ] = {
1401 [ C(RESULT_ACCESS) ] = 0,
1402 [ C(RESULT_MISS) ] = 0,
1403 },
1404 },
1405 [ C(LL ) ] = {
1406 [ C(OP_READ) ] = {
1407 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1408 [ C(RESULT_ACCESS) ] = 0x01b7,
6d374056 1409 [ C(RESULT_MISS) ] = 0,
1fa64180
YZ		 1410 },
1411 [ C(OP_WRITE) ] = {
1412 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1413 [ C(RESULT_ACCESS) ] = 0x01b7,
1414 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1415 [ C(RESULT_MISS) ] = 0x01b7,
1416 },
1417 [ C(OP_PREFETCH) ] = {
1418 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1419 [ C(RESULT_ACCESS) ] = 0x01b7,
1420 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1421 [ C(RESULT_MISS) ] = 0x01b7,
1422 },
1423 },
1424 [ C(DTLB) ] = {
1425 [ C(OP_READ) ] = {
1426 [ C(RESULT_ACCESS) ] = 0,
1427 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1428 },
1429 [ C(OP_WRITE) ] = {
1430 [ C(RESULT_ACCESS) ] = 0,
1431 [ C(RESULT_MISS) ] = 0,
1432 },
1433 [ C(OP_PREFETCH) ] = {
1434 [ C(RESULT_ACCESS) ] = 0,
1435 [ C(RESULT_MISS) ] = 0,
1436 },
1437 },
1438 [ C(ITLB) ] = {
1439 [ C(OP_READ) ] = {
1440 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
6d374056 1441 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1fa64180
YZ		 1442 },
1443 [ C(OP_WRITE) ] = {
1444 [ C(RESULT_ACCESS) ] = -1,
1445 [ C(RESULT_MISS) ] = -1,
1446 },
1447 [ C(OP_PREFETCH) ] = {
1448 [ C(RESULT_ACCESS) ] = -1,
1449 [ C(RESULT_MISS) ] = -1,
1450 },
1451 },
1452 [ C(BPU ) ] = {
1453 [ C(OP_READ) ] = {
1454 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1455 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1456 },
1457 [ C(OP_WRITE) ] = {
1458 [ C(RESULT_ACCESS) ] = -1,
1459 [ C(RESULT_MISS) ] = -1,
1460 },
1461 [ C(OP_PREFETCH) ] = {
1462 [ C(RESULT_ACCESS) ] = -1,
1463 [ C(RESULT_MISS) ] = -1,
1464 },
1465 },
1466};
1467
1e7b9390
HC		 1468#define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
1469#define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
1470#define KNL_MCDRAM_LOCAL BIT_ULL(21)
1471#define KNL_MCDRAM_FAR BIT_ULL(22)
1472#define KNL_DDR_LOCAL BIT_ULL(23)
1473#define KNL_DDR_FAR BIT_ULL(24)
1474#define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1475 KNL_DDR_LOCAL | KNL_DDR_FAR)
1476#define KNL_L2_READ SLM_DMND_READ
1477#define KNL_L2_WRITE SLM_DMND_WRITE
1478#define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1479#define KNL_L2_ACCESS SLM_LLC_ACCESS
1480#define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1481 KNL_DRAM_ANY | SNB_SNP_ANY | \
1482 SNB_NON_DRAM)
1483
1484static __initconst const u64 knl_hw_cache_extra_regs
1485 [PERF_COUNT_HW_CACHE_MAX]
1486 [PERF_COUNT_HW_CACHE_OP_MAX]
1487 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1488 [C(LL)] = {
1489 [C(OP_READ)] = {
1490 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1491 [C(RESULT_MISS)] = 0,
1492 },
1493 [C(OP_WRITE)] = {
1494 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1495 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1496 },
1497 [C(OP_PREFETCH)] = {
1498 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1499 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
1500 },
1501 },
1502};
1503
1a78d937 1504/*
c3d266c8
KL		 1505 * Used from PMIs where the LBRs are already disabled.
1506 *
1507 * This function could be called consecutively. It is required to remain in
1508 * disabled state if called consecutively.
1509 *
1510 * During consecutive calls, the same disable value will be written to related
1511 * registers, so the PMU state remains unchanged. hw.state in
1512 * intel_bts_disable_local will remain PERF_HES_STOPPED too in consecutive
1513 * calls.
1a78d937
AK		 1514 */
1515static void __intel_pmu_disable_all(void)
f22f54f4 1516{
89cbc767 1517 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4
PZ		 1518
1519 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1520
15c7ad51 1521 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 1522 intel_pmu_disable_bts();
8062382c
AS		 1523 else
1524 intel_bts_disable_local();
ca037701
PZ		 1525
1526 intel_pmu_pebs_disable_all();
1a78d937
AK		 1527}
1528
1529static void intel_pmu_disable_all(void)
1530{
1531 __intel_pmu_disable_all();
caff2bef 1532 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 1533}
1534
1a78d937 1535static void __intel_pmu_enable_all(int added, bool pmi)
f22f54f4 1536{
89cbc767 1537 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1538
d329527e 1539 intel_pmu_pebs_enable_all();
1a78d937 1540 intel_pmu_lbr_enable_all(pmi);
144d31e6
GN		 1541 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1542 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 1543
15c7ad51 1544 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 1545 struct perf_event *event =
15c7ad51 1546 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 1547
1548 if (WARN_ON_ONCE(!event))
1549 return;
1550
1551 intel_pmu_enable_bts(event->hw.config);
8062382c
AS		 1552 } else
1553 intel_bts_enable_local();
f22f54f4
PZ		 1554}
1555
1a78d937
AK		 1556static void intel_pmu_enable_all(int added)
1557{
1558 __intel_pmu_enable_all(added, false);
1559}
1560
11164cd4
PZ		 1561/*
1562 * Workaround for:
1563 * Intel Errata AAK100 (model 26)
1564 * Intel Errata AAP53 (model 30)
40b91cd1 1565 * Intel Errata BD53 (model 44)
11164cd4 1566 *
351af072
ZY		 1567 * The official story:
1568 * These chips need to be 'reset' when adding counters by programming the
1569 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1570 * in sequence on the same PMC or on different PMCs.
1571 *
1572 * In practise it appears some of these events do in fact count, and
1573 * we need to programm all 4 events.
11164cd4 1574 */
351af072 1575static void intel_pmu_nhm_workaround(void)
11164cd4 1576{
89cbc767 1577 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
351af072
ZY		 1578 static const unsigned long nhm_magic[4] = {
1579 0x4300B5,
1580 0x4300D2,
1581 0x4300B1,
1582 0x4300B1
1583 };
1584 struct perf_event *event;
1585 int i;
11164cd4 1586
351af072
ZY		 1587 /*
1588 * The Errata requires below steps:
1589 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1590 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1591 * the corresponding PMCx;
1592 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1593 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1594 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1595 */
11164cd4 1596
351af072
ZY		 1597 /*
1598 * The real steps we choose are a little different from above.
1599 * A) To reduce MSR operations, we don't run step 1) as they
1600 * are already cleared before this function is called;
1601 * B) Call x86_perf_event_update to save PMCx before configuring
1602 * PERFEVTSELx with magic number;
1603 * C) With step 5), we do clear only when the PERFEVTSELx is
1604 * not used currently.
1605 * D) Call x86_perf_event_set_period to restore PMCx;
1606 */
11164cd4 1607
351af072
ZY		 1608 /* We always operate 4 pairs of PERF Counters */
1609 for (i = 0; i < 4; i++) {
1610 event = cpuc->events[i];
1611 if (event)
1612 x86_perf_event_update(event);
1613 }
11164cd4 1614
351af072
ZY		 1615 for (i = 0; i < 4; i++) {
1616 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1617 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1618 }
1619
1620 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1621 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 1622
351af072
ZY		 1623 for (i = 0; i < 4; i++) {
1624 event = cpuc->events[i];
1625
1626 if (event) {
1627 x86_perf_event_set_period(event);
31fa58af 1628 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 1629 ARCH_PERFMON_EVENTSEL_ENABLE);
1630 } else
1631 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 1632 }
351af072
ZY		 1633}
1634
1635static void intel_pmu_nhm_enable_all(int added)
1636{
1637 if (added)
1638 intel_pmu_nhm_workaround();
11164cd4
PZ		 1639 intel_pmu_enable_all(added);
1640}
1641
f22f54f4
PZ		 1642static inline u64 intel_pmu_get_status(void)
1643{
1644 u64 status;
1645
1646 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1647
1648 return status;
1649}
1650
1651static inline void intel_pmu_ack_status(u64 ack)
1652{
1653 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1654}
1655
ca037701 1656static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 1657{
15c7ad51 1658 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 1659 u64 ctrl_val, mask;
1660
1661 mask = 0xfULL << (idx * 4);
1662
1663 rdmsrl(hwc->config_base, ctrl_val);
1664 ctrl_val &= ~mask;
7645a24c 1665 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1666}
1667
2b9e344d
PZ		 1668static inline bool event_is_checkpointed(struct perf_event *event)
1669{
1670 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1671}
1672
ca037701 1673static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 1674{
aff3d91a 1675 struct hw_perf_event *hwc = &event->hw;
89cbc767 1676 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1677
15c7ad51 1678 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 1679 intel_pmu_disable_bts();
1680 intel_pmu_drain_bts_buffer();
1681 return;
1682 }
1683
144d31e6
GN		 1684 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1685 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
2b9e344d 1686 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
144d31e6 1687
60ce0fbd
SE		 1688 /*
1689 * must disable before any actual event
1690 * because any event may be combined with LBR
1691 */
a46a2300 1692 if (needs_branch_stack(event))
60ce0fbd
SE		 1693 intel_pmu_lbr_disable(event);
1694
f22f54f4 1695 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1696 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 1697 return;
1698 }
1699
aff3d91a 1700 x86_pmu_disable_event(event);
ca037701 1701
ab608344 1702 if (unlikely(event->attr.precise_ip))
ef21f683 1703 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 1704}
1705
ca037701 1706static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 1707{
15c7ad51 1708 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 1709 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1710
1711 /*
1712 * Enable IRQ generation (0x8),
1713 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1714 * if requested:
1715 */
1716 bits = 0x8ULL;
1717 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1718 bits |= 0x2;
1719 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1720 bits |= 0x1;
1721
1722 /*
1723 * ANY bit is supported in v3 and up
1724 */
1725 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1726 bits |= 0x4;
1727
1728 bits <<= (idx * 4);
1729 mask = 0xfULL << (idx * 4);
1730
1731 rdmsrl(hwc->config_base, ctrl_val);
1732 ctrl_val &= ~mask;
1733 ctrl_val |= bits;
7645a24c 1734 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1735}
1736
aff3d91a 1737static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1738{
aff3d91a 1739 struct hw_perf_event *hwc = &event->hw;
89cbc767 1740 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1741
15c7ad51 1742 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1743 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1744 return;
1745
1746 intel_pmu_enable_bts(hwc->config);
1747 return;
1748 }
60ce0fbd
SE		 1749 /*
1750 * must enabled before any actual event
1751 * because any event may be combined with LBR
1752 */
a46a2300 1753 if (needs_branch_stack(event))
60ce0fbd 1754 intel_pmu_lbr_enable(event);
f22f54f4 1755
144d31e6
GN		 1756 if (event->attr.exclude_host)
1757 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1758 if (event->attr.exclude_guest)
1759 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1760
2b9e344d
PZ		 1761 if (unlikely(event_is_checkpointed(event)))
1762 cpuc->intel_cp_status |= (1ull << hwc->idx);
1763
f22f54f4 1764 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1765 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1766 return;
1767 }
1768
ab608344 1769 if (unlikely(event->attr.precise_ip))
ef21f683 1770 intel_pmu_pebs_enable(event);
ca037701 1771
31fa58af 1772 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1773}
1774
1775/*
1776 * Save and restart an expired event. Called by NMI contexts,
1777 * so it has to be careful about preempting normal event ops:
1778 */
de0428a7 1779int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 1780{
cc2ad4ba 1781 x86_perf_event_update(event);
2dbf0116
AK		 1782 /*
1783 * For a checkpointed counter always reset back to 0. This
1784 * avoids a situation where the counter overflows, aborts the
1785 * transaction and is then set back to shortly before the
1786 * overflow, and overflows and aborts again.
1787 */
1788 if (unlikely(event_is_checkpointed(event))) {
1789 /* No race with NMIs because the counter should not be armed */
1790 wrmsrl(event->hw.event_base, 0);
1791 local64_set(&event->hw.prev_count, 0);
1792 }
cc2ad4ba 1793 return x86_perf_event_set_period(event);
f22f54f4
PZ		 1794}
1795
1796static void intel_pmu_reset(void)
1797{
0a3aee0d 1798 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 1799 unsigned long flags;
1800 int idx;
1801
948b1bb8 1802 if (!x86_pmu.num_counters)
f22f54f4
PZ		 1803 return;
1804
1805 local_irq_save(flags);
1806
c767a54b 1807 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 1808
948b1bb8 1809 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 1810 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1811 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 1812 }
948b1bb8 1813 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 1814 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 1815
f22f54f4
PZ		 1816 if (ds)
1817 ds->bts_index = ds->bts_buffer_base;
1818
8882edf7
AK		 1819 /* Ack all overflows and disable fixed counters */
1820 if (x86_pmu.version >= 2) {
1821 intel_pmu_ack_status(intel_pmu_get_status());
1822 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1823 }
1824
1825 /* Reset LBRs and LBR freezing */
1826 if (x86_pmu.lbr_nr) {
1827 update_debugctlmsr(get_debugctlmsr() &
1828 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
1829 }
1830
f22f54f4
PZ		 1831 local_irq_restore(flags);
1832}
1833
1834/*
1835 * This handler is triggered by the local APIC, so the APIC IRQ handling
1836 * rules apply:
1837 */
1838static int intel_pmu_handle_irq(struct pt_regs *regs)
1839{
1840 struct perf_sample_data data;
1841 struct cpu_hw_events *cpuc;
1842 int bit, loops;
2e556b5b 1843 u64 status;
b0b2072d 1844 int handled;
f22f54f4 1845
89cbc767 1846 cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1847
2bce5dac 1848 /*
72db5596
AK		 1849 * No known reason to not always do late ACK,
1850 * but just in case do it opt-in.
2bce5dac 1851 */
72db5596
AK		 1852 if (!x86_pmu.late_ack)
1853 apic_write(APIC_LVTPC, APIC_DM_NMI);
1a78d937 1854 __intel_pmu_disable_all();
b0b2072d 1855 handled = intel_pmu_drain_bts_buffer();
8062382c 1856 handled += intel_bts_interrupt();
f22f54f4 1857 status = intel_pmu_get_status();
a3ef2229
MM		 1858 if (!status)
1859 goto done;
f22f54f4
PZ		 1860
1861 loops = 0;
1862again:
0f29e573 1863 intel_pmu_lbr_read();
2e556b5b 1864 intel_pmu_ack_status(status);
f22f54f4 1865 if (++loops > 100) {
ae0def05
DH		 1866 static bool warned = false;
1867 if (!warned) {
1868 WARN(1, "perfevents: irq loop stuck!\n");
1869 perf_event_print_debug();
1870 warned = true;
1871 }
f22f54f4 1872 intel_pmu_reset();
3fb2b8dd 1873 goto done;
f22f54f4
PZ		 1874 }
1875
1876 inc_irq_stat(apic_perf_irqs);
ca037701 1877
caff2bef 1878
b292d7a1 1879 /*
d8020bee
AK		 1880 * Ignore a range of extra bits in status that do not indicate
1881 * overflow by themselves.
b292d7a1 1882 */
d8020bee
AK		 1883 status &= ~(GLOBAL_STATUS_COND_CHG |
1884 GLOBAL_STATUS_ASIF |
1885 GLOBAL_STATUS_LBRS_FROZEN);
1886 if (!status)
1887 goto done;
b292d7a1 1888
ca037701
PZ		 1889 /*
1890 * PEBS overflow sets bit 62 in the global status register
1891 */
de725dec
PZ		 1892 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1893 handled++;
ca037701 1894 x86_pmu.drain_pebs(regs);
de725dec 1895 }
ca037701 1896
52ca9ced
AS		 1897 /*
1898 * Intel PT
1899 */
1900 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
1901 handled++;
1902 intel_pt_interrupt();
1903 }
1904
2dbf0116 1905 /*
2b9e344d
PZ		 1906 * Checkpointed counters can lead to 'spurious' PMIs because the
1907 * rollback caused by the PMI will have cleared the overflow status
1908 * bit. Therefore always force probe these counters.
2dbf0116 1909 */
2b9e344d 1910 status |= cpuc->intel_cp_status;
2dbf0116 1911
984b3f57 1912 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 1913 struct perf_event *event = cpuc->events[bit];
1914
de725dec
PZ		 1915 handled++;
1916
f22f54f4
PZ		 1917 if (!test_bit(bit, cpuc->active_mask))
1918 continue;
1919
1920 if (!intel_pmu_save_and_restart(event))
1921 continue;
1922
fd0d000b 1923 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 1924
60ce0fbd
SE		 1925 if (has_branch_stack(event))
1926 data.br_stack = &cpuc->lbr_stack;
1927
a8b0ca17 1928 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 1929 x86_pmu_stop(event, 0);
f22f54f4
PZ		 1930 }
1931
f22f54f4
PZ		 1932 /*
1933 * Repeat if there is more work to be done:
1934 */
1935 status = intel_pmu_get_status();
1936 if (status)
1937 goto again;
1938
3fb2b8dd 1939done:
c3d266c8
KL		 1940 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
1941 if (cpuc->enabled)
1942 __intel_pmu_enable_all(0, true);
1943
72db5596
AK		 1944 /*
1945 * Only unmask the NMI after the overflow counters
1946 * have been reset. This avoids spurious NMIs on
1947 * Haswell CPUs.
1948 */
1949 if (x86_pmu.late_ack)
1950 apic_write(APIC_LVTPC, APIC_DM_NMI);
de725dec 1951 return handled;
f22f54f4
PZ		 1952}
1953
f22f54f4 1954static struct event_constraint *
ca037701 1955intel_bts_constraints(struct perf_event *event)
f22f54f4 1956{
ca037701
PZ		 1957 struct hw_perf_event *hwc = &event->hw;
1958 unsigned int hw_event, bts_event;
f22f54f4 1959
18a073a3
PZ		 1960 if (event->attr.freq)
1961 return NULL;
1962
ca037701
PZ		 1963 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1964 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1965
ca037701 1966 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1967 return &bts_constraint;
ca037701 1968
f22f54f4
PZ		 1969 return NULL;
1970}
1971
ae3f011f 1972static int intel_alt_er(int idx, u64 config)
b79e8941 1973{
e01d8718
PZ		 1974 int alt_idx = idx;
1975
9a5e3fb5 1976 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
5a425294 1977 return idx;
b79e8941 1978
5a425294 1979 if (idx == EXTRA_REG_RSP_0)
ae3f011f 1980 alt_idx = EXTRA_REG_RSP_1;
5a425294
PZ		 1981
1982 if (idx == EXTRA_REG_RSP_1)
ae3f011f 1983 alt_idx = EXTRA_REG_RSP_0;
5a425294 1984
ae3f011f
KL		 1985 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
1986 return idx;
1987
1988 return alt_idx;
5a425294
PZ		 1989}
1990
1991static void intel_fixup_er(struct perf_event *event, int idx)
1992{
1993 event->hw.extra_reg.idx = idx;
1994
1995 if (idx == EXTRA_REG_RSP_0) {
b79e8941 1996 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1997 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
b79e8941 1998 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 1999 } else if (idx == EXTRA_REG_RSP_1) {
2000 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 2001 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
5a425294 2002 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 2003 }
b79e8941
PZ		 2004}
2005
efc9f05d
SE		 2006/*
2007 * manage allocation of shared extra msr for certain events
2008 *
2009 * sharing can be:
2010 * per-cpu: to be shared between the various events on a single PMU
2011 * per-core: per-cpu + shared by HT threads
2012 */
a7e3ed1e 2013static struct event_constraint *
efc9f05d 2014__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 2015 struct perf_event *event,
2016 struct hw_perf_event_extra *reg)
a7e3ed1e 2017{
efc9f05d 2018 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 2019 struct er_account *era;
cd8a38d3 2020 unsigned long flags;
5a425294 2021 int idx = reg->idx;
a7e3ed1e 2022
5a425294
PZ		 2023 /*
2024 * reg->alloc can be set due to existing state, so for fake cpuc we
2025 * need to ignore this, otherwise we might fail to allocate proper fake
2026 * state for this extra reg constraint. Also see the comment below.
2027 */
2028 if (reg->alloc && !cpuc->is_fake)
b36817e8 2029 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 2030
b79e8941 2031again:
5a425294 2032 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 2033 /*
2034 * we use spin_lock_irqsave() to avoid lockdep issues when
2035 * passing a fake cpuc
2036 */
2037 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 2038
2039 if (!atomic_read(&era->ref) || era->config == reg->config) {
2040
5a425294
PZ		 2041 /*
2042 * If its a fake cpuc -- as per validate_{group,event}() we
2043 * shouldn't touch event state and we can avoid doing so
2044 * since both will only call get_event_constraints() once
2045 * on each event, this avoids the need for reg->alloc.
2046 *
2047 * Not doing the ER fixup will only result in era->reg being
2048 * wrong, but since we won't actually try and program hardware
2049 * this isn't a problem either.
2050 */
2051 if (!cpuc->is_fake) {
2052 if (idx != reg->idx)
2053 intel_fixup_er(event, idx);
2054
2055 /*
2056 * x86_schedule_events() can call get_event_constraints()
2057 * multiple times on events in the case of incremental
2058 * scheduling(). reg->alloc ensures we only do the ER
2059 * allocation once.
2060 */
2061 reg->alloc = 1;
2062 }
2063
efc9f05d
SE		 2064 /* lock in msr value */
2065 era->config = reg->config;
2066 era->reg = reg->reg;
2067
2068 /* one more user */
2069 atomic_inc(&era->ref);
2070
a7e3ed1e 2071 /*
b36817e8
SE		 2072 * need to call x86_get_event_constraint()
2073 * to check if associated event has constraints
a7e3ed1e 2074 */
b36817e8 2075 c = NULL;
5a425294 2076 } else {
ae3f011f 2077 idx = intel_alt_er(idx, reg->config);
5a425294
PZ		 2078 if (idx != reg->idx) {
2079 raw_spin_unlock_irqrestore(&era->lock, flags);
2080 goto again;
2081 }
a7e3ed1e 2082 }
cd8a38d3 2083 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 2084
efc9f05d
SE		 2085 return c;
2086}
2087
2088static void
2089__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2090 struct hw_perf_event_extra *reg)
2091{
2092 struct er_account *era;
2093
2094 /*
5a425294
PZ		 2095 * Only put constraint if extra reg was actually allocated. Also takes
2096 * care of event which do not use an extra shared reg.
2097 *
2098 * Also, if this is a fake cpuc we shouldn't touch any event state
2099 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2100 * either since it'll be thrown out.
efc9f05d 2101 */
5a425294 2102 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 2103 return;
2104
2105 era = &cpuc->shared_regs->regs[reg->idx];
2106
2107 /* one fewer user */
2108 atomic_dec(&era->ref);
2109
2110 /* allocate again next time */
2111 reg->alloc = 0;
2112}
2113
2114static struct event_constraint *
2115intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2116 struct perf_event *event)
2117{
b36817e8
SE		 2118 struct event_constraint *c = NULL, *d;
2119 struct hw_perf_event_extra *xreg, *breg;
2120
2121 xreg = &event->hw.extra_reg;
2122 if (xreg->idx != EXTRA_REG_NONE) {
2123 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2124 if (c == &emptyconstraint)
2125 return c;
2126 }
2127 breg = &event->hw.branch_reg;
2128 if (breg->idx != EXTRA_REG_NONE) {
2129 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2130 if (d == &emptyconstraint) {
2131 __intel_shared_reg_put_constraints(cpuc, xreg);
2132 c = d;
2133 }
2134 }
efc9f05d 2135 return c;
a7e3ed1e
AK		 2136}
2137
de0428a7 2138struct event_constraint *
79cba822
SE		 2139x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2140 struct perf_event *event)
de0428a7
KW		 2141{
2142 struct event_constraint *c;
2143
2144 if (x86_pmu.event_constraints) {
2145 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3 2146 if ((event->hw.config & c->cmask) == c->code) {
9fac2cf3 2147 event->hw.flags |= c->flags;
de0428a7 2148 return c;
9fac2cf3 2149 }
de0428a7
KW		 2150 }
2151 }
2152
2153 return &unconstrained;
2154}
2155
f22f54f4 2156static struct event_constraint *
e979121b 2157__intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
79cba822 2158 struct perf_event *event)
f22f54f4
PZ		 2159{
2160 struct event_constraint *c;
2161
ca037701
PZ		 2162 c = intel_bts_constraints(event);
2163 if (c)
2164 return c;
2165
687805e4 2166 c = intel_shared_regs_constraints(cpuc, event);
f22f54f4
PZ		 2167 if (c)
2168 return c;
2169
687805e4 2170 c = intel_pebs_constraints(event);
a7e3ed1e
AK		 2171 if (c)
2172 return c;
2173
79cba822 2174 return x86_get_event_constraints(cpuc, idx, event);
f22f54f4
PZ		 2175}
2176
e979121b
MD		 2177static void
2178intel_start_scheduling(struct cpu_hw_events *cpuc)
2179{
2180 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2181 struct intel_excl_states *xl;
e979121b 2182 int tid = cpuc->excl_thread_id;
e979121b
MD		 2183
2184 /*
2185 * nothing needed if in group validation mode
2186 */
b37609c3 2187 if (cpuc->is_fake || !is_ht_workaround_enabled())
e979121b 2188 return;
b37609c3 2189
e979121b
MD		 2190 /*
2191 * no exclusion needed
2192 */
17186ccd 2193 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2194 return;
2195
e979121b
MD		 2196 xl = &excl_cntrs->states[tid];
2197
2198 xl->sched_started = true;
e979121b
MD		 2199 /*
2200 * lock shared state until we are done scheduling
2201 * in stop_event_scheduling()
2202 * makes scheduling appear as a transaction
2203 */
e979121b 2204 raw_spin_lock(&excl_cntrs->lock);
e979121b
MD		 2205}
2206
0c41e756
PZ		 2207static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2208{
2209 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2210 struct event_constraint *c = cpuc->event_constraint[idx];
2211 struct intel_excl_states *xl;
2212 int tid = cpuc->excl_thread_id;
2213
2214 if (cpuc->is_fake || !is_ht_workaround_enabled())
2215 return;
2216
2217 if (WARN_ON_ONCE(!excl_cntrs))
2218 return;
2219
2220 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2221 return;
2222
2223 xl = &excl_cntrs->states[tid];
2224
2225 lockdep_assert_held(&excl_cntrs->lock);
2226
1fe684e3 2227 if (c->flags & PERF_X86_EVENT_EXCL)
43ef205b 2228 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
1fe684e3 2229 else
43ef205b 2230 xl->state[cntr] = INTEL_EXCL_SHARED;
0c41e756
PZ		 2231}
2232
e979121b
MD		 2233static void
2234intel_stop_scheduling(struct cpu_hw_events *cpuc)
2235{
2236 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2237 struct intel_excl_states *xl;
e979121b 2238 int tid = cpuc->excl_thread_id;
e979121b
MD		 2239
2240 /*
2241 * nothing needed if in group validation mode
2242 */
b37609c3 2243 if (cpuc->is_fake || !is_ht_workaround_enabled())
e979121b
MD		 2244 return;
2245 /*
2246 * no exclusion needed
2247 */
17186ccd 2248 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2249 return;
2250
e979121b
MD		 2251 xl = &excl_cntrs->states[tid];
2252
e979121b
MD		 2253 xl->sched_started = false;
2254 /*
2255 * release shared state lock (acquired in intel_start_scheduling())
2256 */
2257 raw_spin_unlock(&excl_cntrs->lock);
2258}
2259
2260static struct event_constraint *
2261intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2262 int idx, struct event_constraint *c)
2263{
e979121b 2264 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2265 struct intel_excl_states *xlo;
e979121b 2266 int tid = cpuc->excl_thread_id;
1c565833 2267 int is_excl, i;
e979121b
MD		 2268
2269 /*
2270 * validating a group does not require
2271 * enforcing cross-thread exclusion
2272 */
b37609c3
SE		 2273 if (cpuc->is_fake || !is_ht_workaround_enabled())
2274 return c;
2275
2276 /*
2277 * no exclusion needed
2278 */
17186ccd 2279 if (WARN_ON_ONCE(!excl_cntrs))
e979121b 2280 return c;
e979121b 2281
e979121b
MD		 2282 /*
2283 * because we modify the constraint, we need
2284 * to make a copy. Static constraints come
2285 * from static const tables.
2286 *
2287 * only needed when constraint has not yet
2288 * been cloned (marked dynamic)
2289 */
2290 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
aaf932e8 2291 struct event_constraint *cx;
e979121b 2292
e979121b
MD		 2293 /*
2294 * grab pre-allocated constraint entry
2295 */
2296 cx = &cpuc->constraint_list[idx];
2297
2298 /*
2299 * initialize dynamic constraint
2300 * with static constraint
2301 */
aaf932e8 2302 *cx = *c;
e979121b
MD		 2303
2304 /*
2305 * mark constraint as dynamic, so we
2306 * can free it later on
2307 */
2308 cx->flags |= PERF_X86_EVENT_DYNAMIC;
aaf932e8 2309 c = cx;
e979121b
MD		 2310 }
2311
2312 /*
2313 * From here on, the constraint is dynamic.
2314 * Either it was just allocated above, or it
2315 * was allocated during a earlier invocation
2316 * of this function
2317 */
2318
1c565833
PZ		 2319 /*
2320 * state of sibling HT
2321 */
2322 xlo = &excl_cntrs->states[tid ^ 1];
2323
2324 /*
2325 * event requires exclusive counter access
2326 * across HT threads
2327 */
2328 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2329 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2330 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2331 if (!cpuc->n_excl++)
2332 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2333 }
2334
e979121b
MD		 2335 /*
2336 * Modify static constraint with current dynamic
2337 * state of thread
2338 *
2339 * EXCLUSIVE: sibling counter measuring exclusive event
2340 * SHARED : sibling counter measuring non-exclusive event
2341 * UNUSED : sibling counter unused
2342 */
aaf932e8 2343 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
e979121b
MD		 2344 /*
2345 * exclusive event in sibling counter
2346 * our corresponding counter cannot be used
2347 * regardless of our event
2348 */
1c565833 2349 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
aaf932e8 2350 __clear_bit(i, c->idxmsk);
e979121b
MD		 2351 /*
2352 * if measuring an exclusive event, sibling
2353 * measuring non-exclusive, then counter cannot
2354 * be used
2355 */
1c565833 2356 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED)
aaf932e8 2357 __clear_bit(i, c->idxmsk);
e979121b
MD		 2358 }
2359
2360 /*
2361 * recompute actual bit weight for scheduling algorithm
2362 */
aaf932e8 2363 c->weight = hweight64(c->idxmsk64);
e979121b
MD		 2364
2365 /*
2366 * if we return an empty mask, then switch
2367 * back to static empty constraint to avoid
2368 * the cost of freeing later on
2369 */
aaf932e8
PZ		 2370 if (c->weight == 0)
2371 c = &emptyconstraint;
e979121b 2372
aaf932e8 2373 return c;
e979121b
MD		 2374}
2375
2376static struct event_constraint *
2377intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2378 struct perf_event *event)
2379{
ebfb4988 2380 struct event_constraint *c1 = NULL;
a90738c2 2381 struct event_constraint *c2;
e979121b 2382
ebfb4988
PZ		 2383 if (idx >= 0) /* fake does < 0 */
2384 c1 = cpuc->event_constraint[idx];
2385
e979121b
MD		 2386 /*
2387 * first time only
2388 * - static constraint: no change across incremental scheduling calls
2389 * - dynamic constraint: handled by intel_get_excl_constraints()
2390 */
a90738c2
SE		 2391 c2 = __intel_get_event_constraints(cpuc, idx, event);
2392 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2393 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2394 c1->weight = c2->weight;
2395 c2 = c1;
2396 }
e979121b
MD		 2397
2398 if (cpuc->excl_cntrs)
a90738c2 2399 return intel_get_excl_constraints(cpuc, event, idx, c2);
e979121b 2400
a90738c2 2401 return c2;
e979121b
MD		 2402}
2403
2404static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2405 struct perf_event *event)
2406{
2407 struct hw_perf_event *hwc = &event->hw;
2408 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
e979121b 2409 int tid = cpuc->excl_thread_id;
1c565833 2410 struct intel_excl_states *xl;
e979121b
MD		 2411
2412 /*
2413 * nothing needed if in group validation mode
2414 */
2415 if (cpuc->is_fake)
2416 return;
2417
17186ccd 2418 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2419 return;
2420
cc1790cf
PZ		 2421 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2422 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2423 if (!--cpuc->n_excl)
2424 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2425 }
e979121b
MD		 2426
2427 /*
ba040653
PZ		 2428 * If event was actually assigned, then mark the counter state as
2429 * unused now.
e979121b 2430 */
ba040653
PZ		 2431 if (hwc->idx >= 0) {
2432 xl = &excl_cntrs->states[tid];
2433
2434 /*
2435 * put_constraint may be called from x86_schedule_events()
2436 * which already has the lock held so here make locking
2437 * conditional.
2438 */
2439 if (!xl->sched_started)
2440 raw_spin_lock(&excl_cntrs->lock);
e979121b 2441
1c565833 2442 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
e979121b 2443
ba040653
PZ		 2444 if (!xl->sched_started)
2445 raw_spin_unlock(&excl_cntrs->lock);
2446 }
e979121b
MD		 2447}
2448
efc9f05d
SE		 2449static void
2450intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 2451 struct perf_event *event)
2452{
efc9f05d 2453 struct hw_perf_event_extra *reg;
a7e3ed1e 2454
efc9f05d
SE		 2455 reg = &event->hw.extra_reg;
2456 if (reg->idx != EXTRA_REG_NONE)
2457 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 2458
2459 reg = &event->hw.branch_reg;
2460 if (reg->idx != EXTRA_REG_NONE)
2461 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 2462}
a7e3ed1e 2463
efc9f05d
SE		 2464static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2465 struct perf_event *event)
2466{
2467 intel_put_shared_regs_event_constraints(cpuc, event);
e979121b
MD		 2468
2469 /*
2470 * is PMU has exclusive counter restrictions, then
2471 * all events are subject to and must call the
2472 * put_excl_constraints() routine
2473 */
b371b594 2474 if (cpuc->excl_cntrs)
e979121b 2475 intel_put_excl_constraints(cpuc, event);
e979121b
MD		 2476}
2477
0780c927 2478static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 2479{
0780c927 2480 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 2481 /*
2482 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2483 * (0x003c) so that we can use it with PEBS.
2484 *
2485 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2486 * PEBS capable. However we can use INST_RETIRED.ANY_P
2487 * (0x00c0), which is a PEBS capable event, to get the same
2488 * count.
2489 *
2490 * INST_RETIRED.ANY_P counts the number of cycles that retires
2491 * CNTMASK instructions. By setting CNTMASK to a value (16)
2492 * larger than the maximum number of instructions that can be
2493 * retired per cycle (4) and then inverting the condition, we
2494 * count all cycles that retire 16 or less instructions, which
2495 * is every cycle.
2496 *
2497 * Thereby we gain a PEBS capable cycle counter.
2498 */
f9b4eeb8
PZ		 2499 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2500
0780c927
PZ		 2501 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2502 event->hw.config = alt_config;
2503 }
2504}
2505
2506static void intel_pebs_aliases_snb(struct perf_event *event)
2507{
2508 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2509 /*
2510 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2511 * (0x003c) so that we can use it with PEBS.
2512 *
2513 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2514 * PEBS capable. However we can use UOPS_RETIRED.ALL
2515 * (0x01c2), which is a PEBS capable event, to get the same
2516 * count.
2517 *
2518 * UOPS_RETIRED.ALL counts the number of cycles that retires
2519 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2520 * larger than the maximum number of micro-ops that can be
2521 * retired per cycle (4) and then inverting the condition, we
2522 * count all cycles that retire 16 or less micro-ops, which
2523 * is every cycle.
2524 *
2525 * Thereby we gain a PEBS capable cycle counter.
2526 */
2527 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 2528
2529 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2530 event->hw.config = alt_config;
2531 }
0780c927
PZ		 2532}
2533
72469764
AK		 2534static void intel_pebs_aliases_precdist(struct perf_event *event)
2535{
2536 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2537 /*
2538 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2539 * (0x003c) so that we can use it with PEBS.
2540 *
2541 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2542 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
2543 * (0x01c0), which is a PEBS capable event, to get the same
2544 * count.
2545 *
2546 * The PREC_DIST event has special support to minimize sample
2547 * shadowing effects. One drawback is that it can be
2548 * only programmed on counter 1, but that seems like an
2549 * acceptable trade off.
2550 */
2551 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
2552
2553 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2554 event->hw.config = alt_config;
2555 }
2556}
2557
2558static void intel_pebs_aliases_ivb(struct perf_event *event)
2559{
2560 if (event->attr.precise_ip < 3)
2561 return intel_pebs_aliases_snb(event);
2562 return intel_pebs_aliases_precdist(event);
2563}
2564
2565static void intel_pebs_aliases_skl(struct perf_event *event)
2566{
2567 if (event->attr.precise_ip < 3)
2568 return intel_pebs_aliases_core2(event);
2569 return intel_pebs_aliases_precdist(event);
2570}
2571
a7b58d21
AK		 2572static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
2573{
2574 unsigned long flags = x86_pmu.free_running_flags;
2575
2576 if (event->attr.use_clockid)
2577 flags &= ~PERF_SAMPLE_TIME;
2578 return flags;
2579}
2580
0780c927
PZ		 2581static int intel_pmu_hw_config(struct perf_event *event)
2582{
2583 int ret = x86_pmu_hw_config(event);
2584
2585 if (ret)
2586 return ret;
2587
851559e3 2588 if (event->attr.precise_ip) {
3569c0d7 2589 if (!event->attr.freq) {
851559e3 2590 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
a7b58d21
AK		 2591 if (!(event->attr.sample_type &
2592 ~intel_pmu_free_running_flags(event)))
3569c0d7
YZ		 2593 event->hw.flags |= PERF_X86_EVENT_FREERUNNING;
2594 }
851559e3
YZ		 2595 if (x86_pmu.pebs_aliases)
2596 x86_pmu.pebs_aliases(event);
2597 }
7639dae0 2598
a46a2300 2599 if (needs_branch_stack(event)) {
60ce0fbd
SE		 2600 ret = intel_pmu_setup_lbr_filter(event);
2601 if (ret)
2602 return ret;
48070342
AS		 2603
2604 /*
2605 * BTS is set up earlier in this path, so don't account twice
2606 */
2607 if (!intel_pmu_has_bts(event)) {
2608 /* disallow lbr if conflicting events are present */
2609 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
2610 return -EBUSY;
2611
2612 event->destroy = hw_perf_lbr_event_destroy;
2613 }
60ce0fbd
SE		 2614 }
2615
b4cdc5c2
PZ		 2616 if (event->attr.type != PERF_TYPE_RAW)
2617 return 0;
2618
2619 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
2620 return 0;
2621
2622 if (x86_pmu.version < 3)
2623 return -EINVAL;
2624
2625 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
2626 return -EACCES;
2627
2628 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
2629
2630 return 0;
2631}
2632
144d31e6
GN		 2633struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
2634{
2635 if (x86_pmu.guest_get_msrs)
2636 return x86_pmu.guest_get_msrs(nr);
2637 *nr = 0;
2638 return NULL;
2639}
2640EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
2641
2642static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
2643{
89cbc767 2644 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2645 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2646
2647 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
2648 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
2649 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 2650 /*
2651 * If PMU counter has PEBS enabled it is not enough to disable counter
2652 * on a guest entry since PEBS memory write can overshoot guest entry
2653 * and corrupt guest memory. Disabling PEBS solves the problem.
2654 */
2655 arr[1].msr = MSR_IA32_PEBS_ENABLE;
2656 arr[1].host = cpuc->pebs_enabled;
2657 arr[1].guest = 0;
144d31e6 2658
26a4f3c0 2659 *nr = 2;
144d31e6
GN		 2660 return arr;
2661}
2662
2663static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2664{
89cbc767 2665 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2666 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2667 int idx;
2668
2669 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2670 struct perf_event *event = cpuc->events[idx];
2671
2672 arr[idx].msr = x86_pmu_config_addr(idx);
2673 arr[idx].host = arr[idx].guest = 0;
2674
2675 if (!test_bit(idx, cpuc->active_mask))
2676 continue;
2677
2678 arr[idx].host = arr[idx].guest =
2679 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2680
2681 if (event->attr.exclude_host)
2682 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2683 else if (event->attr.exclude_guest)
2684 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2685 }
2686
2687 *nr = x86_pmu.num_counters;
2688 return arr;
2689}
2690
2691static void core_pmu_enable_event(struct perf_event *event)
2692{
2693 if (!event->attr.exclude_host)
2694 x86_pmu_enable_event(event);
2695}
2696
2697static void core_pmu_enable_all(int added)
2698{
89cbc767 2699 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2700 int idx;
2701
2702 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2703 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2704
2705 if (!test_bit(idx, cpuc->active_mask) ||
2706 cpuc->events[idx]->attr.exclude_host)
2707 continue;
2708
2709 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2710 }
2711}
2712
3a632cb2
AK		 2713static int hsw_hw_config(struct perf_event *event)
2714{
2715 int ret = intel_pmu_hw_config(event);
2716
2717 if (ret)
2718 return ret;
2719 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2720 return 0;
2721 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2722
2723 /*
2724 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2725 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2726 * this combination.
2727 */
2728 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2729 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2730 event->attr.precise_ip > 0))
2731 return -EOPNOTSUPP;
2732
2dbf0116
AK		 2733 if (event_is_checkpointed(event)) {
2734 /*
2735 * Sampling of checkpointed events can cause situations where
2736 * the CPU constantly aborts because of a overflow, which is
2737 * then checkpointed back and ignored. Forbid checkpointing
2738 * for sampling.
2739 *
2740 * But still allow a long sampling period, so that perf stat
2741 * from KVM works.
2742 */
2743 if (event->attr.sample_period > 0 &&
2744 event->attr.sample_period < 0x7fffffff)
2745 return -EOPNOTSUPP;
2746 }
3a632cb2
AK		 2747 return 0;
2748}
2749
2750static struct event_constraint counter2_constraint =
2751 EVENT_CONSTRAINT(0, 0x4, 0);
2752
2753static struct event_constraint *
79cba822
SE		 2754hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2755 struct perf_event *event)
3a632cb2 2756{
79cba822
SE		 2757 struct event_constraint *c;
2758
2759 c = intel_get_event_constraints(cpuc, idx, event);
3a632cb2
AK		 2760
2761 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2762 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2763 if (c->idxmsk64 & (1U << 2))
2764 return &counter2_constraint;
2765 return &emptyconstraint;
2766 }
2767
2768 return c;
2769}
2770
294fe0f5
AK		 2771/*
2772 * Broadwell:
2773 *
2774 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
2775 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
2776 * the two to enforce a minimum period of 128 (the smallest value that has bits
2777 * 0-5 cleared and >= 100).
2778 *
2779 * Because of how the code in x86_perf_event_set_period() works, the truncation
2780 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
2781 * to make up for the 'lost' events due to carrying the 'error' in period_left.
2782 *
2783 * Therefore the effective (average) period matches the requested period,
2784 * despite coarser hardware granularity.
2785 */
2786static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
2787{
2788 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
2789 X86_CONFIG(.event=0xc0, .umask=0x01)) {
2790 if (left < 128)
2791 left = 128;
2792 left &= ~0x3fu;
2793 }
2794 return left;
2795}
2796
641cc938
JO		 2797PMU_FORMAT_ATTR(event, "config:0-7" );
2798PMU_FORMAT_ATTR(umask, "config:8-15" );
2799PMU_FORMAT_ATTR(edge, "config:18" );
2800PMU_FORMAT_ATTR(pc, "config:19" );
2801PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
2802PMU_FORMAT_ATTR(inv, "config:23" );
2803PMU_FORMAT_ATTR(cmask, "config:24-31" );
3a632cb2
AK		 2804PMU_FORMAT_ATTR(in_tx, "config:32");
2805PMU_FORMAT_ATTR(in_tx_cp, "config:33");
641cc938
JO		 2806
2807static struct attribute *intel_arch_formats_attr[] = {
2808 &format_attr_event.attr,
2809 &format_attr_umask.attr,
2810 &format_attr_edge.attr,
2811 &format_attr_pc.attr,
2812 &format_attr_inv.attr,
2813 &format_attr_cmask.attr,
2814 NULL,
2815};
2816
0bf79d44
JO		 2817ssize_t intel_event_sysfs_show(char *page, u64 config)
2818{
2819 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
2820
2821 return x86_event_sysfs_show(page, config, event);
2822}
2823
de0428a7 2824struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 2825{
2826 struct intel_shared_regs *regs;
2827 int i;
2828
2829 regs = kzalloc_node(sizeof(struct intel_shared_regs),
2830 GFP_KERNEL, cpu_to_node(cpu));
2831 if (regs) {
2832 /*
2833 * initialize the locks to keep lockdep happy
2834 */
2835 for (i = 0; i < EXTRA_REG_MAX; i++)
2836 raw_spin_lock_init(&regs->regs[i].lock);
2837
2838 regs->core_id = -1;
2839 }
2840 return regs;
2841}
2842
6f6539ca
MD		 2843static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
2844{
2845 struct intel_excl_cntrs *c;
6f6539ca
MD		 2846
2847 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
2848 GFP_KERNEL, cpu_to_node(cpu));
2849 if (c) {
2850 raw_spin_lock_init(&c->lock);
6f6539ca
MD		 2851 c->core_id = -1;
2852 }
2853 return c;
2854}
2855
a7e3ed1e
AK		 2856static int intel_pmu_cpu_prepare(int cpu)
2857{
2858 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2859
6f6539ca
MD		 2860 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
2861 cpuc->shared_regs = allocate_shared_regs(cpu);
2862 if (!cpuc->shared_regs)
dbc72b7a 2863 goto err;
6f6539ca 2864 }
69092624 2865
6f6539ca
MD		 2866 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2867 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
2868
2869 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
2870 if (!cpuc->constraint_list)
dbc72b7a 2871 goto err_shared_regs;
6f6539ca
MD		 2872
2873 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
dbc72b7a
PZ		 2874 if (!cpuc->excl_cntrs)
2875 goto err_constraint_list;
2876
6f6539ca
MD		 2877 cpuc->excl_thread_id = 0;
2878 }
a7e3ed1e 2879
a7e3ed1e 2880 return NOTIFY_OK;
dbc72b7a
PZ		 2881
2882err_constraint_list:
2883 kfree(cpuc->constraint_list);
2884 cpuc->constraint_list = NULL;
2885
2886err_shared_regs:
2887 kfree(cpuc->shared_regs);
2888 cpuc->shared_regs = NULL;
2889
2890err:
2891 return NOTIFY_BAD;
a7e3ed1e
AK		 2892}
2893
74846d35
PZ		 2894static void intel_pmu_cpu_starting(int cpu)
2895{
a7e3ed1e
AK		 2896 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2897 int core_id = topology_core_id(cpu);
2898 int i;
2899
69092624
LM		 2900 init_debug_store_on_cpu(cpu);
2901 /*
2902 * Deal with CPUs that don't clear their LBRs on power-up.
2903 */
2904 intel_pmu_lbr_reset();
2905
b36817e8
SE		 2906 cpuc->lbr_sel = NULL;
2907
2908 if (!cpuc->shared_regs)
69092624
LM		 2909 return;
2910
9a5e3fb5 2911 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
06931e62 2912 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
b36817e8 2913 struct intel_shared_regs *pc;
a7e3ed1e 2914
b36817e8
SE		 2915 pc = per_cpu(cpu_hw_events, i).shared_regs;
2916 if (pc && pc->core_id == core_id) {
8f04b853 2917 cpuc->kfree_on_online[0] = cpuc->shared_regs;
b36817e8
SE		 2918 cpuc->shared_regs = pc;
2919 break;
2920 }
a7e3ed1e 2921 }
b36817e8
SE		 2922 cpuc->shared_regs->core_id = core_id;
2923 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 2924 }
2925
b36817e8
SE		 2926 if (x86_pmu.lbr_sel_map)
2927 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
6f6539ca
MD		 2928
2929 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
06931e62 2930 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
6f6539ca
MD		 2931 struct intel_excl_cntrs *c;
2932
2933 c = per_cpu(cpu_hw_events, i).excl_cntrs;
2934 if (c && c->core_id == core_id) {
2935 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
2936 cpuc->excl_cntrs = c;
2937 cpuc->excl_thread_id = 1;
2938 break;
2939 }
2940 }
2941 cpuc->excl_cntrs->core_id = core_id;
2942 cpuc->excl_cntrs->refcnt++;
2943 }
74846d35
PZ		 2944}
2945
b37609c3 2946static void free_excl_cntrs(int cpu)
74846d35 2947{
a7e3ed1e 2948 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6f6539ca 2949 struct intel_excl_cntrs *c;
a7e3ed1e 2950
6f6539ca
MD		 2951 c = cpuc->excl_cntrs;
2952 if (c) {
2953 if (c->core_id == -1 || --c->refcnt == 0)
2954 kfree(c);
2955 cpuc->excl_cntrs = NULL;
2956 kfree(cpuc->constraint_list);
2957 cpuc->constraint_list = NULL;
2958 }
b37609c3 2959}
a7e3ed1e 2960
b37609c3
SE		 2961static void intel_pmu_cpu_dying(int cpu)
2962{
2963 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2964 struct intel_shared_regs *pc;
2965
2966 pc = cpuc->shared_regs;
2967 if (pc) {
2968 if (pc->core_id == -1 || --pc->refcnt == 0)
2969 kfree(pc);
2970 cpuc->shared_regs = NULL;
e979121b
MD		 2971 }
2972
b37609c3
SE		 2973 free_excl_cntrs(cpu);
2974
74846d35
PZ		 2975 fini_debug_store_on_cpu(cpu);
2976}
2977
9c964efa
YZ		 2978static void intel_pmu_sched_task(struct perf_event_context *ctx,
2979 bool sched_in)
2980{
2981 if (x86_pmu.pebs_active)
2982 intel_pmu_pebs_sched_task(ctx, sched_in);
2983 if (x86_pmu.lbr_nr)
2984 intel_pmu_lbr_sched_task(ctx, sched_in);
2985}
2986
641cc938
JO		 2987PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2988
a63fcab4
SE		 2989PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2990
d0dc8494
AK		 2991PMU_FORMAT_ATTR(frontend, "config1:0-23");
2992
641cc938
JO		 2993static struct attribute *intel_arch3_formats_attr[] = {
2994 &format_attr_event.attr,
2995 &format_attr_umask.attr,
2996 &format_attr_edge.attr,
2997 &format_attr_pc.attr,
2998 &format_attr_any.attr,
2999 &format_attr_inv.attr,
3000 &format_attr_cmask.attr,
3a632cb2
AK		 3001 &format_attr_in_tx.attr,
3002 &format_attr_in_tx_cp.attr,
641cc938
JO		 3003
3004 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
a63fcab4 3005 &format_attr_ldlat.attr, /* PEBS load latency */
641cc938
JO		 3006 NULL,
3007};
3008
d0dc8494
AK		 3009static struct attribute *skl_format_attr[] = {
3010 &format_attr_frontend.attr,
3011 NULL,
3012};
3013
3b6e0421
JO		 3014static __initconst const struct x86_pmu core_pmu = {
3015 .name = "core",
3016 .handle_irq = x86_pmu_handle_irq,
3017 .disable_all = x86_pmu_disable_all,
3018 .enable_all = core_pmu_enable_all,
3019 .enable = core_pmu_enable_event,
3020 .disable = x86_pmu_disable_event,
3021 .hw_config = x86_pmu_hw_config,
3022 .schedule_events = x86_schedule_events,
3023 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3024 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3025 .event_map = intel_pmu_event_map,
3026 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3027 .apic = 1,
a7b58d21
AK		 3028 .free_running_flags = PEBS_FREERUNNING_FLAGS,
3029
3b6e0421
JO		 3030 /*
3031 * Intel PMCs cannot be accessed sanely above 32-bit width,
3032 * so we install an artificial 1<<31 period regardless of
3033 * the generic event period:
3034 */
3035 .max_period = (1ULL<<31) - 1,
3036 .get_event_constraints = intel_get_event_constraints,
3037 .put_event_constraints = intel_put_event_constraints,
3038 .event_constraints = intel_core_event_constraints,
3039 .guest_get_msrs = core_guest_get_msrs,
3040 .format_attrs = intel_arch_formats_attr,
3041 .events_sysfs_show = intel_event_sysfs_show,
3042
3043 /*
3044 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
3045 * together with PMU version 1 and thus be using core_pmu with
3046 * shared_regs. We need following callbacks here to allocate
3047 * it properly.
3048 */
3049 .cpu_prepare = intel_pmu_cpu_prepare,
3050 .cpu_starting = intel_pmu_cpu_starting,
3051 .cpu_dying = intel_pmu_cpu_dying,
3052};
3053
caaa8be3 3054static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 3055 .name = "Intel",
3056 .handle_irq = intel_pmu_handle_irq,
3057 .disable_all = intel_pmu_disable_all,
3058 .enable_all = intel_pmu_enable_all,
3059 .enable = intel_pmu_enable_event,
3060 .disable = intel_pmu_disable_event,
b4cdc5c2 3061 .hw_config = intel_pmu_hw_config,
a072738e 3062 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 3063 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3064 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3065 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 3066 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3067 .apic = 1,
a7b58d21 3068 .free_running_flags = PEBS_FREERUNNING_FLAGS,
f22f54f4
PZ		 3069 /*
3070 * Intel PMCs cannot be accessed sanely above 32 bit width,
3071 * so we install an artificial 1<<31 period regardless of
3072 * the generic event period:
3073 */
3074 .max_period = (1ULL << 31) - 1,
3f6da390 3075 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 3076 .put_event_constraints = intel_put_event_constraints,
0780c927 3077 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 3078
641cc938 3079 .format_attrs = intel_arch3_formats_attr,
0bf79d44 3080 .events_sysfs_show = intel_event_sysfs_show,
641cc938 3081
a7e3ed1e 3082 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 3083 .cpu_starting = intel_pmu_cpu_starting,
3084 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 3085 .guest_get_msrs = intel_guest_get_msrs,
9c964efa 3086 .sched_task = intel_pmu_sched_task,
f22f54f4
PZ		 3087};
3088
c1d6f42f 3089static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 3090{
3091 /*
3092 * PEBS is unreliable due to:
3093 *
3094 * AJ67 - PEBS may experience CPL leaks
3095 * AJ68 - PEBS PMI may be delayed by one event
3096 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
3097 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
3098 *
3099 * AJ67 could be worked around by restricting the OS/USR flags.
3100 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
3101 *
3102 * AJ106 could possibly be worked around by not allowing LBR
3103 * usage from PEBS, including the fixup.
3104 * AJ68 could possibly be worked around by always programming
ec75a716 3105 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 3106 *
3107 * But taken together it might just make sense to not enable PEBS on
3108 * these chips.
3109 */
c767a54b 3110 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 3111 x86_pmu.pebs = 0;
3112 x86_pmu.pebs_constraints = NULL;
3113}
3114
c93dc84c
PZ		 3115static int intel_snb_pebs_broken(int cpu)
3116{
3117 u32 rev = UINT_MAX; /* default to broken for unknown models */
3118
3119 switch (cpu_data(cpu).x86_model) {
3120 case 42: /* SNB */
3121 rev = 0x28;
3122 break;
3123
3124 case 45: /* SNB-EP */
3125 switch (cpu_data(cpu).x86_mask) {
3126 case 6: rev = 0x618; break;
3127 case 7: rev = 0x70c; break;
3128 }
3129 }
3130
3131 return (cpu_data(cpu).microcode < rev);
3132}
3133
3134static void intel_snb_check_microcode(void)
3135{
3136 int pebs_broken = 0;
3137 int cpu;
3138
3139 get_online_cpus();
3140 for_each_online_cpu(cpu) {
3141 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
3142 break;
3143 }
3144 put_online_cpus();
3145
3146 if (pebs_broken == x86_pmu.pebs_broken)
3147 return;
3148
3149 /*
3150 * Serialized by the microcode lock..
3151 */
3152 if (x86_pmu.pebs_broken) {
3153 pr_info("PEBS enabled due to microcode update\n");
3154 x86_pmu.pebs_broken = 0;
3155 } else {
3156 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
3157 x86_pmu.pebs_broken = 1;
3158 }
3159}
3160
338b522c
KL		 3161/*
3162 * Under certain circumstances, access certain MSR may cause #GP.
3163 * The function tests if the input MSR can be safely accessed.
3164 */
3165static bool check_msr(unsigned long msr, u64 mask)
3166{
3167 u64 val_old, val_new, val_tmp;
3168
3169 /*
3170 * Read the current value, change it and read it back to see if it
3171 * matches, this is needed to detect certain hardware emulators
3172 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
3173 */
3174 if (rdmsrl_safe(msr, &val_old))
3175 return false;
3176
3177 /*
3178 * Only change the bits which can be updated by wrmsrl.
3179 */
3180 val_tmp = val_old ^ mask;
3181 if (wrmsrl_safe(msr, val_tmp) ||
3182 rdmsrl_safe(msr, &val_new))
3183 return false;
3184
3185 if (val_new != val_tmp)
3186 return false;
3187
3188 /* Here it's sure that the MSR can be safely accessed.
3189 * Restore the old value and return.
3190 */
3191 wrmsrl(msr, val_old);
3192
3193 return true;
3194}
3195
c1d6f42f 3196static __init void intel_sandybridge_quirk(void)
6a600a8b 3197{
c93dc84c
PZ		 3198 x86_pmu.check_microcode = intel_snb_check_microcode;
3199 intel_snb_check_microcode();
6a600a8b
PZ		 3200}
3201
c1d6f42f
PZ		 3202static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
3203 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
3204 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
3205 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
3206 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
3207 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
3208 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
3209 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 3210};
3211
c1d6f42f
PZ		 3212static __init void intel_arch_events_quirk(void)
3213{
3214 int bit;
3215
3216 /* disable event that reported as not presend by cpuid */
3217 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
3218 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 3219 pr_warn("CPUID marked event: \'%s\' unavailable\n",
3220 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 3221 }
3222}
3223
3224static __init void intel_nehalem_quirk(void)
3225{
3226 union cpuid10_ebx ebx;
3227
3228 ebx.full = x86_pmu.events_maskl;
3229 if (ebx.split.no_branch_misses_retired) {
3230 /*
3231 * Erratum AAJ80 detected, we work it around by using
3232 * the BR_MISP_EXEC.ANY event. This will over-count
3233 * branch-misses, but it's still much better than the
3234 * architectural event which is often completely bogus:
3235 */
3236 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
3237 ebx.split.no_branch_misses_retired = 0;
3238 x86_pmu.events_maskl = ebx.full;
c767a54b 3239 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 3240 }
3241}
3242
93fcf72c
MD		 3243/*
3244 * enable software workaround for errata:
3245 * SNB: BJ122
3246 * IVB: BV98
3247 * HSW: HSD29
3248 *
3249 * Only needed when HT is enabled. However detecting
b37609c3
SE		 3250 * if HT is enabled is difficult (model specific). So instead,
3251 * we enable the workaround in the early boot, and verify if
3252 * it is needed in a later initcall phase once we have valid
3253 * topology information to check if HT is actually enabled
93fcf72c
MD		 3254 */
3255static __init void intel_ht_bug(void)
3256{
b37609c3 3257 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
93fcf72c 3258
93fcf72c 3259 x86_pmu.start_scheduling = intel_start_scheduling;
0c41e756 3260 x86_pmu.commit_scheduling = intel_commit_scheduling;
93fcf72c 3261 x86_pmu.stop_scheduling = intel_stop_scheduling;
93fcf72c
MD		 3262}
3263
7f2ee91f
IM		 3264EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
3265EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
f9134f36 3266
4b2c4f1f 3267/* Haswell special events */
7f2ee91f
IM		 3268EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
3269EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
3270EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
3271EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
3272EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
3273EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
3274EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
3275EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
3276EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
3277EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
3278EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
3279EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4b2c4f1f 3280
f9134f36 3281static struct attribute *hsw_events_attrs[] = {
4b2c4f1f
AK		 3282 EVENT_PTR(tx_start),
3283 EVENT_PTR(tx_commit),
3284 EVENT_PTR(tx_abort),
3285 EVENT_PTR(tx_capacity),
3286 EVENT_PTR(tx_conflict),
3287 EVENT_PTR(el_start),
3288 EVENT_PTR(el_commit),
3289 EVENT_PTR(el_abort),
3290 EVENT_PTR(el_capacity),
3291 EVENT_PTR(el_conflict),
3292 EVENT_PTR(cycles_t),
3293 EVENT_PTR(cycles_ct),
f9134f36
AK		 3294 EVENT_PTR(mem_ld_hsw),
3295 EVENT_PTR(mem_st_hsw),
3296 NULL
3297};
3298
de0428a7 3299__init int intel_pmu_init(void)
f22f54f4
PZ		 3300{
3301 union cpuid10_edx edx;
3302 union cpuid10_eax eax;
ffb871bc 3303 union cpuid10_ebx ebx;
a1eac7ac 3304 struct event_constraint *c;
f22f54f4 3305 unsigned int unused;
338b522c
KL		 3306 struct extra_reg *er;
3307 int version, i;
f22f54f4
PZ		 3308
3309 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 3310 switch (boot_cpu_data.x86) {
3311 case 0x6:
3312 return p6_pmu_init();
e717bf4e
VW		 3313 case 0xb:
3314 return knc_pmu_init();
a072738e
CG		 3315 case 0xf:
3316 return p4_pmu_init();
3317 }
f22f54f4 3318 return -ENODEV;
f22f54f4
PZ		 3319 }
3320
3321 /*
3322 * Check whether the Architectural PerfMon supports
3323 * Branch Misses Retired hw_event or not.
3324 */
ffb871bc
GN		 3325 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
3326 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 3327 return -ENODEV;
3328
3329 version = eax.split.version_id;
3330 if (version < 2)
3331 x86_pmu = core_pmu;
3332 else
3333 x86_pmu = intel_pmu;
3334
3335 x86_pmu.version = version;
948b1bb8
RR		 3336 x86_pmu.num_counters = eax.split.num_counters;
3337 x86_pmu.cntval_bits = eax.split.bit_width;
3338 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 3339
c1d6f42f
PZ		 3340 x86_pmu.events_maskl = ebx.full;
3341 x86_pmu.events_mask_len = eax.split.mask_length;
3342
70ab7003
AK		 3343 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
3344
f22f54f4
PZ		 3345 /*
3346 * Quirk: v2 perfmon does not report fixed-purpose events, so
3347 * assume at least 3 events:
3348 */
3349 if (version > 1)
948b1bb8 3350 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 3351
c9b08884 3352 if (boot_cpu_has(X86_FEATURE_PDCM)) {
8db909a7
PZ		 3353 u64 capabilities;
3354
3355 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
3356 x86_pmu.intel_cap.capabilities = capabilities;
3357 }
3358
ca037701
PZ		 3359 intel_ds_init();
3360
c1d6f42f
PZ		 3361 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
3362
f22f54f4
PZ		 3363 /*
3364 * Install the hw-cache-events table:
3365 */
3366 switch (boot_cpu_data.x86_model) {
0f7c29ce 3367 case 14: /* 65nm Core "Yonah" */
f22f54f4
PZ		 3368 pr_cont("Core events, ");
3369 break;
3370
0f7c29ce 3371 case 15: /* 65nm Core2 "Merom" */
c1d6f42f 3372 x86_add_quirk(intel_clovertown_quirk);
0f7c29ce
PZ		 3373 case 22: /* 65nm Core2 "Merom-L" */
3374 case 23: /* 45nm Core2 "Penryn" */
3375 case 29: /* 45nm Core2 "Dunnington (MP) */
f22f54f4
PZ		 3376 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3377 sizeof(hw_cache_event_ids));
3378
caff2bef
PZ		 3379 intel_pmu_lbr_init_core();
3380
f22f54f4 3381 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 3382 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 3383 pr_cont("Core2 events, ");
3384 break;
3385
0f7c29ce
PZ		 3386 case 30: /* 45nm Nehalem */
3387 case 26: /* 45nm Nehalem-EP */
3388 case 46: /* 45nm Nehalem-EX */
f22f54f4
PZ		 3389 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3390 sizeof(hw_cache_event_ids));
e994d7d2
AK		 3391 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3392 sizeof(hw_cache_extra_regs));
f22f54f4 3393
caff2bef
PZ		 3394 intel_pmu_lbr_init_nhm();
3395
f22f54f4 3396 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 3397 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 3398 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 3399 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 3400
f20093ee
SE		 3401 x86_pmu.cpu_events = nhm_events_attrs;
3402
91fc4cc0 3403 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 3404 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3405 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 3406 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 3407 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3408 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 3409
c1d6f42f 3410 x86_add_quirk(intel_nehalem_quirk);
ec75a716 3411
11164cd4 3412 pr_cont("Nehalem events, ");
f22f54f4 3413 break;
caff2bef 3414
0f7c29ce
PZ		 3415 case 28: /* 45nm Atom "Pineview" */
3416 case 38: /* 45nm Atom "Lincroft" */
3417 case 39: /* 32nm Atom "Penwell" */
3418 case 53: /* 32nm Atom "Cloverview" */
3419 case 54: /* 32nm Atom "Cedarview" */
f22f54f4
PZ		 3420 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
3421 sizeof(hw_cache_event_ids));
3422
caff2bef
PZ		 3423 intel_pmu_lbr_init_atom();
3424
f22f54f4 3425 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 3426 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
673d188b 3427 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
f22f54f4
PZ		 3428 pr_cont("Atom events, ");
3429 break;
3430
0f7c29ce 3431 case 55: /* 22nm Atom "Silvermont" */
ef454cae 3432 case 76: /* 14nm Atom "Airmont" */
0f7c29ce 3433 case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
1fa64180
YZ		 3434 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
3435 sizeof(hw_cache_event_ids));
3436 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
3437 sizeof(hw_cache_extra_regs));
3438
3439 intel_pmu_lbr_init_atom();
3440
3441 x86_pmu.event_constraints = intel_slm_event_constraints;
3442 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3443 x86_pmu.extra_regs = intel_slm_extra_regs;
9a5e3fb5 3444 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
1fa64180
YZ		 3445 pr_cont("Silvermont events, ");
3446 break;
3447
0f7c29ce
PZ		 3448 case 37: /* 32nm Westmere */
3449 case 44: /* 32nm Westmere-EP */
3450 case 47: /* 32nm Westmere-EX */
f22f54f4
PZ		 3451 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
3452 sizeof(hw_cache_event_ids));
e994d7d2
AK		 3453 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3454 sizeof(hw_cache_extra_regs));
f22f54f4 3455
caff2bef
PZ		 3456 intel_pmu_lbr_init_nhm();
3457
f22f54f4 3458 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 3459 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 3460 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 3461 x86_pmu.extra_regs = intel_westmere_extra_regs;
9a5e3fb5 3462 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
30112039 3463
f20093ee
SE		 3464 x86_pmu.cpu_events = nhm_events_attrs;
3465
30112039 3466 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 3467 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3468 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 3469 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 3470 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3471 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 3472
f22f54f4
PZ		 3473 pr_cont("Westmere events, ");
3474 break;
b622d644 3475
0f7c29ce
PZ		 3476 case 42: /* 32nm SandyBridge */
3477 case 45: /* 32nm SandyBridge-E/EN/EP */
47a8863d 3478 x86_add_quirk(intel_sandybridge_quirk);
93fcf72c 3479 x86_add_quirk(intel_ht_bug);
b06b3d49
LM		 3480 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3481 sizeof(hw_cache_event_ids));
74e6543f
YZ		 3482 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3483 sizeof(hw_cache_extra_regs));
b06b3d49 3484
c5cc2cd9 3485 intel_pmu_lbr_init_snb();
b06b3d49
LM		 3486
3487 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 3488 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 3489 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 3490 if (boot_cpu_data.x86_model == 45)
3491 x86_pmu.extra_regs = intel_snbep_extra_regs;
3492 else
3493 x86_pmu.extra_regs = intel_snb_extra_regs;
93fcf72c
MD		 3494
3495
ee89cbc2 3496 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3497 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3498 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
e04d1b23 3499
f20093ee
SE		 3500 x86_pmu.cpu_events = snb_events_attrs;
3501
e04d1b23 3502 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 3503 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3504 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 3505 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 3506 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3507 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 3508
b06b3d49
LM		 3509 pr_cont("SandyBridge events, ");
3510 break;
0f7c29ce
PZ		 3511
3512 case 58: /* 22nm IvyBridge */
3513 case 62: /* 22nm IvyBridge-EP/EX */
93fcf72c 3514 x86_add_quirk(intel_ht_bug);
20a36e39
SE		 3515 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3516 sizeof(hw_cache_event_ids));
1996388e
VW		 3517 /* dTLB-load-misses on IVB is different than SNB */
3518 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3519
20a36e39
SE		 3520 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3521 sizeof(hw_cache_extra_regs));
3522
3523 intel_pmu_lbr_init_snb();
3524
69943182 3525 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39 3526 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
72469764
AK		 3527 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3528 x86_pmu.pebs_prec_dist = true;
f1923820
SE		 3529 if (boot_cpu_data.x86_model == 62)
3530 x86_pmu.extra_regs = intel_snbep_extra_regs;
3531 else
3532 x86_pmu.extra_regs = intel_snb_extra_regs;
20a36e39 3533 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3534 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3535 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
20a36e39 3536
f20093ee
SE		 3537 x86_pmu.cpu_events = snb_events_attrs;
3538
20a36e39
SE		 3539 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3540 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3541 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3542
3543 pr_cont("IvyBridge events, ");
3544 break;
3545
b06b3d49 3546
d86c8eaf
AK		 3547 case 60: /* 22nm Haswell Core */
3548 case 63: /* 22nm Haswell Server */
3549 case 69: /* 22nm Haswell ULT */
3550 case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
93fcf72c 3551 x86_add_quirk(intel_ht_bug);
72db5596 3552 x86_pmu.late_ack = true;
0f1b5ca2
AK		 3553 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3554 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3a632cb2 3555
e9d7f7cd 3556 intel_pmu_lbr_init_hsw();
3a632cb2
AK		 3557
3558 x86_pmu.event_constraints = intel_hsw_event_constraints;
3044318f 3559 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
36bbb2f2 3560 x86_pmu.extra_regs = intel_snbep_extra_regs;
72469764
AK		 3561 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3562 x86_pmu.pebs_prec_dist = true;
3a632cb2 3563 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3564 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3565 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3a632cb2
AK		 3566
3567 x86_pmu.hw_config = hsw_hw_config;
3568 x86_pmu.get_event_constraints = hsw_get_event_constraints;
f9134f36 3569 x86_pmu.cpu_events = hsw_events_attrs;
b7af41a1 3570 x86_pmu.lbr_double_abort = true;
3a632cb2
AK		 3571 pr_cont("Haswell events, ");
3572 break;
3573
91f1b705
AK		 3574 case 61: /* 14nm Broadwell Core-M */
3575 case 86: /* 14nm Broadwell Xeon D */
4b36f1a4
AK		 3576 case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
3577 case 79: /* 14nm Broadwell Server */
91f1b705
AK		 3578 x86_pmu.late_ack = true;
3579 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3580 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3581
3582 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3583 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
3584 BDW_L3_MISS|HSW_SNOOP_DRAM;
3585 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
3586 HSW_SNOOP_DRAM;
3587 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
3588 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3589 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
3590 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3591
78d504bc 3592 intel_pmu_lbr_init_hsw();
91f1b705
AK		 3593
3594 x86_pmu.event_constraints = intel_bdw_event_constraints;
3595 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3596 x86_pmu.extra_regs = intel_snbep_extra_regs;
72469764
AK		 3597 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3598 x86_pmu.pebs_prec_dist = true;
91f1b705 3599 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3600 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3601 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
91f1b705
AK		 3602
3603 x86_pmu.hw_config = hsw_hw_config;
3604 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3605 x86_pmu.cpu_events = hsw_events_attrs;
294fe0f5 3606 x86_pmu.limit_period = bdw_limit_period;
91f1b705
AK		 3607 pr_cont("Broadwell events, ");
3608 break;
3609
1e7b9390
HC		 3610 case 87: /* Knights Landing Xeon Phi */
3611 memcpy(hw_cache_event_ids,
3612 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3613 memcpy(hw_cache_extra_regs,
3614 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3615 intel_pmu_lbr_init_knl();
3616
3617 x86_pmu.event_constraints = intel_slm_event_constraints;
3618 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3619 x86_pmu.extra_regs = intel_knl_extra_regs;
3620
3621 /* all extra regs are per-cpu when HT is on */
3622 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3623 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3624
3625 pr_cont("Knights Landing events, ");
3626 break;
3627
9a92e16f
AK		 3628 case 78: /* 14nm Skylake Mobile */
3629 case 94: /* 14nm Skylake Desktop */
3630 x86_pmu.late_ack = true;
3631 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3632 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3633 intel_pmu_lbr_init_skl();
3634
3635 x86_pmu.event_constraints = intel_skl_event_constraints;
3636 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
3637 x86_pmu.extra_regs = intel_skl_extra_regs;
72469764
AK		 3638 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
3639 x86_pmu.pebs_prec_dist = true;
9a92e16f
AK		 3640 /* all extra regs are per-cpu when HT is on */
3641 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3642 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3643
3644 x86_pmu.hw_config = hsw_hw_config;
3645 x86_pmu.get_event_constraints = hsw_get_event_constraints;
d0dc8494
AK		 3646 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
3647 skl_format_attr);
9a92e16f
AK		 3648 WARN_ON(!x86_pmu.format_attrs);
3649 x86_pmu.cpu_events = hsw_events_attrs;
3650 pr_cont("Skylake events, ");
3651 break;
3652
f22f54f4 3653 default:
0af3ac1f
AK		 3654 switch (x86_pmu.version) {
3655 case 1:
3656 x86_pmu.event_constraints = intel_v1_event_constraints;
3657 pr_cont("generic architected perfmon v1, ");
3658 break;
3659 default:
3660 /*
3661 * default constraints for v2 and up
3662 */
3663 x86_pmu.event_constraints = intel_gen_event_constraints;
3664 pr_cont("generic architected perfmon, ");
3665 break;
3666 }
f22f54f4 3667 }
ffb871bc 3668
a1eac7ac
RR		 3669 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
3670 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
3671 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
3672 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
3673 }
3674 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
3675
3676 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
3677 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
3678 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
3679 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
3680 }
3681
3682 x86_pmu.intel_ctrl |=
3683 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
3684
3685 if (x86_pmu.event_constraints) {
3686 /*
3687 * event on fixed counter2 (REF_CYCLES) only works on this
3688 * counter, so do not extend mask to generic counters
3689 */
3690 for_each_event_constraint(c, x86_pmu.event_constraints) {
2c33645d
PI		 3691 if (c->cmask == FIXED_EVENT_FLAGS
3692 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
3693 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
a1eac7ac 3694 }
2c33645d
PI		 3695 c->idxmsk64 &=
3696 ~(~0UL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
3697 c->weight = hweight64(c->idxmsk64);
a1eac7ac
RR		 3698 }
3699 }
3700
338b522c
KL		 3701 /*
3702 * Access LBR MSR may cause #GP under certain circumstances.
3703 * E.g. KVM doesn't support LBR MSR
3704 * Check all LBT MSR here.
3705 * Disable LBR access if any LBR MSRs can not be accessed.
3706 */
3707 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
3708 x86_pmu.lbr_nr = 0;
3709 for (i = 0; i < x86_pmu.lbr_nr; i++) {
3710 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
3711 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
3712 x86_pmu.lbr_nr = 0;
3713 }
3714
3715 /*
3716 * Access extra MSR may cause #GP under certain circumstances.
3717 * E.g. KVM doesn't support offcore event
3718 * Check all extra_regs here.
3719 */
3720 if (x86_pmu.extra_regs) {
3721 for (er = x86_pmu.extra_regs; er->msr; er++) {
8c4fe709 3722 er->extra_msr_access = check_msr(er->msr, 0x11UL);
338b522c
KL		 3723 /* Disable LBR select mapping */
3724 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
3725 x86_pmu.lbr_sel_map = NULL;
3726 }
3727 }
3728
069e0c3c
AK		 3729 /* Support full width counters using alternative MSR range */
3730 if (x86_pmu.intel_cap.full_width_write) {
3731 x86_pmu.max_period = x86_pmu.cntval_mask;
3732 x86_pmu.perfctr = MSR_IA32_PMC0;
3733 pr_cont("full-width counters, ");
3734 }
3735
f22f54f4
PZ		 3736 return 0;
3737}
b37609c3
SE		 3738
3739/*
3740 * HT bug: phase 2 init
3741 * Called once we have valid topology information to check
3742 * whether or not HT is enabled
3743 * If HT is off, then we disable the workaround
3744 */
3745static __init int fixup_ht_bug(void)
3746{
3747 int cpu = smp_processor_id();
3748 int w, c;
3749 /*
3750 * problem not present on this CPU model, nothing to do
3751 */
3752 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
3753 return 0;
3754
06931e62 3755 w = cpumask_weight(topology_sibling_cpumask(cpu));
b37609c3
SE		 3756 if (w > 1) {
3757 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
3758 return 0;
3759 }
3760
ec6a9066 3761 if (lockup_detector_suspend() != 0) {
999bbe49
UO		 3762 pr_debug("failed to disable PMU erratum BJ122, BV98, HSD29 workaround\n");
3763 return 0;
3764 }
b37609c3
SE		 3765
3766 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
3767
b37609c3 3768 x86_pmu.start_scheduling = NULL;
0c41e756 3769 x86_pmu.commit_scheduling = NULL;
b37609c3
SE		 3770 x86_pmu.stop_scheduling = NULL;
3771
ec6a9066 3772 lockup_detector_resume();
b37609c3
SE		 3773
3774 get_online_cpus();
3775
3776 for_each_online_cpu(c) {
3777 free_excl_cntrs(c);
3778 }
3779
3780 put_online_cpus();
3781 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
3782 return 0;
3783}
3784subsys_initcall(fixup_ht_bug)
Linux 6.x block layer and io_uring tree(s)