[linux-2.6-block.git] / arch / sparc64 / kernel / head.S

/* $Id: head.S,v 1.87 2002/02/09 19:49:31 davem Exp $
 * head.S: Initial boot code for the Sparc64 port of Linux.
 *
 * Copyright (C) 1996,1997 David S. Miller (davem@caip.rutgers.edu)
 * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
 */

#include <linux/config.h>
#include <linux/version.h>
#include <linux/errno.h>
#include <asm/thread_info.h>
#include <asm/asi.h>
#include <asm/pstate.h>
#include <asm/ptrace.h>
#include <asm/spitfire.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/errno.h>
#include <asm/signal.h>
#include <asm/processor.h>
#include <asm/lsu.h>
#include <asm/dcr.h>
#include <asm/dcu.h>
#include <asm/head.h>
#include <asm/ttable.h>
#include <asm/mmu.h>
#include <asm/cpudata.h>
	
/* This section from from _start to sparc64_boot_end should fit into
 * 0x0000000000404000 to 0x0000000000408000.
 */
	.text
	.globl	start, _start, stext, _stext
_start:
start:
_stext:
stext:
! 0x0000000000404000
	b	sparc64_boot
	 flushw					/* Flush register file.      */

/* This stuff has to be in sync with SILO and other potential boot loaders
 * Fields should be kept upward compatible and whenever any change is made,
 * HdrS version should be incremented.
 */
        .global root_flags, ram_flags, root_dev
        .global sparc_ramdisk_image, sparc_ramdisk_size
	.global sparc_ramdisk_image64

        .ascii  "HdrS"
        .word   LINUX_VERSION_CODE

	/* History:
	 *
	 * 0x0300 : Supports being located at other than 0x4000
	 * 0x0202 : Supports kernel params string
	 * 0x0201 : Supports reboot_command
	 */
	.half   0x0301          /* HdrS version */

root_flags:
        .half   1
root_dev:
        .half   0
ram_flags:
        .half   0
sparc_ramdisk_image:
        .word   0
sparc_ramdisk_size:
        .word   0
        .xword  reboot_command
	.xword	bootstr_info
sparc_ramdisk_image64:
	.xword	0
	.word	_end

	/* PROM cif handler code address is in %o4.  */
sparc64_boot:
1:	rd	%pc, %g7
	set	1b, %g1
	cmp	%g1, %g7
	be,pn	%xcc, sparc64_boot_after_remap
	 mov	%o4, %l7

	/* We need to remap the kernel.  Use position independant
	 * code to remap us to KERNBASE.
	 *
	 * SILO can invoke us with 32-bit address masking enabled,
	 * so make sure that's clear.
	 */
	rdpr	%pstate, %g1
	andn	%g1, PSTATE_AM, %g1
	wrpr	%g1, 0x0, %pstate
	ba,a,pt	%xcc, 1f

	.globl	prom_finddev_name, prom_chosen_path
	.globl	prom_getprop_name, prom_mmu_name
	.globl	prom_callmethod_name, prom_translate_name
	.globl	prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
	.globl	prom_boot_mapped_pc, prom_boot_mapping_mode
	.globl	prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
prom_finddev_name:
	.asciz	"finddevice"
prom_chosen_path:
	.asciz	"/chosen"
prom_getprop_name:
	.asciz	"getprop"
prom_mmu_name:
	.asciz	"mmu"
prom_callmethod_name:
	.asciz	"call-method"
prom_translate_name:
	.asciz	"translate"
prom_map_name:
	.asciz	"map"
prom_unmap_name:
	.asciz	"unmap"
	.align	4
prom_mmu_ihandle_cache:
	.word	0
prom_boot_mapped_pc:
	.word	0
prom_boot_mapping_mode:
	.word	0
	.align	8
prom_boot_mapping_phys_high:
	.xword	0
prom_boot_mapping_phys_low:
	.xword	0
1:
	rd	%pc, %l0
	mov	(1b - prom_finddev_name), %l1
	mov	(1b - prom_chosen_path), %l2
	mov	(1b - prom_boot_mapped_pc), %l3
	sub	%l0, %l1, %l1
	sub	%l0, %l2, %l2
	sub	%l0, %l3, %l3
	stw	%l0, [%l3]
	sub	%sp, (192 + 128), %sp

	/* chosen_node = prom_finddevice("/chosen") */
	stx	%l1, [%sp + 2047 + 128 + 0x00]	! service, "finddevice"
	mov	1, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x08]	! num_args, 1
	stx	%l3, [%sp + 2047 + 128 + 0x10]	! num_rets, 1
	stx	%l2, [%sp + 2047 + 128 + 0x18]	! arg1, "/chosen"
	stx	%g0, [%sp + 2047 + 128 + 0x20]	! ret1
	call	%l7
	 add	%sp, (2047 + 128), %o0		! argument array

	ldx	[%sp + 2047 + 128 + 0x20], %l4	! chosen device node

	mov	(1b - prom_getprop_name), %l1
	mov	(1b - prom_mmu_name), %l2
	mov	(1b - prom_mmu_ihandle_cache), %l5
	sub	%l0, %l1, %l1
	sub	%l0, %l2, %l2
	sub	%l0, %l5, %l5

	/* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
	stx	%l1, [%sp + 2047 + 128 + 0x00]	! service, "getprop"
	mov	4, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x08]	! num_args, 4
	mov	1, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x10]	! num_rets, 1
	stx	%l4, [%sp + 2047 + 128 + 0x18]	! arg1, chosen_node
	stx	%l2, [%sp + 2047 + 128 + 0x20]	! arg2, "mmu"
	stx	%l5, [%sp + 2047 + 128 + 0x28]	! arg3, &prom_mmu_ihandle_cache
	mov	4, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x30]	! arg4, sizeof(arg3)
	stx	%g0, [%sp + 2047 + 128 + 0x38]	! ret1
	call	%l7
	 add	%sp, (2047 + 128), %o0		! argument array

	mov	(1b - prom_callmethod_name), %l1
	mov	(1b - prom_translate_name), %l2
	sub	%l0, %l1, %l1
	sub	%l0, %l2, %l2
	lduw	[%l5], %l5			! prom_mmu_ihandle_cache

	stx	%l1, [%sp + 2047 + 128 + 0x00]	! service, "call-method"
	mov	3, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x08]	! num_args, 3
	mov	5, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x10]	! num_rets, 5
	stx	%l2, [%sp + 2047 + 128 + 0x18]	! arg1: "translate"
	stx	%l5, [%sp + 2047 + 128 + 0x20]	! arg2: prom_mmu_ihandle_cache
	/* PAGE align */
	srlx	%l0, 13, %l3
	sllx	%l3, 13, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x28]	! arg3: vaddr, our PC
	stx	%g0, [%sp + 2047 + 128 + 0x30]	! res1
	stx	%g0, [%sp + 2047 + 128 + 0x38]	! res2
	stx	%g0, [%sp + 2047 + 128 + 0x40]	! res3
	stx	%g0, [%sp + 2047 + 128 + 0x48]	! res4
	stx	%g0, [%sp + 2047 + 128 + 0x50]	! res5
	call	%l7
	 add	%sp, (2047 + 128), %o0		! argument array

	ldx	[%sp + 2047 + 128 + 0x40], %l1	! translation mode
	mov	(1b - prom_boot_mapping_mode), %l4
	sub	%l0, %l4, %l4
	stw	%l1, [%l4]
	mov	(1b - prom_boot_mapping_phys_high), %l4
	sub	%l0, %l4, %l4
	ldx	[%sp + 2047 + 128 + 0x48], %l2	! physaddr high
	stx	%l2, [%l4 + 0x0]
	ldx	[%sp + 2047 + 128 + 0x50], %l3	! physaddr low
	/* 4MB align */
	srlx	%l3, 22, %l3
	sllx	%l3, 22, %l3
	stx	%l3, [%l4 + 0x8]

	/* Leave service as-is, "call-method" */
	mov	7, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x08]	! num_args, 7
	mov	1, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x10]	! num_rets, 1
	mov	(1b - prom_map_name), %l3
	sub	%l0, %l3, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x18]	! arg1: "map"
	/* Leave arg2 as-is, prom_mmu_ihandle_cache */
	mov	-1, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x28]	! arg3: mode (-1 default)
	sethi	%hi(8 * 1024 * 1024), %l3
	stx	%l3, [%sp + 2047 + 128 + 0x30]	! arg4: size (8MB)
	sethi	%hi(KERNBASE), %l3
	stx	%l3, [%sp + 2047 + 128 + 0x38]	! arg5: vaddr (KERNBASE)
	stx	%g0, [%sp + 2047 + 128 + 0x40]	! arg6: empty
	mov	(1b - prom_boot_mapping_phys_low), %l3
	sub	%l0, %l3, %l3
	ldx	[%l3], %l3
	stx	%l3, [%sp + 2047 + 128 + 0x48]	! arg7: phys addr
	call	%l7
	 add	%sp, (2047 + 128), %o0		! argument array

	add	%sp, (192 + 128), %sp

sparc64_boot_after_remap:
	BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
	BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
	ba,pt	%xcc, spitfire_boot
	 nop

cheetah_plus_boot:
	/* Preserve OBP chosen DCU and DCR register settings.  */
	ba,pt	%xcc, cheetah_generic_boot
	 nop

cheetah_boot:
	mov	DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
	wr	%g1, %asr18

	sethi	%uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
	or	%g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
	sllx	%g7, 32, %g7
	or	%g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
	stxa	%g7, [%g0] ASI_DCU_CONTROL_REG
	membar	#Sync

cheetah_generic_boot:
	mov	TSB_EXTENSION_P, %g3
	stxa	%g0, [%g3] ASI_DMMU
	stxa	%g0, [%g3] ASI_IMMU
	membar	#Sync

	mov	TSB_EXTENSION_S, %g3
	stxa	%g0, [%g3] ASI_DMMU
	membar	#Sync

	mov	TSB_EXTENSION_N, %g3
	stxa	%g0, [%g3] ASI_DMMU
	stxa	%g0, [%g3] ASI_IMMU
	membar	#Sync

	ba,a,pt	%xcc, jump_to_sun4u_init

spitfire_boot:
	/* Typically PROM has already enabled both MMU's and both on-chip
	 * caches, but we do it here anyway just to be paranoid.
	 */
	mov	(LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
	stxa	%g1, [%g0] ASI_LSU_CONTROL
	membar	#Sync

jump_to_sun4u_init:
	/*
	 * Make sure we are in privileged mode, have address masking,
         * using the ordinary globals and have enabled floating
         * point.
	 *
	 * Again, typically PROM has left %pil at 13 or similar, and
	 * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
         */
	wrpr    %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
	wr	%g0, 0, %fprs

	set	sun4u_init, %g2
	jmpl    %g2 + %g0, %g0
	 nop

sun4u_init:
	/* Set ctx 0 */
	mov	PRIMARY_CONTEXT, %g7
	stxa	%g0, [%g7] ASI_DMMU
	membar	#Sync

	mov	SECONDARY_CONTEXT, %g7
	stxa	%g0, [%g7] ASI_DMMU
	membar	#Sync

	BRANCH_IF_ANY_CHEETAH(g1,g7,cheetah_tlb_fixup)

	ba,pt	%xcc, spitfire_tlb_fixup
	 nop

cheetah_tlb_fixup:
	mov	2, %g2		/* Set TLB type to cheetah+. */
	BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)

	mov	1, %g2		/* Set TLB type to cheetah. */

1:	sethi	%hi(tlb_type), %g1
	stw	%g2, [%g1 + %lo(tlb_type)]

	/* Patch copy/page operations to cheetah optimized versions. */
	call	cheetah_patch_copyops
	 nop
	call	cheetah_patch_copy_page
	 nop
	call	cheetah_patch_cachetlbops
	 nop

	ba,pt	%xcc, tlb_fixup_done
	 nop

spitfire_tlb_fixup:
	/* Set TLB type to spitfire. */
	mov	0, %g2
	sethi	%hi(tlb_type), %g1
	stw	%g2, [%g1 + %lo(tlb_type)]

tlb_fixup_done:
	sethi	%hi(init_thread_union), %g6
	or	%g6, %lo(init_thread_union), %g6
	ldx	[%g6 + TI_TASK], %g4
	mov	%sp, %l6
	mov	%o4, %l7

	wr	%g0, ASI_P, %asi
	mov	1, %g1
	sllx	%g1, THREAD_SHIFT, %g1
	sub	%g1, (STACKFRAME_SZ + STACK_BIAS), %g1
	add	%g6, %g1, %sp
	mov	0, %fp

	/* Set per-cpu pointer initially to zero, this makes
	 * the boot-cpu use the in-kernel-image per-cpu areas
	 * before setup_per_cpu_area() is invoked.
	 */
	clr	%g5

	wrpr	%g0, 0, %wstate
	wrpr	%g0, 0x0, %tl

	/* Clear the bss */
	sethi	%hi(__bss_start), %o0
	or	%o0, %lo(__bss_start), %o0
	sethi	%hi(_end), %o1
	or	%o1, %lo(_end), %o1
	call	__bzero
	 sub	%o1, %o0, %o1

	mov	%l6, %o1			! OpenPROM stack
	call	prom_init
	 mov	%l7, %o0			! OpenPROM cif handler

	/* Off we go.... */
	call	start_kernel
	 nop
	/* Not reached... */

	/* This is meant to allow the sharing of this code between
	 * boot processor invocation (via setup_tba() below) and
	 * secondary processor startup (via trampoline.S).  The
	 * former does use this code, the latter does not yet due
	 * to some complexities.  That should be fixed up at some
	 * point.
	 *
	 * There used to be enormous complexity wrt. transferring
	 * over from the firwmare's trap table to the Linux kernel's.
	 * For example, there was a chicken & egg problem wrt. building
	 * the OBP page tables, yet needing to be on the Linux kernel
	 * trap table (to translate PAGE_OFFSET addresses) in order to
	 * do that.
	 *
	 * We now handle OBP tlb misses differently, via linear lookups
	 * into the prom_trans[] array.  So that specific problem no
	 * longer exists.  Yet, unfortunately there are still some issues
	 * preventing trampoline.S from using this code... ho hum.
	 */
	.globl	setup_trap_table
setup_trap_table:
	save	%sp, -192, %sp

	/* Force interrupts to be disabled. */
	rdpr	%pstate, %o1
	andn	%o1, PSTATE_IE, %o1
	wrpr	%o1, 0x0, %pstate
	wrpr	%g0, 15, %pil

	/* Make the firmware call to jump over to the Linux trap table.  */
	call	prom_set_trap_table
	 sethi	%hi(sparc64_ttable_tl0), %o0

	/* Start using proper page size encodings in ctx register.  */
	sethi	%hi(sparc64_kern_pri_context), %g3
	ldx	[%g3 + %lo(sparc64_kern_pri_context)], %g2
	mov	PRIMARY_CONTEXT, %g1
	stxa	%g2, [%g1] ASI_DMMU
	membar	#Sync

	/* Kill PROM timer */
	sethi	%hi(0x80000000), %o2
	sllx	%o2, 32, %o2
	wr	%o2, 0, %tick_cmpr

	BRANCH_IF_ANY_CHEETAH(o2,o3,1f)

	ba,pt	%xcc, 2f
	 nop

	/* Disable STICK_INT interrupts. */
1:
	sethi	%hi(0x80000000), %o2
	sllx	%o2, 32, %o2
	wr	%o2, %asr25

2:
	wrpr	%g0, %g0, %wstate

	call	init_irqwork_curcpu
	 nop

	/* Now we can turn interrupts back on. */
	rdpr	%pstate, %o1
	or	%o1, PSTATE_IE, %o1
	wrpr	%o1, 0, %pstate
	wrpr	%g0, 0x0, %pil

	ret
	 restore

	.globl	setup_tba
setup_tba:
	save	%sp, -192, %sp

	/* The boot processor is the only cpu which invokes this
	 * routine, the other cpus set things up via trampoline.S.
	 * So save the OBP trap table address here.
	 */
	rdpr	%tba, %g7
	sethi	%hi(prom_tba), %o1
	or	%o1, %lo(prom_tba), %o1
	stx	%g7, [%o1]

	call	setup_trap_table
	 nop

	ret
	 restore
sparc64_boot_end:

#include "systbls.S"
#include "sun4v_tlb_miss.S"
#include "ktlb.S"
#include "tsb.S"
#include "etrap.S"
#include "rtrap.S"
#include "winfixup.S"
#include "entry.S"

/*
 * The following skip makes sure the trap table in ttable.S is aligned
 * on a 32K boundary as required by the v9 specs for TBA register.
 *
 * We align to a 32K boundary, then we have the 32K kernel TSB,
 * then the 32K aligned trap table.
 */
1:
	.skip	0x4000 + _start - 1b

	.globl	swapper_tsb
swapper_tsb:
	.skip	(32 * 1024)

! 0x0000000000408000

#include "ttable.S"

	.data
	.align	8
	.globl	prom_tba, tlb_type
prom_tba:	.xword	0
tlb_type:	.word	0	/* Must NOT end up in BSS */
	.section	".fixup",#alloc,#execinstr

	.globl	__ret_efault, __retl_efault
__ret_efault:
	ret
	 restore %g0, -EFAULT, %o0
__retl_efault:
	retl
	 mov	-EFAULT, %o0
Commit	Line	Data
1da177e4 LT	1	/* $Id: head.S,v 1.87 2002/02/09 19:49:31 davem Exp $
	2	* head.S: Initial boot code for the Sparc64 port of Linux.
	3	*
	4	* Copyright (C) 1996,1997 David S. Miller (davem@caip.rutgers.edu)
	5	* Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
	6	* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	7	* Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
	8	*/
	9
	10	#include <linux/config.h>
	11	#include <linux/version.h>
	12	#include <linux/errno.h>
	13	#include <asm/thread_info.h>
	14	#include <asm/asi.h>
	15	#include <asm/pstate.h>
	16	#include <asm/ptrace.h>
	17	#include <asm/spitfire.h>
	18	#include <asm/page.h>
	19	#include <asm/pgtable.h>
	20	#include <asm/errno.h>
	21	#include <asm/signal.h>
	22	#include <asm/processor.h>
	23	#include <asm/lsu.h>
	24	#include <asm/dcr.h>
	25	#include <asm/dcu.h>
	26	#include <asm/head.h>
	27	#include <asm/ttable.h>
	28	#include <asm/mmu.h>
56fb4df6	29	#include <asm/cpudata.h>
1da177e4 LT	30
1da177e4 LT	31	/* This section from from _start to sparc64_boot_end should fit into
c9c10830	32	* 0x0000000000404000 to 0x0000000000408000.
1da177e4	33	*/
1da177e4 LT	34	.text
	35	.globl start, _start, stext, _stext
	36	_start:
	37	start:
	38	_stext:
	39	stext:
1da177e4 LT	40	! 0x0000000000404000
	41	b sparc64_boot
	42	flushw /* Flush register file. */
	43
	44	/* This stuff has to be in sync with SILO and other potential boot loaders
	45	* Fields should be kept upward compatible and whenever any change is made,
	46	* HdrS version should be incremented.
	47	*/
	48	.global root_flags, ram_flags, root_dev
	49	.global sparc_ramdisk_image, sparc_ramdisk_size
	50	.global sparc_ramdisk_image64
	51
	52	.ascii "HdrS"
	53	.word LINUX_VERSION_CODE
	54
	55	/* History:
	56	*
	57	* 0x0300 : Supports being located at other than 0x4000
	58	* 0x0202 : Supports kernel params string
	59	* 0x0201 : Supports reboot_command
	60	*/
	61	.half 0x0301 /* HdrS version */
	62
	63	root_flags:
	64	.half 1
	65	root_dev:
	66	.half 0
	67	ram_flags:
	68	.half 0
	69	sparc_ramdisk_image:
	70	.word 0
	71	sparc_ramdisk_size:
	72	.word 0
	73	.xword reboot_command
	74	.xword bootstr_info
	75	sparc_ramdisk_image64:
	76	.xword 0
	77	.word _end
	78
bff06d55 DM	79	/* PROM cif handler code address is in %o4. */
	80	sparc64_boot:
	81	1: rd %pc, %g7
	82	set 1b, %g1
	83	cmp %g1, %g7
	84	be,pn %xcc, sparc64_boot_after_remap
	85	mov %o4, %l7
	86
	87	/* We need to remap the kernel. Use position independant
	88	* code to remap us to KERNBASE.
1da177e4	89	*
bff06d55 DM	90	* SILO can invoke us with 32-bit address masking enabled,
bff06d55 DM	91	* so make sure that's clear.
1da177e4	92	*/
bff06d55 DM	93	rdpr %pstate, %g1
	94	andn %g1, PSTATE_AM, %g1
	95	wrpr %g1, 0x0, %pstate
	96	ba,a,pt %xcc, 1f
	97
	98	.globl prom_finddev_name, prom_chosen_path
	99	.globl prom_getprop_name, prom_mmu_name
	100	.globl prom_callmethod_name, prom_translate_name
	101	.globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
	102	.globl prom_boot_mapped_pc, prom_boot_mapping_mode
	103	.globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
	104	prom_finddev_name:
	105	.asciz "finddevice"
	106	prom_chosen_path:
	107	.asciz "/chosen"
	108	prom_getprop_name:
	109	.asciz "getprop"
	110	prom_mmu_name:
	111	.asciz "mmu"
	112	prom_callmethod_name:
	113	.asciz "call-method"
	114	prom_translate_name:
	115	.asciz "translate"
	116	prom_map_name:
	117	.asciz "map"
	118	prom_unmap_name:
	119	.asciz "unmap"
	120	.align 4
	121	prom_mmu_ihandle_cache:
	122	.word 0
	123	prom_boot_mapped_pc:
	124	.word 0
	125	prom_boot_mapping_mode:
	126	.word 0
	127	.align 8
	128	prom_boot_mapping_phys_high:
	129	.xword 0
	130	prom_boot_mapping_phys_low:
	131	.xword 0
	132	1:
	133	rd %pc, %l0
	134	mov (1b - prom_finddev_name), %l1
	135	mov (1b - prom_chosen_path), %l2
	136	mov (1b - prom_boot_mapped_pc), %l3
	137	sub %l0, %l1, %l1
	138	sub %l0, %l2, %l2
	139	sub %l0, %l3, %l3
	140	stw %l0, [%l3]
	141	sub %sp, (192 + 128), %sp
	142
	143	/* chosen_node = prom_finddevice("/chosen") */
	144	stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
	145	mov 1, %l3
	146	stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
	147	stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
	148	stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
	149	stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
	150	call %l7
	151	add %sp, (2047 + 128), %o0 ! argument array
	152
	153	ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
	154
	155	mov (1b - prom_getprop_name), %l1
	156	mov (1b - prom_mmu_name), %l2
157	mov (1b - prom_mmu_ihandle_cache), %l5
158	sub %l0, %l1, %l1
159	sub %l0, %l2, %l2
160	sub %l0, %l5, %l5
161
162	/* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
163	stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
164	mov 4, %l3
165	stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
166	mov 1, %l3
167	stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
168	stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
169	stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
170	stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
171	mov 4, %l3
172	stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
173	stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
174	call %l7
175	add %sp, (2047 + 128), %o0 ! argument array
176
177	mov (1b - prom_callmethod_name), %l1
178	mov (1b - prom_translate_name), %l2
179	sub %l0, %l1, %l1
180	sub %l0, %l2, %l2
181	lduw [%l5], %l5 ! prom_mmu_ihandle_cache
182
183	stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
184	mov 3, %l3
185	stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
186	mov 5, %l3
187	stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
188	stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
189	stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
b1b510aa DM	190	/* PAGE align */
	191	srlx %l0, 13, %l3
	192	sllx %l3, 13, %l3
bff06d55 DM	193	stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
	194	stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
	195	stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
	196	stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
	197	stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
	198	stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
	199	call %l7
	200	add %sp, (2047 + 128), %o0 ! argument array
	201
	202	ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
	203	mov (1b - prom_boot_mapping_mode), %l4
	204	sub %l0, %l4, %l4
	205	stw %l1, [%l4]
	206	mov (1b - prom_boot_mapping_phys_high), %l4
	207	sub %l0, %l4, %l4
	208	ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
	209	stx %l2, [%l4 + 0x0]
	210	ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
b1b510aa DM	211	/* 4MB align */
	212	srlx %l3, 22, %l3
	213	sllx %l3, 22, %l3
bff06d55 DM	214	stx %l3, [%l4 + 0x8]
	215
	216	/* Leave service as-is, "call-method" */
	217	mov 7, %l3
	218	stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
	219	mov 1, %l3
a8201c61	220	stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
bff06d55 DM	221	mov (1b - prom_map_name), %l3
	222	sub %l0, %l3, %l3
	223	stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
	224	/* Leave arg2 as-is, prom_mmu_ihandle_cache */
	225	mov -1, %l3
	226	stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
	227	sethi %hi(8 * 1024 * 1024), %l3
	228	stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: size (8MB)
	229	sethi %hi(KERNBASE), %l3
	230	stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
	231	stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
	232	mov (1b - prom_boot_mapping_phys_low), %l3
	233	sub %l0, %l3, %l3
	234	ldx [%l3], %l3
	235	stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
	236	call %l7
	237	add %sp, (2047 + 128), %o0 ! argument array
	238
	239	add %sp, (192 + 128), %sp
	240
	241	sparc64_boot_after_remap:
1da177e4 LT	242	BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
	243	BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
	244	ba,pt %xcc, spitfire_boot
	245	nop
	246
	247	cheetah_plus_boot:
	248	/* Preserve OBP chosen DCU and DCR register settings. */
	249	ba,pt %xcc, cheetah_generic_boot
	250	nop
	251
	252	cheetah_boot:
	253	mov DCR_BPE \| DCR_RPE \| DCR_SI \| DCR_IFPOE \| DCR_MS, %g1
	254	wr %g1, %asr18
	255
	256	sethi %uhi(DCU_ME\|DCU_RE\|DCU_HPE\|DCU_SPE\|DCU_SL\|DCU_WE), %g7
	257	or %g7, %ulo(DCU_ME\|DCU_RE\|DCU_HPE\|DCU_SPE\|DCU_SL\|DCU_WE), %g7
	258	sllx %g7, 32, %g7
	259	or %g7, DCU_DM \| DCU_IM \| DCU_DC \| DCU_IC, %g7
	260	stxa %g7, [%g0] ASI_DCU_CONTROL_REG
	261	membar #Sync
	262
	263	cheetah_generic_boot:
	264	mov TSB_EXTENSION_P, %g3
	265	stxa %g0, [%g3] ASI_DMMU
	266	stxa %g0, [%g3] ASI_IMMU
	267	membar #Sync
	268
	269	mov TSB_EXTENSION_S, %g3
	270	stxa %g0, [%g3] ASI_DMMU
	271	membar #Sync
	272
	273	mov TSB_EXTENSION_N, %g3
	274	stxa %g0, [%g3] ASI_DMMU
	275	stxa %g0, [%g3] ASI_IMMU
	276	membar #Sync
	277
bff06d55	278	ba,a,pt %xcc, jump_to_sun4u_init
1da177e4 LT	279
	280	spitfire_boot:
	281	/* Typically PROM has already enabled both MMU's and both on-chip
	282	* caches, but we do it here anyway just to be paranoid.
	283	*/
	284	mov (LSU_CONTROL_IC\|LSU_CONTROL_DC\|LSU_CONTROL_IM\|LSU_CONTROL_DM), %g1
	285	stxa %g1, [%g0] ASI_LSU_CONTROL
	286	membar #Sync
	287
bff06d55	288	jump_to_sun4u_init:
1da177e4 LT	289	/*
	290	* Make sure we are in privileged mode, have address masking,
	291	* using the ordinary globals and have enabled floating
	292	* point.
	293	*
	294	* Again, typically PROM has left %pil at 13 or similar, and
	295	* (PSTATE_PRIV \| PSTATE_PEF \| PSTATE_IE) in %pstate.
	296	*/
	297	wrpr %g0, (PSTATE_PRIV\|PSTATE_PEF\|PSTATE_IE), %pstate
	298	wr %g0, 0, %fprs
	299
1da177e4 LT	300	set sun4u_init, %g2
	301	jmpl %g2 + %g0, %g0
	302	nop
	303
	304	sun4u_init:
	305	/* Set ctx 0 */
	306	mov PRIMARY_CONTEXT, %g7
	307	stxa %g0, [%g7] ASI_DMMU
	308	membar #Sync
	309
	310	mov SECONDARY_CONTEXT, %g7
	311	stxa %g0, [%g7] ASI_DMMU
	312	membar #Sync
	313
1da177e4 LT	314	BRANCH_IF_ANY_CHEETAH(g1,g7,cheetah_tlb_fixup)
	315
	316	ba,pt %xcc, spitfire_tlb_fixup
	317	nop
	318
	319	cheetah_tlb_fixup:
1da177e4 LT	320	mov 2, %g2 /* Set TLB type to cheetah+. */
	321	BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
	322
	323	mov 1, %g2 /* Set TLB type to cheetah. */
	324
	325	1: sethi %hi(tlb_type), %g1
	326	stw %g2, [%g1 + %lo(tlb_type)]
	327
0835ae0f	328	/* Patch copy/page operations to cheetah optimized versions. */
1da177e4 LT	329	call cheetah_patch_copyops
1da177e4 LT	330	nop
dbd2fdf5 DM	331	call cheetah_patch_copy_page
dbd2fdf5 DM	332	nop
1da177e4 LT	333	call cheetah_patch_cachetlbops
	334	nop
	335
	336	ba,pt %xcc, tlb_fixup_done
	337	nop
	338
	339	spitfire_tlb_fixup:
1da177e4 LT	340	/* Set TLB type to spitfire. */
	341	mov 0, %g2
	342	sethi %hi(tlb_type), %g1
	343	stw %g2, [%g1 + %lo(tlb_type)]
	344
	345	tlb_fixup_done:
	346	sethi %hi(init_thread_union), %g6
	347	or %g6, %lo(init_thread_union), %g6
	348	ldx [%g6 + TI_TASK], %g4
	349	mov %sp, %l6
	350	mov %o4, %l7
	351
1da177e4 LT	352	wr %g0, ASI_P, %asi
	353	mov 1, %g1
	354	sllx %g1, THREAD_SHIFT, %g1
	355	sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
	356	add %g6, %g1, %sp
	357	mov 0, %fp
	358
	359	/* Set per-cpu pointer initially to zero, this makes
	360	* the boot-cpu use the in-kernel-image per-cpu areas
	361	* before setup_per_cpu_area() is invoked.
	362	*/
	363	clr %g5
	364
	365	wrpr %g0, 0, %wstate
	366	wrpr %g0, 0x0, %tl
	367
	368	/* Clear the bss */
	369	sethi %hi(__bss_start), %o0
	370	or %o0, %lo(__bss_start), %o0
	371	sethi %hi(_end), %o1
	372	or %o1, %lo(_end), %o1
	373	call __bzero
	374	sub %o1, %o0, %o1
	375
	376	mov %l6, %o1 ! OpenPROM stack
	377	call prom_init
	378	mov %l7, %o0 ! OpenPROM cif handler
	379
	380	/* Off we go.... */
	381	call start_kernel
	382	nop
	383	/* Not reached... */
	384
5d8e1b18 DM	385	/* This is meant to allow the sharing of this code between
	386	* boot processor invocation (via setup_tba() below) and
	387	* secondary processor startup (via trampoline.S). The
	388	* former does use this code, the latter does not yet due
	389	* to some complexities. That should be fixed up at some
	390	* point.
c9c10830 DM	391	*
	392	* There used to be enormous complexity wrt. transferring
	393	* over from the firwmare's trap table to the Linux kernel's.
	394	* For example, there was a chicken & egg problem wrt. building
	395	* the OBP page tables, yet needing to be on the Linux kernel
	396	* trap table (to translate PAGE_OFFSET addresses) in order to
	397	* do that.
	398	*
	399	* We now handle OBP tlb misses differently, via linear lookups
	400	* into the prom_trans[] array. So that specific problem no
	401	* longer exists. Yet, unfortunately there are still some issues
	402	* preventing trampoline.S from using this code... ho hum.
5d8e1b18 DM	403	*/
	404	.globl setup_trap_table
	405	setup_trap_table:
	406	save %sp, -192, %sp
	407
c9c10830	408	/* Force interrupts to be disabled. */
5d8e1b18 DM	409	rdpr %pstate, %o1
	410	andn %o1, PSTATE_IE, %o1
	411	wrpr %o1, 0x0, %pstate
	412	wrpr %g0, 15, %pil
1da177e4	413
c9c10830	414	/* Make the firmware call to jump over to the Linux trap table. */
5d8e1b18 DM	415	call prom_set_trap_table
	416	sethi %hi(sparc64_ttable_tl0), %o0
	417
	418	/* Start using proper page size encodings in ctx register. */
	419	sethi %hi(sparc64_kern_pri_context), %g3
	420	ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
	421	mov PRIMARY_CONTEXT, %g1
	422	stxa %g2, [%g1] ASI_DMMU
	423	membar #Sync
	424
1da177e4 LT	425	/* Kill PROM timer */
	426	sethi %hi(0x80000000), %o2
	427	sllx %o2, 32, %o2
	428	wr %o2, 0, %tick_cmpr
	429
	430	BRANCH_IF_ANY_CHEETAH(o2,o3,1f)
	431
	432	ba,pt %xcc, 2f
	433	nop
	434
	435	/* Disable STICK_INT interrupts. */
	436	1:
	437	sethi %hi(0x80000000), %o2
	438	sllx %o2, 32, %o2
	439	wr %o2, %asr25
	440
1da177e4 LT	441	2:
1da177e4 LT	442	wrpr %g0, %g0, %wstate
1da177e4 LT	443
	444	call init_irqwork_curcpu
	445	nop
	446
5d8e1b18	447	/* Now we can turn interrupts back on. */
1da177e4 LT	448	rdpr %pstate, %o1
	449	or %o1, PSTATE_IE, %o1
	450	wrpr %o1, 0, %pstate
5d8e1b18 DM	451	wrpr %g0, 0x0, %pil
	452
	453	ret
	454	restore
	455
	456	.globl setup_tba
a8b900d8	457	setup_tba:
5d8e1b18 DM	458	save %sp, -192, %sp
	459
	460	/* The boot processor is the only cpu which invokes this
	461	* routine, the other cpus set things up via trampoline.S.
	462	* So save the OBP trap table address here.
	463	*/
	464	rdpr %tba, %g7
	465	sethi %hi(prom_tba), %o1
	466	or %o1, %lo(prom_tba), %o1
	467	stx %g7, [%o1]
	468
	469	call setup_trap_table
	470	nop
1da177e4 LT	471
	472	ret
	473	restore
c9c10830 DM	474	sparc64_boot_end:
	475
	476	#include "systbls.S"
d257d5da	477	#include "sun4v_tlb_miss.S"
c9c10830	478	#include "ktlb.S"
74bf4312	479	#include "tsb.S"
c9c10830 DM	480	#include "etrap.S"
	481	#include "rtrap.S"
	482	#include "winfixup.S"
	483	#include "entry.S"
1da177e4 LT	484
1da177e4 LT	485	/*
c9c10830	486	* The following skip makes sure the trap table in ttable.S is aligned
1da177e4	487	* on a 32K boundary as required by the v9 specs for TBA register.
2f7ee7c6 DM	488	*
	489	* We align to a 32K boundary, then we have the 32K kernel TSB,
	490	* then the 32K aligned trap table.
1da177e4	491	*/
c9c10830 DM	492	1:
c9c10830 DM	493	.skip 0x4000 + _start - 1b
1da177e4	494
2f7ee7c6 DM	495	.globl swapper_tsb
	496	swapper_tsb:
	497	.skip (32 * 1024)
1da177e4 LT	498
	499	! 0x0000000000408000
	500
	501	#include "ttable.S"
1da177e4 LT	502
	503	.data
	504	.align 8
	505	.globl prom_tba, tlb_type
	506	prom_tba: .xword 0
	507	tlb_type: .word 0 /* Must NOT end up in BSS */
	508	.section ".fixup",#alloc,#execinstr
5fd29752 DM	509
5fd29752 DM	510	.globl __ret_efault, __retl_efault
1da177e4 LT	511	__ret_efault:
	512	ret
	513	restore %g0, -EFAULT, %o0
5fd29752 DM	514	__retl_efault:
	515	retl
	516	mov -EFAULT, %o0