[linux-2.6-block.git] / arch / sparc64 / kernel / head.S

/* $Id: head.S,v 1.87 2002/02/09 19:49:31 davem Exp $
 * head.S: Initial boot code for the Sparc64 port of Linux.
 *
 * Copyright (C) 1996,1997 David S. Miller (davem@caip.rutgers.edu)
 * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
 */

#include <linux/version.h>
#include <linux/errno.h>
#include <linux/threads.h>
#include <asm/thread_info.h>
#include <asm/asi.h>
#include <asm/pstate.h>
#include <asm/ptrace.h>
#include <asm/spitfire.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/errno.h>
#include <asm/signal.h>
#include <asm/processor.h>
#include <asm/lsu.h>
#include <asm/dcr.h>
#include <asm/dcu.h>
#include <asm/head.h>
#include <asm/ttable.h>
#include <asm/mmu.h>
#include <asm/cpudata.h>
	
/* This section from from _start to sparc64_boot_end should fit into
 * 0x0000000000404000 to 0x0000000000408000.
 */
	.text
	.globl	start, _start, stext, _stext
_start:
start:
_stext:
stext:
! 0x0000000000404000
	b	sparc64_boot
	 flushw					/* Flush register file.      */

/* This stuff has to be in sync with SILO and other potential boot loaders
 * Fields should be kept upward compatible and whenever any change is made,
 * HdrS version should be incremented.
 */
        .global root_flags, ram_flags, root_dev
        .global sparc_ramdisk_image, sparc_ramdisk_size
	.global sparc_ramdisk_image64

        .ascii  "HdrS"
        .word   LINUX_VERSION_CODE

	/* History:
	 *
	 * 0x0300 : Supports being located at other than 0x4000
	 * 0x0202 : Supports kernel params string
	 * 0x0201 : Supports reboot_command
	 */
	.half   0x0301          /* HdrS version */

root_flags:
        .half   1
root_dev:
        .half   0
ram_flags:
        .half   0
sparc_ramdisk_image:
        .word   0
sparc_ramdisk_size:
        .word   0
        .xword  reboot_command
	.xword	bootstr_info
sparc_ramdisk_image64:
	.xword	0
	.word	_end

	/* PROM cif handler code address is in %o4.  */
sparc64_boot:
1:	rd	%pc, %g7
	set	1b, %g1
	cmp	%g1, %g7
	be,pn	%xcc, sparc64_boot_after_remap
	 mov	%o4, %l7

	/* We need to remap the kernel.  Use position independant
	 * code to remap us to KERNBASE.
	 *
	 * SILO can invoke us with 32-bit address masking enabled,
	 * so make sure that's clear.
	 */
	rdpr	%pstate, %g1
	andn	%g1, PSTATE_AM, %g1
	wrpr	%g1, 0x0, %pstate
	ba,a,pt	%xcc, 1f

	.globl	prom_finddev_name, prom_chosen_path, prom_root_node
	.globl	prom_getprop_name, prom_mmu_name, prom_peer_name
	.globl	prom_callmethod_name, prom_translate_name, prom_root_compatible
	.globl	prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
	.globl	prom_boot_mapped_pc, prom_boot_mapping_mode
	.globl	prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
	.globl	is_sun4v
prom_peer_name:
	.asciz	"peer"
prom_compatible_name:
	.asciz	"compatible"
prom_finddev_name:
	.asciz	"finddevice"
prom_chosen_path:
	.asciz	"/chosen"
prom_getprop_name:
	.asciz	"getprop"
prom_mmu_name:
	.asciz	"mmu"
prom_callmethod_name:
	.asciz	"call-method"
prom_translate_name:
	.asciz	"translate"
prom_map_name:
	.asciz	"map"
prom_unmap_name:
	.asciz	"unmap"
prom_sun4v_name:
	.asciz	"sun4v"
	.align	4
prom_root_compatible:
	.skip	64
prom_root_node:
	.word	0
prom_mmu_ihandle_cache:
	.word	0
prom_boot_mapped_pc:
	.word	0
prom_boot_mapping_mode:
	.word	0
	.align	8
prom_boot_mapping_phys_high:
	.xword	0
prom_boot_mapping_phys_low:
	.xword	0
is_sun4v:
	.word	0
1:
	rd	%pc, %l0

	mov	(1b - prom_peer_name), %l1
	sub	%l0, %l1, %l1
	mov	0, %l2

	/* prom_root_node = prom_peer(0) */
	stx	%l1, [%sp + 2047 + 128 + 0x00]	! service, "peer"
	mov	1, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x08]	! num_args, 1
	stx	%l3, [%sp + 2047 + 128 + 0x10]	! num_rets, 1
	stx	%l2, [%sp + 2047 + 128 + 0x18]	! arg1, 0
	stx	%g0, [%sp + 2047 + 128 + 0x20]	! ret1
	call	%l7
	 add	%sp, (2047 + 128), %o0		! argument array

	ldx	[%sp + 2047 + 128 + 0x20], %l4	! prom root node
	mov	(1b - prom_root_node), %l1
	sub	%l0, %l1, %l1
	stw	%l4, [%l1]

	mov	(1b - prom_getprop_name), %l1
	mov	(1b - prom_compatible_name), %l2
	mov	(1b - prom_root_compatible), %l5
	sub	%l0, %l1, %l1
	sub	%l0, %l2, %l2
	sub	%l0, %l5, %l5

	/* prom_getproperty(prom_root_node, "compatible",
	 *                  &prom_root_compatible, 64)
	 */
	stx	%l1, [%sp + 2047 + 128 + 0x00]	! service, "getprop"
	mov	4, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x08]	! num_args, 4
	mov	1, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x10]	! num_rets, 1
	stx	%l4, [%sp + 2047 + 128 + 0x18]	! arg1, prom_root_node
	stx	%l2, [%sp + 2047 + 128 + 0x20]	! arg2, "compatible"
	stx	%l5, [%sp + 2047 + 128 + 0x28]	! arg3, &prom_root_compatible
	mov	64, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x30]	! arg4, size
	stx	%g0, [%sp + 2047 + 128 + 0x38]	! ret1
	call	%l7
	 add	%sp, (2047 + 128), %o0		! argument array

	mov	(1b - prom_finddev_name), %l1
	mov	(1b - prom_chosen_path), %l2
	mov	(1b - prom_boot_mapped_pc), %l3
	sub	%l0, %l1, %l1
	sub	%l0, %l2, %l2
	sub	%l0, %l3, %l3
	stw	%l0, [%l3]
	sub	%sp, (192 + 128), %sp

	/* chosen_node = prom_finddevice("/chosen") */
	stx	%l1, [%sp + 2047 + 128 + 0x00]	! service, "finddevice"
	mov	1, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x08]	! num_args, 1
	stx	%l3, [%sp + 2047 + 128 + 0x10]	! num_rets, 1
	stx	%l2, [%sp + 2047 + 128 + 0x18]	! arg1, "/chosen"
	stx	%g0, [%sp + 2047 + 128 + 0x20]	! ret1
	call	%l7
	 add	%sp, (2047 + 128), %o0		! argument array

	ldx	[%sp + 2047 + 128 + 0x20], %l4	! chosen device node

	mov	(1b - prom_getprop_name), %l1
	mov	(1b - prom_mmu_name), %l2
	mov	(1b - prom_mmu_ihandle_cache), %l5
	sub	%l0, %l1, %l1
	sub	%l0, %l2, %l2
	sub	%l0, %l5, %l5

	/* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
	stx	%l1, [%sp + 2047 + 128 + 0x00]	! service, "getprop"
	mov	4, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x08]	! num_args, 4
	mov	1, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x10]	! num_rets, 1
	stx	%l4, [%sp + 2047 + 128 + 0x18]	! arg1, chosen_node
	stx	%l2, [%sp + 2047 + 128 + 0x20]	! arg2, "mmu"
	stx	%l5, [%sp + 2047 + 128 + 0x28]	! arg3, &prom_mmu_ihandle_cache
	mov	4, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x30]	! arg4, sizeof(arg3)
	stx	%g0, [%sp + 2047 + 128 + 0x38]	! ret1
	call	%l7
	 add	%sp, (2047 + 128), %o0		! argument array

	mov	(1b - prom_callmethod_name), %l1
	mov	(1b - prom_translate_name), %l2
	sub	%l0, %l1, %l1
	sub	%l0, %l2, %l2
	lduw	[%l5], %l5			! prom_mmu_ihandle_cache

	stx	%l1, [%sp + 2047 + 128 + 0x00]	! service, "call-method"
	mov	3, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x08]	! num_args, 3
	mov	5, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x10]	! num_rets, 5
	stx	%l2, [%sp + 2047 + 128 + 0x18]	! arg1: "translate"
	stx	%l5, [%sp + 2047 + 128 + 0x20]	! arg2: prom_mmu_ihandle_cache
	/* PAGE align */
	srlx	%l0, 13, %l3
	sllx	%l3, 13, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x28]	! arg3: vaddr, our PC
	stx	%g0, [%sp + 2047 + 128 + 0x30]	! res1
	stx	%g0, [%sp + 2047 + 128 + 0x38]	! res2
	stx	%g0, [%sp + 2047 + 128 + 0x40]	! res3
	stx	%g0, [%sp + 2047 + 128 + 0x48]	! res4
	stx	%g0, [%sp + 2047 + 128 + 0x50]	! res5
	call	%l7
	 add	%sp, (2047 + 128), %o0		! argument array

	ldx	[%sp + 2047 + 128 + 0x40], %l1	! translation mode
	mov	(1b - prom_boot_mapping_mode), %l4
	sub	%l0, %l4, %l4
	stw	%l1, [%l4]
	mov	(1b - prom_boot_mapping_phys_high), %l4
	sub	%l0, %l4, %l4
	ldx	[%sp + 2047 + 128 + 0x48], %l2	! physaddr high
	stx	%l2, [%l4 + 0x0]
	ldx	[%sp + 2047 + 128 + 0x50], %l3	! physaddr low
	/* 4MB align */
	srlx	%l3, 22, %l3
	sllx	%l3, 22, %l3
	stx	%l3, [%l4 + 0x8]

	/* Leave service as-is, "call-method" */
	mov	7, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x08]	! num_args, 7
	mov	1, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x10]	! num_rets, 1
	mov	(1b - prom_map_name), %l3
	sub	%l0, %l3, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x18]	! arg1: "map"
	/* Leave arg2 as-is, prom_mmu_ihandle_cache */
	mov	-1, %l3
	stx	%l3, [%sp + 2047 + 128 + 0x28]	! arg3: mode (-1 default)
	sethi	%hi(8 * 1024 * 1024), %l3
	stx	%l3, [%sp + 2047 + 128 + 0x30]	! arg4: size (8MB)
	sethi	%hi(KERNBASE), %l3
	stx	%l3, [%sp + 2047 + 128 + 0x38]	! arg5: vaddr (KERNBASE)
	stx	%g0, [%sp + 2047 + 128 + 0x40]	! arg6: empty
	mov	(1b - prom_boot_mapping_phys_low), %l3
	sub	%l0, %l3, %l3
	ldx	[%l3], %l3
	stx	%l3, [%sp + 2047 + 128 + 0x48]	! arg7: phys addr
	call	%l7
	 add	%sp, (2047 + 128), %o0		! argument array

	add	%sp, (192 + 128), %sp

sparc64_boot_after_remap:
	sethi	%hi(prom_root_compatible), %g1
	or	%g1, %lo(prom_root_compatible), %g1
	sethi	%hi(prom_sun4v_name), %g7
	or	%g7, %lo(prom_sun4v_name), %g7
	mov	5, %g3
1:	ldub	[%g7], %g2
	ldub	[%g1], %g4
	cmp	%g2, %g4
	bne,pn	%icc, 2f
	 add	%g7, 1, %g7
	subcc	%g3, 1, %g3
	bne,pt	%xcc, 1b
	 add	%g1, 1, %g1

	sethi	%hi(is_sun4v), %g1
	or	%g1, %lo(is_sun4v), %g1
	mov	1, %g7
	stw	%g7, [%g1]

2:
	BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
	BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
	BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
	ba,pt	%xcc, spitfire_boot
	 nop

cheetah_plus_boot:
	/* Preserve OBP chosen DCU and DCR register settings.  */
	ba,pt	%xcc, cheetah_generic_boot
	 nop

cheetah_boot:
	mov	DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
	wr	%g1, %asr18

	sethi	%uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
	or	%g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
	sllx	%g7, 32, %g7
	or	%g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
	stxa	%g7, [%g0] ASI_DCU_CONTROL_REG
	membar	#Sync

cheetah_generic_boot:
	mov	TSB_EXTENSION_P, %g3
	stxa	%g0, [%g3] ASI_DMMU
	stxa	%g0, [%g3] ASI_IMMU
	membar	#Sync

	mov	TSB_EXTENSION_S, %g3
	stxa	%g0, [%g3] ASI_DMMU
	membar	#Sync

	mov	TSB_EXTENSION_N, %g3
	stxa	%g0, [%g3] ASI_DMMU
	stxa	%g0, [%g3] ASI_IMMU
	membar	#Sync

	ba,a,pt	%xcc, jump_to_sun4u_init

spitfire_boot:
	/* Typically PROM has already enabled both MMU's and both on-chip
	 * caches, but we do it here anyway just to be paranoid.
	 */
	mov	(LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
	stxa	%g1, [%g0] ASI_LSU_CONTROL
	membar	#Sync

jump_to_sun4u_init:
	/*
	 * Make sure we are in privileged mode, have address masking,
         * using the ordinary globals and have enabled floating
         * point.
	 *
	 * Again, typically PROM has left %pil at 13 or similar, and
	 * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
         */
	wrpr    %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
	wr	%g0, 0, %fprs

	set	sun4u_init, %g2
	jmpl    %g2 + %g0, %g0
	 nop

sun4u_init:
	BRANCH_IF_SUN4V(g1, sun4v_init)

	/* Set ctx 0 */
	mov		PRIMARY_CONTEXT, %g7
	stxa		%g0, [%g7] ASI_DMMU
	membar		#Sync

	mov		SECONDARY_CONTEXT, %g7
	stxa		%g0, [%g7] ASI_DMMU
	membar	#Sync

	ba,pt		%xcc, sun4u_continue
	 nop

sun4v_init:
	/* Set ctx 0 */
	mov		PRIMARY_CONTEXT, %g7
	stxa		%g0, [%g7] ASI_MMU
	membar		#Sync

	mov		SECONDARY_CONTEXT, %g7
	stxa		%g0, [%g7] ASI_MMU
	membar		#Sync
	ba,pt		%xcc, niagara_tlb_fixup
	 nop

sun4u_continue:
	BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)

	ba,pt	%xcc, spitfire_tlb_fixup
	 nop

niagara_tlb_fixup:
	mov	3, %g2		/* Set TLB type to hypervisor. */
	sethi	%hi(tlb_type), %g1
	stw	%g2, [%g1 + %lo(tlb_type)]

	/* Patch copy/clear ops.  */
	call	niagara_patch_copyops
	 nop
	call	niagara_patch_bzero
	 nop
	call	niagara_patch_pageops
	 nop

	/* Patch TLB/cache ops.  */
	call	hypervisor_patch_cachetlbops
	 nop

	ba,pt	%xcc, tlb_fixup_done
	 nop

cheetah_tlb_fixup:
	mov	2, %g2		/* Set TLB type to cheetah+. */
	BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)

	mov	1, %g2		/* Set TLB type to cheetah. */

1:	sethi	%hi(tlb_type), %g1
	stw	%g2, [%g1 + %lo(tlb_type)]

	/* Patch copy/page operations to cheetah optimized versions. */
	call	cheetah_patch_copyops
	 nop
	call	cheetah_patch_copy_page
	 nop
	call	cheetah_patch_cachetlbops
	 nop

	ba,pt	%xcc, tlb_fixup_done
	 nop

spitfire_tlb_fixup:
	/* Set TLB type to spitfire. */
	mov	0, %g2
	sethi	%hi(tlb_type), %g1
	stw	%g2, [%g1 + %lo(tlb_type)]

tlb_fixup_done:
	sethi	%hi(init_thread_union), %g6
	or	%g6, %lo(init_thread_union), %g6
	ldx	[%g6 + TI_TASK], %g4
	mov	%sp, %l6
	mov	%o4, %l7

	wr	%g0, ASI_P, %asi
	mov	1, %g1
	sllx	%g1, THREAD_SHIFT, %g1
	sub	%g1, (STACKFRAME_SZ + STACK_BIAS), %g1
	add	%g6, %g1, %sp
	mov	0, %fp

	/* Set per-cpu pointer initially to zero, this makes
	 * the boot-cpu use the in-kernel-image per-cpu areas
	 * before setup_per_cpu_area() is invoked.
	 */
	clr	%g5

	wrpr	%g0, 0, %wstate
	wrpr	%g0, 0x0, %tl

	/* Clear the bss */
	sethi	%hi(__bss_start), %o0
	or	%o0, %lo(__bss_start), %o0
	sethi	%hi(_end), %o1
	or	%o1, %lo(_end), %o1
	call	__bzero
	 sub	%o1, %o0, %o1

#ifdef CONFIG_LOCKDEP
	/* We have this call this super early, as even prom_init can grab
	 * spinlocks and thus call into the lockdep code.
	 */
	call	lockdep_init
	 nop
#endif

	mov	%l6, %o1			! OpenPROM stack
	call	prom_init
	 mov	%l7, %o0			! OpenPROM cif handler

	/* Initialize current_thread_info()->cpu as early as possible.
	 * In order to do that accurately we have to patch up the get_cpuid()
	 * assembler sequences.  And that, in turn, requires that we know
	 * if we are on a Starfire box or not.  While we're here, patch up
	 * the sun4v sequences as well.
	 */
	call	check_if_starfire
	 nop
	call	per_cpu_patch
	 nop
	call	sun4v_patch
	 nop

#ifdef CONFIG_SMP
	call	hard_smp_processor_id
	 nop
	cmp	%o0, NR_CPUS
	blu,pt	%xcc, 1f
	 nop
	call	boot_cpu_id_too_large
	 nop
	/* Not reached... */

1:
#else
	mov	0, %o0
#endif
	stb	%o0, [%g6 + TI_CPU]

	/* Off we go.... */
	call	start_kernel
	 nop
	/* Not reached... */

	/* This is meant to allow the sharing of this code between
	 * boot processor invocation (via setup_tba() below) and
	 * secondary processor startup (via trampoline.S).  The
	 * former does use this code, the latter does not yet due
	 * to some complexities.  That should be fixed up at some
	 * point.
	 *
	 * There used to be enormous complexity wrt. transferring
	 * over from the firwmare's trap table to the Linux kernel's.
	 * For example, there was a chicken & egg problem wrt. building
	 * the OBP page tables, yet needing to be on the Linux kernel
	 * trap table (to translate PAGE_OFFSET addresses) in order to
	 * do that.
	 *
	 * We now handle OBP tlb misses differently, via linear lookups
	 * into the prom_trans[] array.  So that specific problem no
	 * longer exists.  Yet, unfortunately there are still some issues
	 * preventing trampoline.S from using this code... ho hum.
	 */
	.globl	setup_trap_table
setup_trap_table:
	save	%sp, -192, %sp

	/* Force interrupts to be disabled. */
	rdpr	%pstate, %l0
	andn	%l0, PSTATE_IE, %o1
	wrpr	%o1, 0x0, %pstate
	rdpr	%pil, %l1
	wrpr	%g0, 15, %pil

	/* Make the firmware call to jump over to the Linux trap table.  */
	sethi	%hi(is_sun4v), %o0
	lduw	[%o0 + %lo(is_sun4v)], %o0
	brz,pt	%o0, 1f
	 nop

	TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
	add	%g2, TRAP_PER_CPU_FAULT_INFO, %g2
	stxa	%g2, [%g0] ASI_SCRATCHPAD

	/* Compute physical address:
	 *
	 * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
	 */
	sethi	%hi(KERNBASE), %g3
	sub	%g2, %g3, %g2
	sethi	%hi(kern_base), %g3
	ldx	[%g3 + %lo(kern_base)], %g3
	add	%g2, %g3, %o1

	call	prom_set_trap_table_sun4v
	 sethi	%hi(sparc64_ttable_tl0), %o0

	ba,pt	%xcc, 2f
	 nop

1:	call	prom_set_trap_table
	 sethi	%hi(sparc64_ttable_tl0), %o0

	/* Start using proper page size encodings in ctx register.  */
2:	sethi	%hi(sparc64_kern_pri_context), %g3
	ldx	[%g3 + %lo(sparc64_kern_pri_context)], %g2

	mov		PRIMARY_CONTEXT, %g1

661:	stxa		%g2, [%g1] ASI_DMMU
	.section	.sun4v_1insn_patch, "ax"
	.word		661b
	stxa		%g2, [%g1] ASI_MMU
	.previous

	membar	#Sync

	/* Kill PROM timer */
	sethi	%hi(0x80000000), %o2
	sllx	%o2, 32, %o2
	wr	%o2, 0, %tick_cmpr

	BRANCH_IF_SUN4V(o2, 1f)
	BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)

	ba,pt	%xcc, 2f
	 nop

	/* Disable STICK_INT interrupts. */
1:
	sethi	%hi(0x80000000), %o2
	sllx	%o2, 32, %o2
	wr	%o2, %asr25

2:
	wrpr	%g0, %g0, %wstate

	call	init_irqwork_curcpu
	 nop

	/* Now we can restore interrupt state. */
	wrpr	%l0, 0, %pstate
	wrpr	%l1, 0x0, %pil

	ret
	 restore

	.globl	setup_tba
setup_tba:
	save	%sp, -192, %sp

	/* The boot processor is the only cpu which invokes this
	 * routine, the other cpus set things up via trampoline.S.
	 * So save the OBP trap table address here.
	 */
	rdpr	%tba, %g7
	sethi	%hi(prom_tba), %o1
	or	%o1, %lo(prom_tba), %o1
	stx	%g7, [%o1]

	call	setup_trap_table
	 nop

	ret
	 restore
sparc64_boot_end:

#include "ktlb.S"
#include "tsb.S"
#include "etrap.S"
#include "rtrap.S"
#include "winfixup.S"
#include "entry.S"
#include "sun4v_tlb_miss.S"
#include "sun4v_ivec.S"

/*
 * The following skip makes sure the trap table in ttable.S is aligned
 * on a 32K boundary as required by the v9 specs for TBA register.
 *
 * We align to a 32K boundary, then we have the 32K kernel TSB,
 * then the 32K aligned trap table.
 */
1:
	.skip	0x4000 + _start - 1b

	.globl	swapper_tsb
swapper_tsb:
	.skip	(32 * 1024)

! 0x0000000000408000

#include "ttable.S"

#include "systbls.S"

	.data
	.align	8
	.globl	prom_tba, tlb_type
prom_tba:	.xword	0
tlb_type:	.word	0	/* Must NOT end up in BSS */
	.section	".fixup",#alloc,#execinstr

	.globl	__ret_efault, __retl_efault
__ret_efault:
	ret
	 restore %g0, -EFAULT, %o0
__retl_efault:
	retl
	 mov	-EFAULT, %o0
Commit	Line	Data
1da177e4 LT	1	/* $Id: head.S,v 1.87 2002/02/09 19:49:31 davem Exp $
	2	* head.S: Initial boot code for the Sparc64 port of Linux.
	3	*
	4	* Copyright (C) 1996,1997 David S. Miller (davem@caip.rutgers.edu)
	5	* Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
	6	* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	7	* Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
	8	*/
	9
1da177e4 LT	10	#include <linux/version.h>
1da177e4 LT	11	#include <linux/errno.h>
951bc82c	12	#include <linux/threads.h>
1da177e4 LT	13	#include <asm/thread_info.h>
	14	#include <asm/asi.h>
	15	#include <asm/pstate.h>
	16	#include <asm/ptrace.h>
	17	#include <asm/spitfire.h>
	18	#include <asm/page.h>
	19	#include <asm/pgtable.h>
	20	#include <asm/errno.h>
	21	#include <asm/signal.h>
	22	#include <asm/processor.h>
	23	#include <asm/lsu.h>
	24	#include <asm/dcr.h>
	25	#include <asm/dcu.h>
	26	#include <asm/head.h>
	27	#include <asm/ttable.h>
	28	#include <asm/mmu.h>
56fb4df6	29	#include <asm/cpudata.h>
1da177e4 LT	30
1da177e4 LT	31	/* This section from from _start to sparc64_boot_end should fit into
c9c10830	32	* 0x0000000000404000 to 0x0000000000408000.
1da177e4	33	*/
1da177e4 LT	34	.text
	35	.globl start, _start, stext, _stext
	36	_start:
	37	start:
	38	_stext:
	39	stext:
1da177e4 LT	40	! 0x0000000000404000
	41	b sparc64_boot
	42	flushw /* Flush register file. */
	43
	44	/* This stuff has to be in sync with SILO and other potential boot loaders
	45	* Fields should be kept upward compatible and whenever any change is made,
	46	* HdrS version should be incremented.
	47	*/
	48	.global root_flags, ram_flags, root_dev
	49	.global sparc_ramdisk_image, sparc_ramdisk_size
	50	.global sparc_ramdisk_image64
	51
	52	.ascii "HdrS"
	53	.word LINUX_VERSION_CODE
	54
	55	/* History:
	56	*
	57	* 0x0300 : Supports being located at other than 0x4000
	58	* 0x0202 : Supports kernel params string
	59	* 0x0201 : Supports reboot_command
	60	*/
	61	.half 0x0301 /* HdrS version */
	62
	63	root_flags:
	64	.half 1
	65	root_dev:
	66	.half 0
	67	ram_flags:
	68	.half 0
	69	sparc_ramdisk_image:
	70	.word 0
	71	sparc_ramdisk_size:
	72	.word 0
	73	.xword reboot_command
	74	.xword bootstr_info
	75	sparc_ramdisk_image64:
	76	.xword 0
	77	.word _end
	78
bff06d55 DM	79	/* PROM cif handler code address is in %o4. */
	80	sparc64_boot:
	81	1: rd %pc, %g7
	82	set 1b, %g1
	83	cmp %g1, %g7
	84	be,pn %xcc, sparc64_boot_after_remap
	85	mov %o4, %l7
	86
	87	/* We need to remap the kernel. Use position independant
	88	* code to remap us to KERNBASE.
1da177e4	89	*
bff06d55 DM	90	* SILO can invoke us with 32-bit address masking enabled,
bff06d55 DM	91	* so make sure that's clear.
1da177e4	92	*/
bff06d55 DM	93	rdpr %pstate, %g1
	94	andn %g1, PSTATE_AM, %g1
	95	wrpr %g1, 0x0, %pstate
	96	ba,a,pt %xcc, 1f
	97
d82ace7d DM	98	.globl prom_finddev_name, prom_chosen_path, prom_root_node
	99	.globl prom_getprop_name, prom_mmu_name, prom_peer_name
	100	.globl prom_callmethod_name, prom_translate_name, prom_root_compatible
bff06d55 DM	101	.globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
	102	.globl prom_boot_mapped_pc, prom_boot_mapping_mode
	103	.globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
d82ace7d DM	104	.globl is_sun4v
	105	prom_peer_name:
	106	.asciz "peer"
	107	prom_compatible_name:
	108	.asciz "compatible"
bff06d55 DM	109	prom_finddev_name:
	110	.asciz "finddevice"
	111	prom_chosen_path:
	112	.asciz "/chosen"
	113	prom_getprop_name:
	114	.asciz "getprop"
	115	prom_mmu_name:
	116	.asciz "mmu"
	117	prom_callmethod_name:
	118	.asciz "call-method"
	119	prom_translate_name:
	120	.asciz "translate"
	121	prom_map_name:
	122	.asciz "map"
	123	prom_unmap_name:
	124	.asciz "unmap"
d82ace7d	125	prom_sun4v_name:
6cebb520	126	.asciz "sun4v"
bff06d55	127	.align 4
d82ace7d DM	128	prom_root_compatible:
	129	.skip 64
	130	prom_root_node:
	131	.word 0
bff06d55 DM	132	prom_mmu_ihandle_cache:
	133	.word 0
	134	prom_boot_mapped_pc:
	135	.word 0
	136	prom_boot_mapping_mode:
	137	.word 0
	138	.align 8
	139	prom_boot_mapping_phys_high:
	140	.xword 0
	141	prom_boot_mapping_phys_low:
	142	.xword 0
d82ace7d DM	143	is_sun4v:
d82ace7d DM	144	.word 0
bff06d55 DM	145	1:
bff06d55 DM	146	rd %pc, %l0
d82ace7d DM	147
	148	mov (1b - prom_peer_name), %l1
	149	sub %l0, %l1, %l1
	150	mov 0, %l2
	151
	152	/* prom_root_node = prom_peer(0) */
	153	stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
	154	mov 1, %l3
	155	stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
	156	stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
	157	stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
	158	stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
	159	call %l7
	160	add %sp, (2047 + 128), %o0 ! argument array
	161
	162	ldx [%sp + 2047 + 128 + 0x20], %l4 ! prom root node
	163	mov (1b - prom_root_node), %l1
	164	sub %l0, %l1, %l1
	165	stw %l4, [%l1]
	166
	167	mov (1b - prom_getprop_name), %l1
	168	mov (1b - prom_compatible_name), %l2
	169	mov (1b - prom_root_compatible), %l5
	170	sub %l0, %l1, %l1
	171	sub %l0, %l2, %l2
	172	sub %l0, %l5, %l5
	173
	174	/* prom_getproperty(prom_root_node, "compatible",
	175	* &prom_root_compatible, 64)
	176	*/
	177	stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
	178	mov 4, %l3
	179	stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
	180	mov 1, %l3
	181	stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
	182	stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, prom_root_node
	183	stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
	184	stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_root_compatible
	185	mov 64, %l3
	186	stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
	187	stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
	188	call %l7
	189	add %sp, (2047 + 128), %o0 ! argument array
	190
bff06d55 DM	191	mov (1b - prom_finddev_name), %l1
	192	mov (1b - prom_chosen_path), %l2
	193	mov (1b - prom_boot_mapped_pc), %l3
	194	sub %l0, %l1, %l1
	195	sub %l0, %l2, %l2
	196	sub %l0, %l3, %l3
	197	stw %l0, [%l3]
	198	sub %sp, (192 + 128), %sp
	199
	200	/* chosen_node = prom_finddevice("/chosen") */
	201	stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
	202	mov 1, %l3
	203	stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
	204	stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
	205	stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
	206	stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
	207	call %l7
	208	add %sp, (2047 + 128), %o0 ! argument array
	209
	210	ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
	211
	212	mov (1b - prom_getprop_name), %l1
	213	mov (1b - prom_mmu_name), %l2
	214	mov (1b - prom_mmu_ihandle_cache), %l5
	215	sub %l0, %l1, %l1
	216	sub %l0, %l2, %l2
	217	sub %l0, %l5, %l5
	218
	219	/* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
	220	stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
	221	mov 4, %l3
	222	stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
	223	mov 1, %l3
	224	stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
	225	stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
	226	stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
	227	stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
	228	mov 4, %l3
	229	stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
	230	stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
	231	call %l7
	232	add %sp, (2047 + 128), %o0 ! argument array
	233
	234	mov (1b - prom_callmethod_name), %l1
	235	mov (1b - prom_translate_name), %l2
	236	sub %l0, %l1, %l1
	237	sub %l0, %l2, %l2
	238	lduw [%l5], %l5 ! prom_mmu_ihandle_cache
	239
	240	stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
	241	mov 3, %l3
	242	stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
	243	mov 5, %l3
	244	stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
	245	stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
	246	stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
b1b510aa DM	247	/* PAGE align */
	248	srlx %l0, 13, %l3
	249	sllx %l3, 13, %l3
bff06d55 DM	250	stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
	251	stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
	252	stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
	253	stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
	254	stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
	255	stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
	256	call %l7
	257	add %sp, (2047 + 128), %o0 ! argument array
	258
	259	ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
	260	mov (1b - prom_boot_mapping_mode), %l4
	261	sub %l0, %l4, %l4
	262	stw %l1, [%l4]
	263	mov (1b - prom_boot_mapping_phys_high), %l4
	264	sub %l0, %l4, %l4
	265	ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
	266	stx %l2, [%l4 + 0x0]
	267	ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
b1b510aa DM	268	/* 4MB align */
	269	srlx %l3, 22, %l3
	270	sllx %l3, 22, %l3
bff06d55 DM	271	stx %l3, [%l4 + 0x8]
	272
	273	/* Leave service as-is, "call-method" */
	274	mov 7, %l3
	275	stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
	276	mov 1, %l3
a8201c61	277	stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
bff06d55 DM	278	mov (1b - prom_map_name), %l3
	279	sub %l0, %l3, %l3
	280	stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
	281	/* Leave arg2 as-is, prom_mmu_ihandle_cache */
	282	mov -1, %l3
	283	stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
	284	sethi %hi(8 * 1024 * 1024), %l3
	285	stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: size (8MB)
	286	sethi %hi(KERNBASE), %l3
	287	stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
	288	stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
	289	mov (1b - prom_boot_mapping_phys_low), %l3
	290	sub %l0, %l3, %l3
	291	ldx [%l3], %l3
	292	stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
	293	call %l7
	294	add %sp, (2047 + 128), %o0 ! argument array
	295
	296	add %sp, (192 + 128), %sp
	297
	298	sparc64_boot_after_remap:
d82ace7d DM	299	sethi %hi(prom_root_compatible), %g1
	300	or %g1, %lo(prom_root_compatible), %g1
	301	sethi %hi(prom_sun4v_name), %g7
	302	or %g7, %lo(prom_sun4v_name), %g7
6cebb520	303	mov 5, %g3
d82ace7d DM	304	1: ldub [%g7], %g2
	305	ldub [%g1], %g4
	306	cmp %g2, %g4
	307	bne,pn %icc, 2f
	308	add %g7, 1, %g7
	309	subcc %g3, 1, %g3
	310	bne,pt %xcc, 1b
	311	add %g1, 1, %g1
	312
	313	sethi %hi(is_sun4v), %g1
	314	or %g1, %lo(is_sun4v), %g1
	315	mov 1, %g7
	316	stw %g7, [%g1]
	317
	318	2:
	319	BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
1da177e4 LT	320	BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
	321	BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
	322	ba,pt %xcc, spitfire_boot
	323	nop
	324
	325	cheetah_plus_boot:
	326	/* Preserve OBP chosen DCU and DCR register settings. */
	327	ba,pt %xcc, cheetah_generic_boot
	328	nop
	329
	330	cheetah_boot:
	331	mov DCR_BPE \| DCR_RPE \| DCR_SI \| DCR_IFPOE \| DCR_MS, %g1
	332	wr %g1, %asr18
	333
	334	sethi %uhi(DCU_ME\|DCU_RE\|DCU_HPE\|DCU_SPE\|DCU_SL\|DCU_WE), %g7
	335	or %g7, %ulo(DCU_ME\|DCU_RE\|DCU_HPE\|DCU_SPE\|DCU_SL\|DCU_WE), %g7
	336	sllx %g7, 32, %g7
	337	or %g7, DCU_DM \| DCU_IM \| DCU_DC \| DCU_IC, %g7
	338	stxa %g7, [%g0] ASI_DCU_CONTROL_REG
	339	membar #Sync
	340
	341	cheetah_generic_boot:
	342	mov TSB_EXTENSION_P, %g3
	343	stxa %g0, [%g3] ASI_DMMU
	344	stxa %g0, [%g3] ASI_IMMU
	345	membar #Sync
	346
	347	mov TSB_EXTENSION_S, %g3
	348	stxa %g0, [%g3] ASI_DMMU
	349	membar #Sync
	350
	351	mov TSB_EXTENSION_N, %g3
	352	stxa %g0, [%g3] ASI_DMMU
	353	stxa %g0, [%g3] ASI_IMMU
	354	membar #Sync
	355
bff06d55	356	ba,a,pt %xcc, jump_to_sun4u_init
1da177e4 LT	357
	358	spitfire_boot:
	359	/* Typically PROM has already enabled both MMU's and both on-chip
	360	* caches, but we do it here anyway just to be paranoid.
	361	*/
	362	mov (LSU_CONTROL_IC\|LSU_CONTROL_DC\|LSU_CONTROL_IM\|LSU_CONTROL_DM), %g1
	363	stxa %g1, [%g0] ASI_LSU_CONTROL
	364	membar #Sync
	365
bff06d55	366	jump_to_sun4u_init:
1da177e4 LT	367	/*
	368	* Make sure we are in privileged mode, have address masking,
	369	* using the ordinary globals and have enabled floating
	370	* point.
	371	*
	372	* Again, typically PROM has left %pil at 13 or similar, and
	373	* (PSTATE_PRIV \| PSTATE_PEF \| PSTATE_IE) in %pstate.
	374	*/
	375	wrpr %g0, (PSTATE_PRIV\|PSTATE_PEF\|PSTATE_IE), %pstate
	376	wr %g0, 0, %fprs
	377
1da177e4 LT	378	set sun4u_init, %g2
	379	jmpl %g2 + %g0, %g0
	380	nop
	381
	382	sun4u_init:
6cebb520 DM	383	BRANCH_IF_SUN4V(g1, sun4v_init)
6cebb520 DM	384
1da177e4	385	/* Set ctx 0 */
8b11bd12	386	mov PRIMARY_CONTEXT, %g7
6cebb520	387	stxa %g0, [%g7] ASI_DMMU
8b11bd12 DM	388	membar #Sync
	389
	390	mov SECONDARY_CONTEXT, %g7
6cebb520 DM	391	stxa %g0, [%g7] ASI_DMMU
	392	membar #Sync
	393
	394	ba,pt %xcc, sun4u_continue
	395	nop
8b11bd12	396
6cebb520 DM	397	sun4v_init:
	398	/* Set ctx 0 */
	399	mov PRIMARY_CONTEXT, %g7
8b11bd12	400	stxa %g0, [%g7] ASI_MMU
6cebb520	401	membar #Sync
1da177e4	402
6cebb520 DM	403	mov SECONDARY_CONTEXT, %g7
	404	stxa %g0, [%g7] ASI_MMU
	405	membar #Sync
	406	ba,pt %xcc, niagara_tlb_fixup
	407	nop
1da177e4	408
6cebb520	409	sun4u_continue:
d82ace7d	410	BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
1da177e4 LT	411
	412	ba,pt %xcc, spitfire_tlb_fixup
	413	nop
	414
8591e302 DM	415	niagara_tlb_fixup:
	416	mov 3, %g2 /* Set TLB type to hypervisor. */
	417	sethi %hi(tlb_type), %g1
	418	stw %g2, [%g1 + %lo(tlb_type)]
	419
	420	/* Patch copy/clear ops. */
	421	call niagara_patch_copyops
	422	nop
8ca2557c DM	423	call niagara_patch_bzero
8ca2557c DM	424	nop
8591e302 DM	425	call niagara_patch_pageops
	426	nop
	427
	428	/* Patch TLB/cache ops. */
	429	call hypervisor_patch_cachetlbops
	430	nop
	431
d82ace7d DM	432	ba,pt %xcc, tlb_fixup_done
	433	nop
	434
1da177e4	435	cheetah_tlb_fixup:
1da177e4 LT	436	mov 2, %g2 /* Set TLB type to cheetah+. */
	437	BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
	438
	439	mov 1, %g2 /* Set TLB type to cheetah. */
	440
	441	1: sethi %hi(tlb_type), %g1
	442	stw %g2, [%g1 + %lo(tlb_type)]
	443
0835ae0f	444	/* Patch copy/page operations to cheetah optimized versions. */
1da177e4 LT	445	call cheetah_patch_copyops
1da177e4 LT	446	nop
dbd2fdf5 DM	447	call cheetah_patch_copy_page
dbd2fdf5 DM	448	nop
1da177e4 LT	449	call cheetah_patch_cachetlbops
	450	nop
	451
	452	ba,pt %xcc, tlb_fixup_done
	453	nop
	454
	455	spitfire_tlb_fixup:
1da177e4 LT	456	/* Set TLB type to spitfire. */
	457	mov 0, %g2
	458	sethi %hi(tlb_type), %g1
	459	stw %g2, [%g1 + %lo(tlb_type)]
	460
	461	tlb_fixup_done:
	462	sethi %hi(init_thread_union), %g6
	463	or %g6, %lo(init_thread_union), %g6
	464	ldx [%g6 + TI_TASK], %g4
	465	mov %sp, %l6
	466	mov %o4, %l7
	467
1da177e4 LT	468	wr %g0, ASI_P, %asi
	469	mov 1, %g1
	470	sllx %g1, THREAD_SHIFT, %g1
	471	sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
	472	add %g6, %g1, %sp
	473	mov 0, %fp
	474
	475	/* Set per-cpu pointer initially to zero, this makes
	476	* the boot-cpu use the in-kernel-image per-cpu areas
	477	* before setup_per_cpu_area() is invoked.
	478	*/
	479	clr %g5
	480
	481	wrpr %g0, 0, %wstate
	482	wrpr %g0, 0x0, %tl
	483
	484	/* Clear the bss */
	485	sethi %hi(__bss_start), %o0
	486	or %o0, %lo(__bss_start), %o0
	487	sethi %hi(_end), %o1
	488	or %o1, %lo(_end), %o1
	489	call __bzero
	490	sub %o1, %o0, %o1
	491
10e26723 DM	492	#ifdef CONFIG_LOCKDEP
	493	/* We have this call this super early, as even prom_init can grab
	494	* spinlocks and thus call into the lockdep code.
	495	*/
	496	call lockdep_init
	497	nop
	498	#endif
	499
1da177e4 LT	500	mov %l6, %o1 ! OpenPROM stack
	501	call prom_init
	502	mov %l7, %o0 ! OpenPROM cif handler
	503
951bc82c DM	504	/* Initialize current_thread_info()->cpu as early as possible.
	505	* In order to do that accurately we have to patch up the get_cpuid()
	506	* assembler sequences. And that, in turn, requires that we know
	507	* if we are on a Starfire box or not. While we're here, patch up
	508	* the sun4v sequences as well.
	509	*/
	510	call check_if_starfire
	511	nop
	512	call per_cpu_patch
	513	nop
	514	call sun4v_patch
	515	nop
	516
	517	#ifdef CONFIG_SMP
	518	call hard_smp_processor_id
	519	nop
	520	cmp %o0, NR_CPUS
	521	blu,pt %xcc, 1f
	522	nop
	523	call boot_cpu_id_too_large
	524	nop
	525	/* Not reached... */
	526
	527	1:
	528	#else
	529	mov 0, %o0
	530	#endif
	531	stb %o0, [%g6 + TI_CPU]
	532
1da177e4 LT	533	/* Off we go.... */
	534	call start_kernel
	535	nop
	536	/* Not reached... */
	537
5d8e1b18 DM	538	/* This is meant to allow the sharing of this code between
	539	* boot processor invocation (via setup_tba() below) and
	540	* secondary processor startup (via trampoline.S). The
	541	* former does use this code, the latter does not yet due
	542	* to some complexities. That should be fixed up at some
	543	* point.
c9c10830 DM	544	*
	545	* There used to be enormous complexity wrt. transferring
	546	* over from the firwmare's trap table to the Linux kernel's.
	547	* For example, there was a chicken & egg problem wrt. building
	548	* the OBP page tables, yet needing to be on the Linux kernel
	549	* trap table (to translate PAGE_OFFSET addresses) in order to
	550	* do that.
	551	*
	552	* We now handle OBP tlb misses differently, via linear lookups
	553	* into the prom_trans[] array. So that specific problem no
	554	* longer exists. Yet, unfortunately there are still some issues
	555	* preventing trampoline.S from using this code... ho hum.
5d8e1b18 DM	556	*/
	557	.globl setup_trap_table
	558	setup_trap_table:
	559	save %sp, -192, %sp
	560
c9c10830	561	/* Force interrupts to be disabled. */
d8573e20 DM	562	rdpr %pstate, %l0
d8573e20 DM	563	andn %l0, PSTATE_IE, %o1
5d8e1b18	564	wrpr %o1, 0x0, %pstate
d8573e20	565	rdpr %pil, %l1
5d8e1b18	566	wrpr %g0, 15, %pil
1da177e4	567
c9c10830	568	/* Make the firmware call to jump over to the Linux trap table. */
12eaa328 DM	569	sethi %hi(is_sun4v), %o0
	570	lduw [%o0 + %lo(is_sun4v)], %o0
	571	brz,pt %o0, 1f
	572	nop
	573
	574	TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
	575	add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
	576	stxa %g2, [%g0] ASI_SCRATCHPAD
	577
	578	/* Compute physical address:
	579	*
	580	* paddr = kern_base + (mmfsa_vaddr - KERNBASE)
	581	*/
	582	sethi %hi(KERNBASE), %g3
	583	sub %g2, %g3, %g2
	584	sethi %hi(kern_base), %g3
	585	ldx [%g3 + %lo(kern_base)], %g3
	586	add %g2, %g3, %o1
	587
	588	call prom_set_trap_table_sun4v
	589	sethi %hi(sparc64_ttable_tl0), %o0
	590
	591	ba,pt %xcc, 2f
	592	nop
	593
	594	1: call prom_set_trap_table
5d8e1b18 DM	595	sethi %hi(sparc64_ttable_tl0), %o0
	596
	597	/* Start using proper page size encodings in ctx register. */
12eaa328	598	2: sethi %hi(sparc64_kern_pri_context), %g3
5d8e1b18	599	ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
8b11bd12 DM	600
	601	mov PRIMARY_CONTEXT, %g1
	602
	603	661: stxa %g2, [%g1] ASI_DMMU
	604	.section .sun4v_1insn_patch, "ax"
	605	.word 661b
	606	stxa %g2, [%g1] ASI_MMU
	607	.previous
	608
5d8e1b18 DM	609	membar #Sync
5d8e1b18 DM	610
1da177e4 LT	611	/* Kill PROM timer */
	612	sethi %hi(0x80000000), %o2
	613	sllx %o2, 32, %o2
	614	wr %o2, 0, %tick_cmpr
	615
d82ace7d DM	616	BRANCH_IF_SUN4V(o2, 1f)
d82ace7d DM	617	BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
1da177e4 LT	618
	619	ba,pt %xcc, 2f
	620	nop
	621
	622	/* Disable STICK_INT interrupts. */
	623	1:
	624	sethi %hi(0x80000000), %o2
	625	sllx %o2, 32, %o2
	626	wr %o2, %asr25
	627
1da177e4 LT	628	2:
1da177e4 LT	629	wrpr %g0, %g0, %wstate
1da177e4 LT	630
	631	call init_irqwork_curcpu
	632	nop
	633
d8573e20 DM	634	/* Now we can restore interrupt state. */
	635	wrpr %l0, 0, %pstate
	636	wrpr %l1, 0x0, %pil
5d8e1b18 DM	637
	638	ret
	639	restore
	640
	641	.globl setup_tba
a8b900d8	642	setup_tba:
5d8e1b18 DM	643	save %sp, -192, %sp
	644
	645	/* The boot processor is the only cpu which invokes this
	646	* routine, the other cpus set things up via trampoline.S.
	647	* So save the OBP trap table address here.
	648	*/
	649	rdpr %tba, %g7
	650	sethi %hi(prom_tba), %o1
	651	or %o1, %lo(prom_tba), %o1
	652	stx %g7, [%o1]
	653
	654	call setup_trap_table
	655	nop
1da177e4 LT	656
	657	ret
	658	restore
c9c10830 DM	659	sparc64_boot_end:
c9c10830 DM	660
c9c10830	661	#include "ktlb.S"
74bf4312	662	#include "tsb.S"
c9c10830 DM	663	#include "etrap.S"
	664	#include "rtrap.S"
	665	#include "winfixup.S"
	666	#include "entry.S"
5b0c0572 DM	667	#include "sun4v_tlb_miss.S"
5b0c0572 DM	668	#include "sun4v_ivec.S"
1da177e4 LT	669
1da177e4 LT	670	/*
c9c10830	671	* The following skip makes sure the trap table in ttable.S is aligned
1da177e4	672	* on a 32K boundary as required by the v9 specs for TBA register.
2f7ee7c6 DM	673	*
	674	* We align to a 32K boundary, then we have the 32K kernel TSB,
	675	* then the 32K aligned trap table.
1da177e4	676	*/
c9c10830 DM	677	1:
c9c10830 DM	678	.skip 0x4000 + _start - 1b
1da177e4	679
2f7ee7c6 DM	680	.globl swapper_tsb
	681	swapper_tsb:
	682	.skip (32 * 1024)
1da177e4 LT	683
	684	! 0x0000000000408000
	685
	686	#include "ttable.S"
1da177e4	687
074d82cf DM	688	#include "systbls.S"
074d82cf DM	689
1da177e4 LT	690	.data
	691	.align 8
	692	.globl prom_tba, tlb_type
	693	prom_tba: .xword 0
	694	tlb_type: .word 0 /* Must NOT end up in BSS */
	695	.section ".fixup",#alloc,#execinstr
5fd29752 DM	696
5fd29752 DM	697	.globl __ret_efault, __retl_efault
1da177e4 LT	698	__ret_efault:
	699	ret
	700	restore %g0, -EFAULT, %o0
5fd29752 DM	701	__retl_efault:
	702	retl
	703	mov -EFAULT, %o0