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[linux-2.6-block.git] / arch / sparc64 / kernel / head.S
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1da177e4
LT		 1/* $Id: head.S,v 1.87 2002/02/09 19:49:31 davem Exp $
2 * head.S: Initial boot code for the Sparc64 port of Linux.
3 *
4 * Copyright (C) 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
6 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 */
9
10#include <linux/config.h>
11#include <linux/version.h>
12#include <linux/errno.h>
13#include <asm/thread_info.h>
14#include <asm/asi.h>
15#include <asm/pstate.h>
16#include <asm/ptrace.h>
17#include <asm/spitfire.h>
18#include <asm/page.h>
19#include <asm/pgtable.h>
20#include <asm/errno.h>
21#include <asm/signal.h>
22#include <asm/processor.h>
23#include <asm/lsu.h>
24#include <asm/dcr.h>
25#include <asm/dcu.h>
26#include <asm/head.h>
27#include <asm/ttable.h>
28#include <asm/mmu.h>
29
30/* This section from from _start to sparc64_boot_end should fit into
c9c10830 31 * 0x0000000000404000 to 0x0000000000408000.
1da177e4 32 */
1da177e4
LT		 33 .text
34 .globl start, _start, stext, _stext
35_start:
36start:
37_stext:
38stext:
1da177e4
LT		 39! 0x0000000000404000
40 b sparc64_boot
41 flushw /* Flush register file. */
42
43/* This stuff has to be in sync with SILO and other potential boot loaders
44 * Fields should be kept upward compatible and whenever any change is made,
45 * HdrS version should be incremented.
46 */
47 .global root_flags, ram_flags, root_dev
48 .global sparc_ramdisk_image, sparc_ramdisk_size
49 .global sparc_ramdisk_image64
50
51 .ascii "HdrS"
52 .word LINUX_VERSION_CODE
53
54 /* History:
55 *
56 * 0x0300 : Supports being located at other than 0x4000
57 * 0x0202 : Supports kernel params string
58 * 0x0201 : Supports reboot_command
59 */
60 .half 0x0301 /* HdrS version */
61
62root_flags:
63 .half 1
64root_dev:
65 .half 0
66ram_flags:
67 .half 0
68sparc_ramdisk_image:
69 .word 0
70sparc_ramdisk_size:
71 .word 0
72 .xword reboot_command
73 .xword bootstr_info
74sparc_ramdisk_image64:
75 .xword 0
76 .word _end
77
bff06d55
DM		 78 /* PROM cif handler code address is in %o4. */
79sparc64_boot:
801: rd %pc, %g7
81 set 1b, %g1
82 cmp %g1, %g7
83 be,pn %xcc, sparc64_boot_after_remap
84 mov %o4, %l7
85
86 /* We need to remap the kernel. Use position independant
87 * code to remap us to KERNBASE.
1da177e4 88 *
bff06d55
DM		 89 * SILO can invoke us with 32-bit address masking enabled,
90 * so make sure that's clear.
1da177e4 91 */
bff06d55
DM		 92 rdpr %pstate, %g1
93 andn %g1, PSTATE_AM, %g1
94 wrpr %g1, 0x0, %pstate
95 ba,a,pt %xcc, 1f
96
97 .globl prom_finddev_name, prom_chosen_path
98 .globl prom_getprop_name, prom_mmu_name
99 .globl prom_callmethod_name, prom_translate_name
100 .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
101 .globl prom_boot_mapped_pc, prom_boot_mapping_mode
102 .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
103prom_finddev_name:
104 .asciz "finddevice"
105prom_chosen_path:
106 .asciz "/chosen"
107prom_getprop_name:
108 .asciz "getprop"
109prom_mmu_name:
110 .asciz "mmu"
111prom_callmethod_name:
112 .asciz "call-method"
113prom_translate_name:
114 .asciz "translate"
115prom_map_name:
116 .asciz "map"
117prom_unmap_name:
118 .asciz "unmap"
119 .align 4
120prom_mmu_ihandle_cache:
121 .word 0
122prom_boot_mapped_pc:
123 .word 0
124prom_boot_mapping_mode:
125 .word 0
126 .align 8
127prom_boot_mapping_phys_high:
128 .xword 0
129prom_boot_mapping_phys_low:
130 .xword 0
1311:
132 rd %pc, %l0
133 mov (1b - prom_finddev_name), %l1
134 mov (1b - prom_chosen_path), %l2
135 mov (1b - prom_boot_mapped_pc), %l3
136 sub %l0, %l1, %l1
137 sub %l0, %l2, %l2
138 sub %l0, %l3, %l3
139 stw %l0, [%l3]
140 sub %sp, (192 + 128), %sp
141
142 /* chosen_node = prom_finddevice("/chosen") */
143 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
144 mov 1, %l3
145 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
146 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
147 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
148 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
149 call %l7
150 add %sp, (2047 + 128), %o0 ! argument array
151
152 ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
153
154 mov (1b - prom_getprop_name), %l1
155 mov (1b - prom_mmu_name), %l2
156 mov (1b - prom_mmu_ihandle_cache), %l5
157 sub %l0, %l1, %l1
158 sub %l0, %l2, %l2
159 sub %l0, %l5, %l5
160
161 /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
162 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
163 mov 4, %l3
164 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
165 mov 1, %l3
166 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
167 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
168 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
169 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
170 mov 4, %l3
171 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
172 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
173 call %l7
174 add %sp, (2047 + 128), %o0 ! argument array
175
176 mov (1b - prom_callmethod_name), %l1
177 mov (1b - prom_translate_name), %l2
178 sub %l0, %l1, %l1
179 sub %l0, %l2, %l2
180 lduw [%l5], %l5 ! prom_mmu_ihandle_cache
181
182 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
183 mov 3, %l3
184 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
185 mov 5, %l3
186 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
187 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
188 stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
b1b510aa
DM		 189 /* PAGE align */
190 srlx %l0, 13, %l3
191 sllx %l3, 13, %l3
bff06d55
DM		 192 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
193 stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
194 stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
195 stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
196 stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
197 stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
198 call %l7
199 add %sp, (2047 + 128), %o0 ! argument array
200
201 ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
202 mov (1b - prom_boot_mapping_mode), %l4
203 sub %l0, %l4, %l4
204 stw %l1, [%l4]
205 mov (1b - prom_boot_mapping_phys_high), %l4
206 sub %l0, %l4, %l4
207 ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
208 stx %l2, [%l4 + 0x0]
209 ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
b1b510aa
DM		 210 /* 4MB align */
211 srlx %l3, 22, %l3
212 sllx %l3, 22, %l3
bff06d55
DM		 213 stx %l3, [%l4 + 0x8]
214
215 /* Leave service as-is, "call-method" */
216 mov 7, %l3
217 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
218 mov 1, %l3
a8201c61 219 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
bff06d55
DM		 220 mov (1b - prom_map_name), %l3
221 sub %l0, %l3, %l3
222 stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
223 /* Leave arg2 as-is, prom_mmu_ihandle_cache */
224 mov -1, %l3
225 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
226 sethi %hi(8 * 1024 * 1024), %l3
227 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: size (8MB)
228 sethi %hi(KERNBASE), %l3
229 stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
230 stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
231 mov (1b - prom_boot_mapping_phys_low), %l3
232 sub %l0, %l3, %l3
233 ldx [%l3], %l3
234 stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
235 call %l7
236 add %sp, (2047 + 128), %o0 ! argument array
237
238 add %sp, (192 + 128), %sp
239
240sparc64_boot_after_remap:
1da177e4
LT		 241 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
242 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
243 ba,pt %xcc, spitfire_boot
244 nop
245
246cheetah_plus_boot:
247 /* Preserve OBP chosen DCU and DCR register settings. */
248 ba,pt %xcc, cheetah_generic_boot
249 nop
250
251cheetah_boot:
252 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
253 wr %g1, %asr18
254
255 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
256 or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
257 sllx %g7, 32, %g7
258 or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
259 stxa %g7, [%g0] ASI_DCU_CONTROL_REG
260 membar #Sync
261
262cheetah_generic_boot:
263 mov TSB_EXTENSION_P, %g3
264 stxa %g0, [%g3] ASI_DMMU
265 stxa %g0, [%g3] ASI_IMMU
266 membar #Sync
267
268 mov TSB_EXTENSION_S, %g3
269 stxa %g0, [%g3] ASI_DMMU
270 membar #Sync
271
272 mov TSB_EXTENSION_N, %g3
273 stxa %g0, [%g3] ASI_DMMU
274 stxa %g0, [%g3] ASI_IMMU
275 membar #Sync
276
bff06d55 277 ba,a,pt %xcc, jump_to_sun4u_init
1da177e4
LT		 278
279spitfire_boot:
280 /* Typically PROM has already enabled both MMU's and both on-chip
281 * caches, but we do it here anyway just to be paranoid.
282 */
283 mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
284 stxa %g1, [%g0] ASI_LSU_CONTROL
285 membar #Sync
286
bff06d55 287jump_to_sun4u_init:
1da177e4
LT		 288 /*
289 * Make sure we are in privileged mode, have address masking,
290 * using the ordinary globals and have enabled floating
291 * point.
292 *
293 * Again, typically PROM has left %pil at 13 or similar, and
294 * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
295 */
296 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
297 wr %g0, 0, %fprs
298
1da177e4
LT		 299 set sun4u_init, %g2
300 jmpl %g2 + %g0, %g0
301 nop
302
303sun4u_init:
304 /* Set ctx 0 */
305 mov PRIMARY_CONTEXT, %g7
306 stxa %g0, [%g7] ASI_DMMU
307 membar #Sync
308
309 mov SECONDARY_CONTEXT, %g7
310 stxa %g0, [%g7] ASI_DMMU
311 membar #Sync
312
1da177e4
LT		 313 BRANCH_IF_ANY_CHEETAH(g1,g7,cheetah_tlb_fixup)
314
315 ba,pt %xcc, spitfire_tlb_fixup
316 nop
317
318cheetah_tlb_fixup:
1da177e4
LT		 319 mov 2, %g2 /* Set TLB type to cheetah+. */
320 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
321
322 mov 1, %g2 /* Set TLB type to cheetah. */
323
3241: sethi %hi(tlb_type), %g1
325 stw %g2, [%g1 + %lo(tlb_type)]
326
0835ae0f 327 /* Patch copy/page operations to cheetah optimized versions. */
1da177e4
LT		 328 call cheetah_patch_copyops
329 nop
dbd2fdf5
DM		 330 call cheetah_patch_copy_page
331 nop
1da177e4
LT		 332 call cheetah_patch_cachetlbops
333 nop
334
335 ba,pt %xcc, tlb_fixup_done
336 nop
337
338spitfire_tlb_fixup:
1da177e4
LT		 339 /* Set TLB type to spitfire. */
340 mov 0, %g2
341 sethi %hi(tlb_type), %g1
342 stw %g2, [%g1 + %lo(tlb_type)]
343
344tlb_fixup_done:
345 sethi %hi(init_thread_union), %g6
346 or %g6, %lo(init_thread_union), %g6
347 ldx [%g6 + TI_TASK], %g4
348 mov %sp, %l6
349 mov %o4, %l7
350
1da177e4
LT		 351 wr %g0, ASI_P, %asi
352 mov 1, %g1
353 sllx %g1, THREAD_SHIFT, %g1
354 sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
355 add %g6, %g1, %sp
356 mov 0, %fp
357
358 /* Set per-cpu pointer initially to zero, this makes
359 * the boot-cpu use the in-kernel-image per-cpu areas
360 * before setup_per_cpu_area() is invoked.
361 */
362 clr %g5
363
364 wrpr %g0, 0, %wstate
365 wrpr %g0, 0x0, %tl
366
367 /* Clear the bss */
368 sethi %hi(__bss_start), %o0
369 or %o0, %lo(__bss_start), %o0
370 sethi %hi(_end), %o1
371 or %o1, %lo(_end), %o1
372 call __bzero
373 sub %o1, %o0, %o1
374
375 mov %l6, %o1 ! OpenPROM stack
376 call prom_init
377 mov %l7, %o0 ! OpenPROM cif handler
378
379 /* Off we go.... */
380 call start_kernel
381 nop
382 /* Not reached... */
383
5d8e1b18
DM		 384 /* This is meant to allow the sharing of this code between
385 * boot processor invocation (via setup_tba() below) and
386 * secondary processor startup (via trampoline.S). The
387 * former does use this code, the latter does not yet due
388 * to some complexities. That should be fixed up at some
389 * point.
c9c10830
DM		 390 *
391 * There used to be enormous complexity wrt. transferring
392 * over from the firwmare's trap table to the Linux kernel's.
393 * For example, there was a chicken & egg problem wrt. building
394 * the OBP page tables, yet needing to be on the Linux kernel
395 * trap table (to translate PAGE_OFFSET addresses) in order to
396 * do that.
397 *
398 * We now handle OBP tlb misses differently, via linear lookups
399 * into the prom_trans[] array. So that specific problem no
400 * longer exists. Yet, unfortunately there are still some issues
401 * preventing trampoline.S from using this code... ho hum.
5d8e1b18
DM		 402 */
403 .globl setup_trap_table
404setup_trap_table:
405 save %sp, -192, %sp
406
c9c10830 407 /* Force interrupts to be disabled. */
5d8e1b18
DM		 408 rdpr %pstate, %o1
409 andn %o1, PSTATE_IE, %o1
410 wrpr %o1, 0x0, %pstate
411 wrpr %g0, 15, %pil
1da177e4 412
c9c10830 413 /* Make the firmware call to jump over to the Linux trap table. */
5d8e1b18
DM		 414 call prom_set_trap_table
415 sethi %hi(sparc64_ttable_tl0), %o0
416
417 /* Start using proper page size encodings in ctx register. */
418 sethi %hi(sparc64_kern_pri_context), %g3
419 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
420 mov PRIMARY_CONTEXT, %g1
421 stxa %g2, [%g1] ASI_DMMU
422 membar #Sync
423
424 /* The Linux trap handlers expect various trap global registers
425 * to be setup with some fixed values. So here we set these
426 * up very carefully. These globals are:
427 *
428 * Alternate Globals (PSTATE_AG):
429 *
430 * %g6 --> current_thread_info()
431 *
5d8e1b18
DM		 432 * Interrupt Globals (PSTATE_IG, setup by init_irqwork_curcpu()):
433 *
434 * %g6 --> __irq_work[smp_processor_id()]
435 */
1da177e4 436
1da177e4
LT		 437 rdpr %pstate, %o1
438 mov %g6, %o2
5d8e1b18 439 wrpr %o1, PSTATE_AG, %pstate
1da177e4
LT		 440 mov %o2, %g6
441
1da177e4
LT		 442 /* Kill PROM timer */
443 sethi %hi(0x80000000), %o2
444 sllx %o2, 32, %o2
445 wr %o2, 0, %tick_cmpr
446
447 BRANCH_IF_ANY_CHEETAH(o2,o3,1f)
448
449 ba,pt %xcc, 2f
450 nop
451
452 /* Disable STICK_INT interrupts. */
4531:
454 sethi %hi(0x80000000), %o2
455 sllx %o2, 32, %o2
456 wr %o2, %asr25
457
1da177e4
LT		 4582:
459 wrpr %g0, %g0, %wstate
5d8e1b18 460 wrpr %o1, 0x0, %pstate
1da177e4
LT		 461
462 call init_irqwork_curcpu
463 nop
464
5d8e1b18 465 /* Now we can turn interrupts back on. */
1da177e4
LT		 466 rdpr %pstate, %o1
467 or %o1, PSTATE_IE, %o1
468 wrpr %o1, 0, %pstate
5d8e1b18
DM		 469 wrpr %g0, 0x0, %pil
470
471 ret
472 restore
473
474 .globl setup_tba
475setup_tba: /* i0 = is_starfire */
476 save %sp, -192, %sp
477
478 /* The boot processor is the only cpu which invokes this
479 * routine, the other cpus set things up via trampoline.S.
480 * So save the OBP trap table address here.
481 */
482 rdpr %tba, %g7
483 sethi %hi(prom_tba), %o1
484 or %o1, %lo(prom_tba), %o1
485 stx %g7, [%o1]
486
487 call setup_trap_table
488 nop
1da177e4
LT		 489
490 ret
491 restore
c9c10830
DM		 492sparc64_boot_end:
493
494#include "systbls.S"
495#include "ktlb.S"
74bf4312 496#include "tsb.S"
c9c10830
DM		 497#include "etrap.S"
498#include "rtrap.S"
499#include "winfixup.S"
500#include "entry.S"
1da177e4
LT		 501
502/*
c9c10830 503 * The following skip makes sure the trap table in ttable.S is aligned
1da177e4
LT		 504 * on a 32K boundary as required by the v9 specs for TBA register.
505 */
c9c10830
DM		 5061:
507 .skip 0x4000 + _start - 1b
1da177e4
LT		 508
509#ifdef CONFIG_SBUS
510/* This is just a hack to fool make depend config.h discovering
511 strategy: As the .S files below need config.h, but
512 make depend does not find it for them, we include config.h
513 in head.S */
514#endif
515
516! 0x0000000000408000
517
518#include "ttable.S"
1da177e4
LT		 519
520 .data
521 .align 8
522 .globl prom_tba, tlb_type
523prom_tba: .xword 0
524tlb_type: .word 0 /* Must NOT end up in BSS */
525 .section ".fixup",#alloc,#execinstr
5fd29752
DM		 526
527 .globl __ret_efault, __retl_efault
1da177e4
LT		 528__ret_efault:
529 ret
530 restore %g0, -EFAULT, %o0
5fd29752
DM		 531__retl_efault:
532 retl
533 mov -EFAULT, %o0
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