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1da177e4 LT |
1 | /* $Id: head.S,v 1.87 2002/02/09 19:49:31 davem Exp $ |
2 | * head.S: Initial boot code for the Sparc64 port of Linux. | |
3 | * | |
4 | * Copyright (C) 1996,1997 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au) | |
6 | * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
7 | * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx) | |
8 | */ | |
9 | ||
10 | #include <linux/config.h> | |
11 | #include <linux/version.h> | |
12 | #include <linux/errno.h> | |
13 | #include <asm/thread_info.h> | |
14 | #include <asm/asi.h> | |
15 | #include <asm/pstate.h> | |
16 | #include <asm/ptrace.h> | |
17 | #include <asm/spitfire.h> | |
18 | #include <asm/page.h> | |
19 | #include <asm/pgtable.h> | |
20 | #include <asm/errno.h> | |
21 | #include <asm/signal.h> | |
22 | #include <asm/processor.h> | |
23 | #include <asm/lsu.h> | |
24 | #include <asm/dcr.h> | |
25 | #include <asm/dcu.h> | |
26 | #include <asm/head.h> | |
27 | #include <asm/ttable.h> | |
28 | #include <asm/mmu.h> | |
56fb4df6 | 29 | #include <asm/cpudata.h> |
1da177e4 LT |
30 | |
31 | /* This section from from _start to sparc64_boot_end should fit into | |
c9c10830 | 32 | * 0x0000000000404000 to 0x0000000000408000. |
1da177e4 | 33 | */ |
1da177e4 LT |
34 | .text |
35 | .globl start, _start, stext, _stext | |
36 | _start: | |
37 | start: | |
38 | _stext: | |
39 | stext: | |
1da177e4 LT |
40 | ! 0x0000000000404000 |
41 | b sparc64_boot | |
42 | flushw /* Flush register file. */ | |
43 | ||
44 | /* This stuff has to be in sync with SILO and other potential boot loaders | |
45 | * Fields should be kept upward compatible and whenever any change is made, | |
46 | * HdrS version should be incremented. | |
47 | */ | |
48 | .global root_flags, ram_flags, root_dev | |
49 | .global sparc_ramdisk_image, sparc_ramdisk_size | |
50 | .global sparc_ramdisk_image64 | |
51 | ||
52 | .ascii "HdrS" | |
53 | .word LINUX_VERSION_CODE | |
54 | ||
55 | /* History: | |
56 | * | |
57 | * 0x0300 : Supports being located at other than 0x4000 | |
58 | * 0x0202 : Supports kernel params string | |
59 | * 0x0201 : Supports reboot_command | |
60 | */ | |
61 | .half 0x0301 /* HdrS version */ | |
62 | ||
63 | root_flags: | |
64 | .half 1 | |
65 | root_dev: | |
66 | .half 0 | |
67 | ram_flags: | |
68 | .half 0 | |
69 | sparc_ramdisk_image: | |
70 | .word 0 | |
71 | sparc_ramdisk_size: | |
72 | .word 0 | |
73 | .xword reboot_command | |
74 | .xword bootstr_info | |
75 | sparc_ramdisk_image64: | |
76 | .xword 0 | |
77 | .word _end | |
78 | ||
bff06d55 DM |
79 | /* PROM cif handler code address is in %o4. */ |
80 | sparc64_boot: | |
81 | 1: rd %pc, %g7 | |
82 | set 1b, %g1 | |
83 | cmp %g1, %g7 | |
84 | be,pn %xcc, sparc64_boot_after_remap | |
85 | mov %o4, %l7 | |
86 | ||
87 | /* We need to remap the kernel. Use position independant | |
88 | * code to remap us to KERNBASE. | |
1da177e4 | 89 | * |
bff06d55 DM |
90 | * SILO can invoke us with 32-bit address masking enabled, |
91 | * so make sure that's clear. | |
1da177e4 | 92 | */ |
bff06d55 DM |
93 | rdpr %pstate, %g1 |
94 | andn %g1, PSTATE_AM, %g1 | |
95 | wrpr %g1, 0x0, %pstate | |
96 | ba,a,pt %xcc, 1f | |
97 | ||
98 | .globl prom_finddev_name, prom_chosen_path | |
99 | .globl prom_getprop_name, prom_mmu_name | |
100 | .globl prom_callmethod_name, prom_translate_name | |
101 | .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache | |
102 | .globl prom_boot_mapped_pc, prom_boot_mapping_mode | |
103 | .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low | |
104 | prom_finddev_name: | |
105 | .asciz "finddevice" | |
106 | prom_chosen_path: | |
107 | .asciz "/chosen" | |
108 | prom_getprop_name: | |
109 | .asciz "getprop" | |
110 | prom_mmu_name: | |
111 | .asciz "mmu" | |
112 | prom_callmethod_name: | |
113 | .asciz "call-method" | |
114 | prom_translate_name: | |
115 | .asciz "translate" | |
116 | prom_map_name: | |
117 | .asciz "map" | |
118 | prom_unmap_name: | |
119 | .asciz "unmap" | |
120 | .align 4 | |
121 | prom_mmu_ihandle_cache: | |
122 | .word 0 | |
123 | prom_boot_mapped_pc: | |
124 | .word 0 | |
125 | prom_boot_mapping_mode: | |
126 | .word 0 | |
127 | .align 8 | |
128 | prom_boot_mapping_phys_high: | |
129 | .xword 0 | |
130 | prom_boot_mapping_phys_low: | |
131 | .xword 0 | |
132 | 1: | |
133 | rd %pc, %l0 | |
134 | mov (1b - prom_finddev_name), %l1 | |
135 | mov (1b - prom_chosen_path), %l2 | |
136 | mov (1b - prom_boot_mapped_pc), %l3 | |
137 | sub %l0, %l1, %l1 | |
138 | sub %l0, %l2, %l2 | |
139 | sub %l0, %l3, %l3 | |
140 | stw %l0, [%l3] | |
141 | sub %sp, (192 + 128), %sp | |
142 | ||
143 | /* chosen_node = prom_finddevice("/chosen") */ | |
144 | stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice" | |
145 | mov 1, %l3 | |
146 | stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1 | |
147 | stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1 | |
148 | stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen" | |
149 | stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1 | |
150 | call %l7 | |
151 | add %sp, (2047 + 128), %o0 ! argument array | |
152 | ||
153 | ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node | |
154 | ||
155 | mov (1b - prom_getprop_name), %l1 | |
156 | mov (1b - prom_mmu_name), %l2 | |
157 | mov (1b - prom_mmu_ihandle_cache), %l5 | |
158 | sub %l0, %l1, %l1 | |
159 | sub %l0, %l2, %l2 | |
160 | sub %l0, %l5, %l5 | |
161 | ||
162 | /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */ | |
163 | stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop" | |
164 | mov 4, %l3 | |
165 | stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4 | |
166 | mov 1, %l3 | |
167 | stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1 | |
168 | stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node | |
169 | stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu" | |
170 | stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache | |
171 | mov 4, %l3 | |
172 | stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3) | |
173 | stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1 | |
174 | call %l7 | |
175 | add %sp, (2047 + 128), %o0 ! argument array | |
176 | ||
177 | mov (1b - prom_callmethod_name), %l1 | |
178 | mov (1b - prom_translate_name), %l2 | |
179 | sub %l0, %l1, %l1 | |
180 | sub %l0, %l2, %l2 | |
181 | lduw [%l5], %l5 ! prom_mmu_ihandle_cache | |
182 | ||
183 | stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method" | |
184 | mov 3, %l3 | |
185 | stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3 | |
186 | mov 5, %l3 | |
187 | stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5 | |
188 | stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate" | |
189 | stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache | |
b1b510aa DM |
190 | /* PAGE align */ |
191 | srlx %l0, 13, %l3 | |
192 | sllx %l3, 13, %l3 | |
bff06d55 DM |
193 | stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC |
194 | stx %g0, [%sp + 2047 + 128 + 0x30] ! res1 | |
195 | stx %g0, [%sp + 2047 + 128 + 0x38] ! res2 | |
196 | stx %g0, [%sp + 2047 + 128 + 0x40] ! res3 | |
197 | stx %g0, [%sp + 2047 + 128 + 0x48] ! res4 | |
198 | stx %g0, [%sp + 2047 + 128 + 0x50] ! res5 | |
199 | call %l7 | |
200 | add %sp, (2047 + 128), %o0 ! argument array | |
201 | ||
202 | ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode | |
203 | mov (1b - prom_boot_mapping_mode), %l4 | |
204 | sub %l0, %l4, %l4 | |
205 | stw %l1, [%l4] | |
206 | mov (1b - prom_boot_mapping_phys_high), %l4 | |
207 | sub %l0, %l4, %l4 | |
208 | ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high | |
209 | stx %l2, [%l4 + 0x0] | |
210 | ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low | |
b1b510aa DM |
211 | /* 4MB align */ |
212 | srlx %l3, 22, %l3 | |
213 | sllx %l3, 22, %l3 | |
bff06d55 DM |
214 | stx %l3, [%l4 + 0x8] |
215 | ||
216 | /* Leave service as-is, "call-method" */ | |
217 | mov 7, %l3 | |
218 | stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7 | |
219 | mov 1, %l3 | |
a8201c61 | 220 | stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1 |
bff06d55 DM |
221 | mov (1b - prom_map_name), %l3 |
222 | sub %l0, %l3, %l3 | |
223 | stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map" | |
224 | /* Leave arg2 as-is, prom_mmu_ihandle_cache */ | |
225 | mov -1, %l3 | |
226 | stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default) | |
227 | sethi %hi(8 * 1024 * 1024), %l3 | |
228 | stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: size (8MB) | |
229 | sethi %hi(KERNBASE), %l3 | |
230 | stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE) | |
231 | stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty | |
232 | mov (1b - prom_boot_mapping_phys_low), %l3 | |
233 | sub %l0, %l3, %l3 | |
234 | ldx [%l3], %l3 | |
235 | stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr | |
236 | call %l7 | |
237 | add %sp, (2047 + 128), %o0 ! argument array | |
238 | ||
239 | add %sp, (192 + 128), %sp | |
240 | ||
241 | sparc64_boot_after_remap: | |
1da177e4 LT |
242 | BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot) |
243 | BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot) | |
244 | ba,pt %xcc, spitfire_boot | |
245 | nop | |
246 | ||
247 | cheetah_plus_boot: | |
248 | /* Preserve OBP chosen DCU and DCR register settings. */ | |
249 | ba,pt %xcc, cheetah_generic_boot | |
250 | nop | |
251 | ||
252 | cheetah_boot: | |
253 | mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1 | |
254 | wr %g1, %asr18 | |
255 | ||
256 | sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7 | |
257 | or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7 | |
258 | sllx %g7, 32, %g7 | |
259 | or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7 | |
260 | stxa %g7, [%g0] ASI_DCU_CONTROL_REG | |
261 | membar #Sync | |
262 | ||
263 | cheetah_generic_boot: | |
264 | mov TSB_EXTENSION_P, %g3 | |
265 | stxa %g0, [%g3] ASI_DMMU | |
266 | stxa %g0, [%g3] ASI_IMMU | |
267 | membar #Sync | |
268 | ||
269 | mov TSB_EXTENSION_S, %g3 | |
270 | stxa %g0, [%g3] ASI_DMMU | |
271 | membar #Sync | |
272 | ||
273 | mov TSB_EXTENSION_N, %g3 | |
274 | stxa %g0, [%g3] ASI_DMMU | |
275 | stxa %g0, [%g3] ASI_IMMU | |
276 | membar #Sync | |
277 | ||
bff06d55 | 278 | ba,a,pt %xcc, jump_to_sun4u_init |
1da177e4 LT |
279 | |
280 | spitfire_boot: | |
281 | /* Typically PROM has already enabled both MMU's and both on-chip | |
282 | * caches, but we do it here anyway just to be paranoid. | |
283 | */ | |
284 | mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1 | |
285 | stxa %g1, [%g0] ASI_LSU_CONTROL | |
286 | membar #Sync | |
287 | ||
bff06d55 | 288 | jump_to_sun4u_init: |
1da177e4 LT |
289 | /* |
290 | * Make sure we are in privileged mode, have address masking, | |
291 | * using the ordinary globals and have enabled floating | |
292 | * point. | |
293 | * | |
294 | * Again, typically PROM has left %pil at 13 or similar, and | |
295 | * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate. | |
296 | */ | |
297 | wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate | |
298 | wr %g0, 0, %fprs | |
299 | ||
1da177e4 LT |
300 | set sun4u_init, %g2 |
301 | jmpl %g2 + %g0, %g0 | |
302 | nop | |
303 | ||
304 | sun4u_init: | |
305 | /* Set ctx 0 */ | |
8b11bd12 DM |
306 | mov PRIMARY_CONTEXT, %g7 |
307 | ||
308 | 661: stxa %g0, [%g7] ASI_DMMU | |
309 | .section .sun4v_1insn_patch, "ax" | |
310 | .word 661b | |
311 | stxa %g0, [%g7] ASI_MMU | |
312 | .previous | |
313 | ||
314 | membar #Sync | |
315 | ||
316 | mov SECONDARY_CONTEXT, %g7 | |
317 | ||
318 | 661: stxa %g0, [%g7] ASI_DMMU | |
319 | .section .sun4v_1insn_patch, "ax" | |
320 | .word 661b | |
321 | stxa %g0, [%g7] ASI_MMU | |
322 | .previous | |
1da177e4 | 323 | |
1da177e4 LT |
324 | membar #Sync |
325 | ||
1da177e4 LT |
326 | BRANCH_IF_ANY_CHEETAH(g1,g7,cheetah_tlb_fixup) |
327 | ||
328 | ba,pt %xcc, spitfire_tlb_fixup | |
329 | nop | |
330 | ||
8591e302 DM |
331 | /* XXX Nothing branches to here yet, when %ver register indicates |
332 | * XXX Niagara we should do this. | |
333 | */ | |
334 | niagara_tlb_fixup: | |
335 | mov 3, %g2 /* Set TLB type to hypervisor. */ | |
336 | sethi %hi(tlb_type), %g1 | |
337 | stw %g2, [%g1 + %lo(tlb_type)] | |
338 | ||
339 | /* Patch copy/clear ops. */ | |
340 | call niagara_patch_copyops | |
341 | nop | |
342 | call niagara_patch_pageops | |
343 | nop | |
344 | ||
345 | /* Patch TLB/cache ops. */ | |
346 | call hypervisor_patch_cachetlbops | |
347 | nop | |
348 | ||
1da177e4 | 349 | cheetah_tlb_fixup: |
1da177e4 LT |
350 | mov 2, %g2 /* Set TLB type to cheetah+. */ |
351 | BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f) | |
352 | ||
353 | mov 1, %g2 /* Set TLB type to cheetah. */ | |
354 | ||
355 | 1: sethi %hi(tlb_type), %g1 | |
356 | stw %g2, [%g1 + %lo(tlb_type)] | |
357 | ||
0835ae0f | 358 | /* Patch copy/page operations to cheetah optimized versions. */ |
1da177e4 LT |
359 | call cheetah_patch_copyops |
360 | nop | |
dbd2fdf5 DM |
361 | call cheetah_patch_copy_page |
362 | nop | |
1da177e4 LT |
363 | call cheetah_patch_cachetlbops |
364 | nop | |
365 | ||
366 | ba,pt %xcc, tlb_fixup_done | |
367 | nop | |
368 | ||
369 | spitfire_tlb_fixup: | |
1da177e4 LT |
370 | /* Set TLB type to spitfire. */ |
371 | mov 0, %g2 | |
372 | sethi %hi(tlb_type), %g1 | |
373 | stw %g2, [%g1 + %lo(tlb_type)] | |
374 | ||
375 | tlb_fixup_done: | |
376 | sethi %hi(init_thread_union), %g6 | |
377 | or %g6, %lo(init_thread_union), %g6 | |
378 | ldx [%g6 + TI_TASK], %g4 | |
379 | mov %sp, %l6 | |
380 | mov %o4, %l7 | |
381 | ||
1da177e4 LT |
382 | wr %g0, ASI_P, %asi |
383 | mov 1, %g1 | |
384 | sllx %g1, THREAD_SHIFT, %g1 | |
385 | sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1 | |
386 | add %g6, %g1, %sp | |
387 | mov 0, %fp | |
388 | ||
389 | /* Set per-cpu pointer initially to zero, this makes | |
390 | * the boot-cpu use the in-kernel-image per-cpu areas | |
391 | * before setup_per_cpu_area() is invoked. | |
392 | */ | |
393 | clr %g5 | |
394 | ||
395 | wrpr %g0, 0, %wstate | |
396 | wrpr %g0, 0x0, %tl | |
397 | ||
398 | /* Clear the bss */ | |
399 | sethi %hi(__bss_start), %o0 | |
400 | or %o0, %lo(__bss_start), %o0 | |
401 | sethi %hi(_end), %o1 | |
402 | or %o1, %lo(_end), %o1 | |
403 | call __bzero | |
404 | sub %o1, %o0, %o1 | |
405 | ||
406 | mov %l6, %o1 ! OpenPROM stack | |
407 | call prom_init | |
408 | mov %l7, %o0 ! OpenPROM cif handler | |
409 | ||
410 | /* Off we go.... */ | |
411 | call start_kernel | |
412 | nop | |
413 | /* Not reached... */ | |
414 | ||
5d8e1b18 DM |
415 | /* This is meant to allow the sharing of this code between |
416 | * boot processor invocation (via setup_tba() below) and | |
417 | * secondary processor startup (via trampoline.S). The | |
418 | * former does use this code, the latter does not yet due | |
419 | * to some complexities. That should be fixed up at some | |
420 | * point. | |
c9c10830 DM |
421 | * |
422 | * There used to be enormous complexity wrt. transferring | |
423 | * over from the firwmare's trap table to the Linux kernel's. | |
424 | * For example, there was a chicken & egg problem wrt. building | |
425 | * the OBP page tables, yet needing to be on the Linux kernel | |
426 | * trap table (to translate PAGE_OFFSET addresses) in order to | |
427 | * do that. | |
428 | * | |
429 | * We now handle OBP tlb misses differently, via linear lookups | |
430 | * into the prom_trans[] array. So that specific problem no | |
431 | * longer exists. Yet, unfortunately there are still some issues | |
432 | * preventing trampoline.S from using this code... ho hum. | |
5d8e1b18 DM |
433 | */ |
434 | .globl setup_trap_table | |
435 | setup_trap_table: | |
436 | save %sp, -192, %sp | |
437 | ||
c9c10830 | 438 | /* Force interrupts to be disabled. */ |
5d8e1b18 DM |
439 | rdpr %pstate, %o1 |
440 | andn %o1, PSTATE_IE, %o1 | |
441 | wrpr %o1, 0x0, %pstate | |
442 | wrpr %g0, 15, %pil | |
1da177e4 | 443 | |
c9c10830 | 444 | /* Make the firmware call to jump over to the Linux trap table. */ |
5d8e1b18 DM |
445 | call prom_set_trap_table |
446 | sethi %hi(sparc64_ttable_tl0), %o0 | |
447 | ||
448 | /* Start using proper page size encodings in ctx register. */ | |
449 | sethi %hi(sparc64_kern_pri_context), %g3 | |
450 | ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2 | |
8b11bd12 DM |
451 | |
452 | mov PRIMARY_CONTEXT, %g1 | |
453 | ||
454 | 661: stxa %g2, [%g1] ASI_DMMU | |
455 | .section .sun4v_1insn_patch, "ax" | |
456 | .word 661b | |
457 | stxa %g2, [%g1] ASI_MMU | |
458 | .previous | |
459 | ||
5d8e1b18 DM |
460 | membar #Sync |
461 | ||
1da177e4 LT |
462 | /* Kill PROM timer */ |
463 | sethi %hi(0x80000000), %o2 | |
464 | sllx %o2, 32, %o2 | |
465 | wr %o2, 0, %tick_cmpr | |
466 | ||
467 | BRANCH_IF_ANY_CHEETAH(o2,o3,1f) | |
468 | ||
469 | ba,pt %xcc, 2f | |
470 | nop | |
471 | ||
472 | /* Disable STICK_INT interrupts. */ | |
473 | 1: | |
474 | sethi %hi(0x80000000), %o2 | |
475 | sllx %o2, 32, %o2 | |
476 | wr %o2, %asr25 | |
477 | ||
1da177e4 LT |
478 | 2: |
479 | wrpr %g0, %g0, %wstate | |
1da177e4 LT |
480 | |
481 | call init_irqwork_curcpu | |
482 | nop | |
483 | ||
5d8e1b18 | 484 | /* Now we can turn interrupts back on. */ |
1da177e4 LT |
485 | rdpr %pstate, %o1 |
486 | or %o1, PSTATE_IE, %o1 | |
487 | wrpr %o1, 0, %pstate | |
5d8e1b18 DM |
488 | wrpr %g0, 0x0, %pil |
489 | ||
490 | ret | |
491 | restore | |
492 | ||
493 | .globl setup_tba | |
a8b900d8 | 494 | setup_tba: |
5d8e1b18 DM |
495 | save %sp, -192, %sp |
496 | ||
497 | /* The boot processor is the only cpu which invokes this | |
498 | * routine, the other cpus set things up via trampoline.S. | |
499 | * So save the OBP trap table address here. | |
500 | */ | |
501 | rdpr %tba, %g7 | |
502 | sethi %hi(prom_tba), %o1 | |
503 | or %o1, %lo(prom_tba), %o1 | |
504 | stx %g7, [%o1] | |
505 | ||
506 | call setup_trap_table | |
507 | nop | |
1da177e4 LT |
508 | |
509 | ret | |
510 | restore | |
c9c10830 DM |
511 | sparc64_boot_end: |
512 | ||
513 | #include "systbls.S" | |
514 | #include "ktlb.S" | |
74bf4312 | 515 | #include "tsb.S" |
c9c10830 DM |
516 | #include "etrap.S" |
517 | #include "rtrap.S" | |
518 | #include "winfixup.S" | |
519 | #include "entry.S" | |
5b0c0572 DM |
520 | #include "sun4v_tlb_miss.S" |
521 | #include "sun4v_ivec.S" | |
1da177e4 LT |
522 | |
523 | /* | |
c9c10830 | 524 | * The following skip makes sure the trap table in ttable.S is aligned |
1da177e4 | 525 | * on a 32K boundary as required by the v9 specs for TBA register. |
2f7ee7c6 DM |
526 | * |
527 | * We align to a 32K boundary, then we have the 32K kernel TSB, | |
528 | * then the 32K aligned trap table. | |
1da177e4 | 529 | */ |
c9c10830 DM |
530 | 1: |
531 | .skip 0x4000 + _start - 1b | |
1da177e4 | 532 | |
2f7ee7c6 DM |
533 | .globl swapper_tsb |
534 | swapper_tsb: | |
535 | .skip (32 * 1024) | |
1da177e4 LT |
536 | |
537 | ! 0x0000000000408000 | |
538 | ||
539 | #include "ttable.S" | |
1da177e4 LT |
540 | |
541 | .data | |
542 | .align 8 | |
543 | .globl prom_tba, tlb_type | |
544 | prom_tba: .xword 0 | |
545 | tlb_type: .word 0 /* Must NOT end up in BSS */ | |
546 | .section ".fixup",#alloc,#execinstr | |
5fd29752 DM |
547 | |
548 | .globl __ret_efault, __retl_efault | |
1da177e4 LT |
549 | __ret_efault: |
550 | ret | |
551 | restore %g0, -EFAULT, %o0 | |
5fd29752 DM |
552 | __retl_efault: |
553 | retl | |
554 | mov -EFAULT, %o0 |