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sparc: video drivers: add facility level
[linux-2.6-block.git] / arch / sparc64 / kernel / head.S
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1966287d 1/* head.S: Initial boot code for the Sparc64 port of Linux.
1da177e4 2 *
1966287d 3 * Copyright (C) 1996, 1997, 2007 David S. Miller (davem@davemloft.net)
1da177e4 4 * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
1966287d 5 * Copyright (C) 1997, 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
1da177e4
LT		 6 * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 */
8
1da177e4
LT		 9#include <linux/version.h>
10#include <linux/errno.h>
951bc82c 11#include <linux/threads.h>
1966287d 12#include <linux/init.h>
1da177e4
LT		 13#include <asm/thread_info.h>
14#include <asm/asi.h>
15#include <asm/pstate.h>
16#include <asm/ptrace.h>
17#include <asm/spitfire.h>
18#include <asm/page.h>
19#include <asm/pgtable.h>
20#include <asm/errno.h>
21#include <asm/signal.h>
22#include <asm/processor.h>
23#include <asm/lsu.h>
24#include <asm/dcr.h>
25#include <asm/dcu.h>
26#include <asm/head.h>
27#include <asm/ttable.h>
28#include <asm/mmu.h>
56fb4df6 29#include <asm/cpudata.h>
1da177e4
LT		 30
31/* This section from from _start to sparc64_boot_end should fit into
c9c10830 32 * 0x0000000000404000 to 0x0000000000408000.
1da177e4 33 */
1da177e4
LT		 34 .text
35 .globl start, _start, stext, _stext
36_start:
37start:
38_stext:
39stext:
1da177e4
LT		 40! 0x0000000000404000
41 b sparc64_boot
42 flushw /* Flush register file. */
43
44/* This stuff has to be in sync with SILO and other potential boot loaders
45 * Fields should be kept upward compatible and whenever any change is made,
46 * HdrS version should be incremented.
47 */
48 .global root_flags, ram_flags, root_dev
49 .global sparc_ramdisk_image, sparc_ramdisk_size
50 .global sparc_ramdisk_image64
51
52 .ascii "HdrS"
53 .word LINUX_VERSION_CODE
54
55 /* History:
56 *
57 * 0x0300 : Supports being located at other than 0x4000
58 * 0x0202 : Supports kernel params string
59 * 0x0201 : Supports reboot_command
60 */
61 .half 0x0301 /* HdrS version */
62
63root_flags:
64 .half 1
65root_dev:
66 .half 0
67ram_flags:
68 .half 0
69sparc_ramdisk_image:
70 .word 0
71sparc_ramdisk_size:
72 .word 0
73 .xword reboot_command
74 .xword bootstr_info
75sparc_ramdisk_image64:
76 .xword 0
77 .word _end
78
bff06d55
DM		 79 /* PROM cif handler code address is in %o4. */
80sparc64_boot:
15f14834 81 mov %o4, %l7
bff06d55
DM		 82
83 /* We need to remap the kernel. Use position independant
84 * code to remap us to KERNBASE.
1da177e4 85 *
bff06d55
DM		 86 * SILO can invoke us with 32-bit address masking enabled,
87 * so make sure that's clear.
1da177e4 88 */
bff06d55
DM		 89 rdpr %pstate, %g1
90 andn %g1, PSTATE_AM, %g1
91 wrpr %g1, 0x0, %pstate
92 ba,a,pt %xcc, 1f
93
d82ace7d
DM		 94 .globl prom_finddev_name, prom_chosen_path, prom_root_node
95 .globl prom_getprop_name, prom_mmu_name, prom_peer_name
96 .globl prom_callmethod_name, prom_translate_name, prom_root_compatible
bff06d55
DM		 97 .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
98 .globl prom_boot_mapped_pc, prom_boot_mapping_mode
99 .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
6c70b6fc 100 .globl prom_compatible_name, prom_cpu_path, prom_cpu_compatible
301feb65 101 .globl is_sun4v, sun4v_chip_type, prom_set_trap_table_name
d82ace7d
DM		 102prom_peer_name:
103 .asciz "peer"
104prom_compatible_name:
105 .asciz "compatible"
bff06d55
DM		 106prom_finddev_name:
107 .asciz "finddevice"
108prom_chosen_path:
109 .asciz "/chosen"
6c70b6fc
DM		 110prom_cpu_path:
111 .asciz "/cpu"
bff06d55
DM		 112prom_getprop_name:
113 .asciz "getprop"
114prom_mmu_name:
115 .asciz "mmu"
116prom_callmethod_name:
117 .asciz "call-method"
118prom_translate_name:
119 .asciz "translate"
120prom_map_name:
121 .asciz "map"
122prom_unmap_name:
123 .asciz "unmap"
301feb65
DM		 124prom_set_trap_table_name:
125 .asciz "SUNW,set-trap-table"
d82ace7d 126prom_sun4v_name:
6cebb520 127 .asciz "sun4v"
6c70b6fc
DM		 128prom_niagara_prefix:
129 .asciz "SUNW,UltraSPARC-T"
bff06d55 130 .align 4
d82ace7d
DM		 131prom_root_compatible:
132 .skip 64
6c70b6fc
DM		 133prom_cpu_compatible:
134 .skip 64
d82ace7d
DM		 135prom_root_node:
136 .word 0
bff06d55
DM		 137prom_mmu_ihandle_cache:
138 .word 0
139prom_boot_mapped_pc:
140 .word 0
141prom_boot_mapping_mode:
142 .word 0
143 .align 8
144prom_boot_mapping_phys_high:
145 .xword 0
146prom_boot_mapping_phys_low:
147 .xword 0
d82ace7d
DM		 148is_sun4v:
149 .word 0
6c70b6fc
DM		 150sun4v_chip_type:
151 .word SUN4V_CHIP_INVALID
bff06d55
DM		 1521:
153 rd %pc, %l0
d82ace7d
DM		 154
155 mov (1b - prom_peer_name), %l1
156 sub %l0, %l1, %l1
157 mov 0, %l2
158
159 /* prom_root_node = prom_peer(0) */
160 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
161 mov 1, %l3
162 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
163 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
164 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
165 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
166 call %l7
167 add %sp, (2047 + 128), %o0 ! argument array
168
169 ldx [%sp + 2047 + 128 + 0x20], %l4 ! prom root node
170 mov (1b - prom_root_node), %l1
171 sub %l0, %l1, %l1
172 stw %l4, [%l1]
173
174 mov (1b - prom_getprop_name), %l1
175 mov (1b - prom_compatible_name), %l2
176 mov (1b - prom_root_compatible), %l5
177 sub %l0, %l1, %l1
178 sub %l0, %l2, %l2
179 sub %l0, %l5, %l5
180
181 /* prom_getproperty(prom_root_node, "compatible",
182 * &prom_root_compatible, 64)
183 */
184 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
185 mov 4, %l3
186 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
187 mov 1, %l3
188 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
189 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, prom_root_node
190 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
191 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_root_compatible
192 mov 64, %l3
193 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
194 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
195 call %l7
196 add %sp, (2047 + 128), %o0 ! argument array
197
bff06d55
DM		 198 mov (1b - prom_finddev_name), %l1
199 mov (1b - prom_chosen_path), %l2
200 mov (1b - prom_boot_mapped_pc), %l3
201 sub %l0, %l1, %l1
202 sub %l0, %l2, %l2
203 sub %l0, %l3, %l3
204 stw %l0, [%l3]
205 sub %sp, (192 + 128), %sp
206
207 /* chosen_node = prom_finddevice("/chosen") */
208 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
209 mov 1, %l3
210 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
211 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
212 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
213 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
214 call %l7
215 add %sp, (2047 + 128), %o0 ! argument array
216
217 ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
218
219 mov (1b - prom_getprop_name), %l1
220 mov (1b - prom_mmu_name), %l2
221 mov (1b - prom_mmu_ihandle_cache), %l5
222 sub %l0, %l1, %l1
223 sub %l0, %l2, %l2
224 sub %l0, %l5, %l5
225
226 /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
227 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
228 mov 4, %l3
229 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
230 mov 1, %l3
231 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
232 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
233 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
234 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
235 mov 4, %l3
236 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
237 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
238 call %l7
239 add %sp, (2047 + 128), %o0 ! argument array
240
241 mov (1b - prom_callmethod_name), %l1
242 mov (1b - prom_translate_name), %l2
243 sub %l0, %l1, %l1
244 sub %l0, %l2, %l2
245 lduw [%l5], %l5 ! prom_mmu_ihandle_cache
246
247 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
248 mov 3, %l3
249 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
250 mov 5, %l3
251 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
252 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
253 stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
b1b510aa
DM		 254 /* PAGE align */
255 srlx %l0, 13, %l3
256 sllx %l3, 13, %l3
bff06d55
DM		 257 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
258 stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
259 stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
260 stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
261 stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
262 stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
263 call %l7
264 add %sp, (2047 + 128), %o0 ! argument array
265
266 ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
267 mov (1b - prom_boot_mapping_mode), %l4
268 sub %l0, %l4, %l4
269 stw %l1, [%l4]
270 mov (1b - prom_boot_mapping_phys_high), %l4
271 sub %l0, %l4, %l4
272 ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
273 stx %l2, [%l4 + 0x0]
274 ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
b1b510aa
DM		 275 /* 4MB align */
276 srlx %l3, 22, %l3
277 sllx %l3, 22, %l3
bff06d55
DM		 278 stx %l3, [%l4 + 0x8]
279
280 /* Leave service as-is, "call-method" */
281 mov 7, %l3
282 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
283 mov 1, %l3
a8201c61 284 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
bff06d55
DM		 285 mov (1b - prom_map_name), %l3
286 sub %l0, %l3, %l3
287 stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
288 /* Leave arg2 as-is, prom_mmu_ihandle_cache */
289 mov -1, %l3
290 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
64658743
DM		 291 /* 4MB align the kernel image size. */
292 set (_end - KERNBASE), %l3
293 set ((4 * 1024 * 1024) - 1), %l4
294 add %l3, %l4, %l3
295 andn %l3, %l4, %l3
296 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: roundup(ksize, 4MB)
bff06d55
DM		 297 sethi %hi(KERNBASE), %l3
298 stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
299 stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
300 mov (1b - prom_boot_mapping_phys_low), %l3
301 sub %l0, %l3, %l3
302 ldx [%l3], %l3
303 stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
304 call %l7
305 add %sp, (2047 + 128), %o0 ! argument array
306
307 add %sp, (192 + 128), %sp
308
d82ace7d
DM		 309 sethi %hi(prom_root_compatible), %g1
310 or %g1, %lo(prom_root_compatible), %g1
311 sethi %hi(prom_sun4v_name), %g7
312 or %g7, %lo(prom_sun4v_name), %g7
6cebb520 313 mov 5, %g3
6c70b6fc 31490: ldub [%g7], %g2
d82ace7d
DM		 315 ldub [%g1], %g4
316 cmp %g2, %g4
6c70b6fc 317 bne,pn %icc, 80f
d82ace7d
DM		 318 add %g7, 1, %g7
319 subcc %g3, 1, %g3
6c70b6fc 320 bne,pt %xcc, 90b
d82ace7d
DM		 321 add %g1, 1, %g1
322
323 sethi %hi(is_sun4v), %g1
324 or %g1, %lo(is_sun4v), %g1
325 mov 1, %g7
326 stw %g7, [%g1]
327
6c70b6fc
DM		 328 /* cpu_node = prom_finddevice("/cpu") */
329 mov (1b - prom_finddev_name), %l1
330 mov (1b - prom_cpu_path), %l2
331 sub %l0, %l1, %l1
332 sub %l0, %l2, %l2
333 sub %sp, (192 + 128), %sp
334
335 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
336 mov 1, %l3
337 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
338 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
339 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/cpu"
340 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
341 call %l7
342 add %sp, (2047 + 128), %o0 ! argument array
343
344 ldx [%sp + 2047 + 128 + 0x20], %l4 ! cpu device node
345
346 mov (1b - prom_getprop_name), %l1
347 mov (1b - prom_compatible_name), %l2
348 mov (1b - prom_cpu_compatible), %l5
349 sub %l0, %l1, %l1
350 sub %l0, %l2, %l2
351 sub %l0, %l5, %l5
352
353 /* prom_getproperty(cpu_node, "compatible",
354 * &prom_cpu_compatible, 64)
355 */
356 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
357 mov 4, %l3
358 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
359 mov 1, %l3
360 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
361 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, cpu_node
362 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
363 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_cpu_compatible
364 mov 64, %l3
365 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
366 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
367 call %l7
368 add %sp, (2047 + 128), %o0 ! argument array
369
370 add %sp, (192 + 128), %sp
371
372 sethi %hi(prom_cpu_compatible), %g1
373 or %g1, %lo(prom_cpu_compatible), %g1
374 sethi %hi(prom_niagara_prefix), %g7
375 or %g7, %lo(prom_niagara_prefix), %g7
376 mov 17, %g3
37790: ldub [%g7], %g2
378 ldub [%g1], %g4
379 cmp %g2, %g4
380 bne,pn %icc, 4f
381 add %g7, 1, %g7
382 subcc %g3, 1, %g3
383 bne,pt %xcc, 90b
384 add %g1, 1, %g1
385
386 sethi %hi(prom_cpu_compatible), %g1
387 or %g1, %lo(prom_cpu_compatible), %g1
388 ldub [%g1 + 17], %g2
389 cmp %g2, '1'
390 be,pt %xcc, 5f
391 mov SUN4V_CHIP_NIAGARA1, %g4
392 cmp %g2, '2'
393 be,pt %xcc, 5f
394 mov SUN4V_CHIP_NIAGARA2, %g4
3954:
396 mov SUN4V_CHIP_UNKNOWN, %g4
3975: sethi %hi(sun4v_chip_type), %g2
398 or %g2, %lo(sun4v_chip_type), %g2
399 stw %g4, [%g2]
400
40180:
d82ace7d 402 BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
1da177e4
LT		 403 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
404 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
405 ba,pt %xcc, spitfire_boot
406 nop
407
408cheetah_plus_boot:
409 /* Preserve OBP chosen DCU and DCR register settings. */
410 ba,pt %xcc, cheetah_generic_boot
411 nop
412
413cheetah_boot:
414 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
415 wr %g1, %asr18
416
417 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
418 or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
419 sllx %g7, 32, %g7
420 or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
421 stxa %g7, [%g0] ASI_DCU_CONTROL_REG
422 membar #Sync
423
424cheetah_generic_boot:
425 mov TSB_EXTENSION_P, %g3
426 stxa %g0, [%g3] ASI_DMMU
427 stxa %g0, [%g3] ASI_IMMU
428 membar #Sync
429
430 mov TSB_EXTENSION_S, %g3
431 stxa %g0, [%g3] ASI_DMMU
432 membar #Sync
433
434 mov TSB_EXTENSION_N, %g3
435 stxa %g0, [%g3] ASI_DMMU
436 stxa %g0, [%g3] ASI_IMMU
437 membar #Sync
438
bff06d55 439 ba,a,pt %xcc, jump_to_sun4u_init
1da177e4
LT		 440
441spitfire_boot:
442 /* Typically PROM has already enabled both MMU's and both on-chip
443 * caches, but we do it here anyway just to be paranoid.
444 */
445 mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
446 stxa %g1, [%g0] ASI_LSU_CONTROL
447 membar #Sync
448
bff06d55 449jump_to_sun4u_init:
1da177e4
LT		 450 /*
451 * Make sure we are in privileged mode, have address masking,
452 * using the ordinary globals and have enabled floating
453 * point.
454 *
455 * Again, typically PROM has left %pil at 13 or similar, and
456 * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
457 */
458 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
459 wr %g0, 0, %fprs
460
1da177e4
LT		 461 set sun4u_init, %g2
462 jmpl %g2 + %g0, %g0
463 nop
464
1966287d 465 .section .text.init.refok
1da177e4 466sun4u_init:
6cebb520
DM		 467 BRANCH_IF_SUN4V(g1, sun4v_init)
468
1da177e4 469 /* Set ctx 0 */
8b11bd12 470 mov PRIMARY_CONTEXT, %g7
6cebb520 471 stxa %g0, [%g7] ASI_DMMU
8b11bd12
DM		 472 membar #Sync
473
474 mov SECONDARY_CONTEXT, %g7
6cebb520
DM		 475 stxa %g0, [%g7] ASI_DMMU
476 membar #Sync
477
478 ba,pt %xcc, sun4u_continue
479 nop
8b11bd12 480
6cebb520
DM		 481sun4v_init:
482 /* Set ctx 0 */
483 mov PRIMARY_CONTEXT, %g7
8b11bd12 484 stxa %g0, [%g7] ASI_MMU
6cebb520 485 membar #Sync
1da177e4 486
6cebb520
DM		 487 mov SECONDARY_CONTEXT, %g7
488 stxa %g0, [%g7] ASI_MMU
489 membar #Sync
490 ba,pt %xcc, niagara_tlb_fixup
491 nop
1da177e4 492
6cebb520 493sun4u_continue:
d82ace7d 494 BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
1da177e4
LT		 495
496 ba,pt %xcc, spitfire_tlb_fixup
497 nop
498
8591e302
DM		 499niagara_tlb_fixup:
500 mov 3, %g2 /* Set TLB type to hypervisor. */
501 sethi %hi(tlb_type), %g1
502 stw %g2, [%g1 + %lo(tlb_type)]
503
504 /* Patch copy/clear ops. */
6c70b6fc
DM		 505 sethi %hi(sun4v_chip_type), %g1
506 lduw [%g1 + %lo(sun4v_chip_type)], %g1
507 cmp %g1, SUN4V_CHIP_NIAGARA1
508 be,pt %xcc, niagara_patch
509 cmp %g1, SUN4V_CHIP_NIAGARA2
cf5adce1 510 be,pt %xcc, niagara2_patch
6c70b6fc
DM		 511 nop
512
513 call generic_patch_copyops
514 nop
515 call generic_patch_bzero
516 nop
517 call generic_patch_pageops
518 nop
519
520 ba,a,pt %xcc, 80f
cf5adce1
DM		 521niagara2_patch:
522 call niagara2_patch_copyops
523 nop
524 call niagara_patch_bzero
525 nop
526 call niagara2_patch_pageops
527 nop
528
529 ba,a,pt %xcc, 80f
6c70b6fc
DM		 530
531niagara_patch:
8591e302
DM		 532 call niagara_patch_copyops
533 nop
8ca2557c
DM		 534 call niagara_patch_bzero
535 nop
8591e302
DM		 536 call niagara_patch_pageops
537 nop
538
6c70b6fc 53980:
8591e302
DM		 540 /* Patch TLB/cache ops. */
541 call hypervisor_patch_cachetlbops
542 nop
543
d82ace7d
DM		 544 ba,pt %xcc, tlb_fixup_done
545 nop
546
1da177e4 547cheetah_tlb_fixup:
1da177e4
LT		 548 mov 2, %g2 /* Set TLB type to cheetah+. */
549 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
550
551 mov 1, %g2 /* Set TLB type to cheetah. */
552
5531: sethi %hi(tlb_type), %g1
554 stw %g2, [%g1 + %lo(tlb_type)]
555
0835ae0f 556 /* Patch copy/page operations to cheetah optimized versions. */
1da177e4
LT		 557 call cheetah_patch_copyops
558 nop
dbd2fdf5
DM		 559 call cheetah_patch_copy_page
560 nop
1da177e4
LT		 561 call cheetah_patch_cachetlbops
562 nop
563
564 ba,pt %xcc, tlb_fixup_done
565 nop
566
567spitfire_tlb_fixup:
1da177e4
LT		 568 /* Set TLB type to spitfire. */
569 mov 0, %g2
570 sethi %hi(tlb_type), %g1
571 stw %g2, [%g1 + %lo(tlb_type)]
572
573tlb_fixup_done:
574 sethi %hi(init_thread_union), %g6
575 or %g6, %lo(init_thread_union), %g6
576 ldx [%g6 + TI_TASK], %g4
577 mov %sp, %l6
1da177e4 578
1da177e4
LT		 579 wr %g0, ASI_P, %asi
580 mov 1, %g1
581 sllx %g1, THREAD_SHIFT, %g1
582 sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
583 add %g6, %g1, %sp
584 mov 0, %fp
585
586 /* Set per-cpu pointer initially to zero, this makes
587 * the boot-cpu use the in-kernel-image per-cpu areas
588 * before setup_per_cpu_area() is invoked.
589 */
590 clr %g5
591
592 wrpr %g0, 0, %wstate
593 wrpr %g0, 0x0, %tl
594
595 /* Clear the bss */
596 sethi %hi(__bss_start), %o0
597 or %o0, %lo(__bss_start), %o0
598 sethi %hi(_end), %o1
599 or %o1, %lo(_end), %o1
600 call __bzero
601 sub %o1, %o0, %o1
602
10e26723
DM		 603#ifdef CONFIG_LOCKDEP
604 /* We have this call this super early, as even prom_init can grab
605 * spinlocks and thus call into the lockdep code.
606 */
607 call lockdep_init
608 nop
609#endif
610
1da177e4
LT		 611 mov %l6, %o1 ! OpenPROM stack
612 call prom_init
613 mov %l7, %o0 ! OpenPROM cif handler
614
951bc82c
DM		 615 /* Initialize current_thread_info()->cpu as early as possible.
616 * In order to do that accurately we have to patch up the get_cpuid()
617 * assembler sequences. And that, in turn, requires that we know
618 * if we are on a Starfire box or not. While we're here, patch up
619 * the sun4v sequences as well.
620 */
621 call check_if_starfire
622 nop
623 call per_cpu_patch
624 nop
625 call sun4v_patch
626 nop
627
628#ifdef CONFIG_SMP
629 call hard_smp_processor_id
630 nop
631 cmp %o0, NR_CPUS
632 blu,pt %xcc, 1f
633 nop
634 call boot_cpu_id_too_large
635 nop
636 /* Not reached... */
637
6381:
ce22e1d3
DM		 639 /* If we boot on a non-zero cpu, all of the per-cpu
640 * variable references we make before setting up the
641 * per-cpu areas will use a bogus offset. Put a
642 * compensating factor into __per_cpu_base to handle
643 * this cleanly.
644 *
645 * What the per-cpu code calculates is:
646 *
647 * __per_cpu_base + (cpu << __per_cpu_shift)
648 *
649 * These two variables are zero initially, so to
650 * make it all cancel out to zero we need to put
651 * "0 - (cpu << 0)" into __per_cpu_base so that the
652 * above formula evaluates to zero.
653 *
654 * We cannot even perform a printk() until this stuff
655 * is setup as that calls cpu_clock() which uses
656 * per-cpu variables.
657 */
658 sub %g0, %o0, %o1
659 sethi %hi(__per_cpu_base), %o2
660 stx %o1, [%o2 + %lo(__per_cpu_base)]
951bc82c
DM		 661#else
662 mov 0, %o0
663#endif
22adb358 664 sth %o0, [%g6 + TI_CPU]
951bc82c 665
ce22e1d3
DM		 666 call prom_init_report
667 nop
668
1da177e4
LT		 669 /* Off we go.... */
670 call start_kernel
671 nop
672 /* Not reached... */
673
1966287d
DM		 674 .previous
675
5d8e1b18
DM		 676 /* This is meant to allow the sharing of this code between
677 * boot processor invocation (via setup_tba() below) and
678 * secondary processor startup (via trampoline.S). The
679 * former does use this code, the latter does not yet due
680 * to some complexities. That should be fixed up at some
681 * point.
c9c10830
DM		 682 *
683 * There used to be enormous complexity wrt. transferring
684 * over from the firwmare's trap table to the Linux kernel's.
685 * For example, there was a chicken & egg problem wrt. building
686 * the OBP page tables, yet needing to be on the Linux kernel
687 * trap table (to translate PAGE_OFFSET addresses) in order to
688 * do that.
689 *
690 * We now handle OBP tlb misses differently, via linear lookups
691 * into the prom_trans[] array. So that specific problem no
692 * longer exists. Yet, unfortunately there are still some issues
693 * preventing trampoline.S from using this code... ho hum.
5d8e1b18
DM		 694 */
695 .globl setup_trap_table
696setup_trap_table:
697 save %sp, -192, %sp
698
c9c10830 699 /* Force interrupts to be disabled. */
d8573e20
DM		 700 rdpr %pstate, %l0
701 andn %l0, PSTATE_IE, %o1
5d8e1b18 702 wrpr %o1, 0x0, %pstate
d8573e20 703 rdpr %pil, %l1
5d8e1b18 704 wrpr %g0, 15, %pil
1da177e4 705
c9c10830 706 /* Make the firmware call to jump over to the Linux trap table. */
12eaa328
DM		 707 sethi %hi(is_sun4v), %o0
708 lduw [%o0 + %lo(is_sun4v)], %o0
709 brz,pt %o0, 1f
710 nop
711
712 TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
713 add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
714 stxa %g2, [%g0] ASI_SCRATCHPAD
715
716 /* Compute physical address:
717 *
718 * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
719 */
720 sethi %hi(KERNBASE), %g3
721 sub %g2, %g3, %g2
722 sethi %hi(kern_base), %g3
723 ldx [%g3 + %lo(kern_base)], %g3
724 add %g2, %g3, %o1
301feb65 725 sethi %hi(sparc64_ttable_tl0), %o0
12eaa328 726
301feb65
DM		 727 set prom_set_trap_table_name, %g2
728 stx %g2, [%sp + 2047 + 128 + 0x00]
729 mov 2, %g2
730 stx %g2, [%sp + 2047 + 128 + 0x08]
731 mov 0, %g2
732 stx %g2, [%sp + 2047 + 128 + 0x10]
733 stx %o0, [%sp + 2047 + 128 + 0x18]
734 stx %o1, [%sp + 2047 + 128 + 0x20]
735 sethi %hi(p1275buf), %g2
736 or %g2, %lo(p1275buf), %g2
737 ldx [%g2 + 0x08], %o1
738 call %o1
739 add %sp, (2047 + 128), %o0
12eaa328
DM		 740
741 ba,pt %xcc, 2f
742 nop
743
301feb65
DM		 7441: sethi %hi(sparc64_ttable_tl0), %o0
745 set prom_set_trap_table_name, %g2
746 stx %g2, [%sp + 2047 + 128 + 0x00]
747 mov 1, %g2
748 stx %g2, [%sp + 2047 + 128 + 0x08]
749 mov 0, %g2
750 stx %g2, [%sp + 2047 + 128 + 0x10]
751 stx %o0, [%sp + 2047 + 128 + 0x18]
752 sethi %hi(p1275buf), %g2
753 or %g2, %lo(p1275buf), %g2
754 ldx [%g2 + 0x08], %o1
755 call %o1
756 add %sp, (2047 + 128), %o0
5d8e1b18
DM		 757
758 /* Start using proper page size encodings in ctx register. */
12eaa328 7592: sethi %hi(sparc64_kern_pri_context), %g3
5d8e1b18 760 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
8b11bd12
DM		 761
762 mov PRIMARY_CONTEXT, %g1
763
764661: stxa %g2, [%g1] ASI_DMMU
765 .section .sun4v_1insn_patch, "ax"
766 .word 661b
767 stxa %g2, [%g1] ASI_MMU
768 .previous
769
5d8e1b18
DM		 770 membar #Sync
771
53140b71
DM		 772 BRANCH_IF_SUN4V(o2, 1f)
773
1da177e4
LT		 774 /* Kill PROM timer */
775 sethi %hi(0x80000000), %o2
776 sllx %o2, 32, %o2
777 wr %o2, 0, %tick_cmpr
778
d82ace7d 779 BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
1da177e4
LT		 780
781 ba,pt %xcc, 2f
782 nop
783
784 /* Disable STICK_INT interrupts. */
7851:
786 sethi %hi(0x80000000), %o2
787 sllx %o2, 32, %o2
788 wr %o2, %asr25
789
1da177e4
LT		 7902:
791 wrpr %g0, %g0, %wstate
1da177e4
LT		 792
793 call init_irqwork_curcpu
794 nop
795
d8573e20
DM		 796 /* Now we can restore interrupt state. */
797 wrpr %l0, 0, %pstate
798 wrpr %l1, 0x0, %pil
5d8e1b18
DM		 799
800 ret
801 restore
802
803 .globl setup_tba
a8b900d8 804setup_tba:
5d8e1b18
DM		 805 save %sp, -192, %sp
806
807 /* The boot processor is the only cpu which invokes this
808 * routine, the other cpus set things up via trampoline.S.
809 * So save the OBP trap table address here.
810 */
811 rdpr %tba, %g7
812 sethi %hi(prom_tba), %o1
813 or %o1, %lo(prom_tba), %o1
814 stx %g7, [%o1]
815
816 call setup_trap_table
817 nop
1da177e4
LT		 818
819 ret
820 restore
c9c10830
DM		 821sparc64_boot_end:
822
c9c10830
DM		 823#include "etrap.S"
824#include "rtrap.S"
825#include "winfixup.S"
826#include "entry.S"
5b0c0572
DM		 827#include "sun4v_tlb_miss.S"
828#include "sun4v_ivec.S"
2d9e2763
DM		 829#include "ktlb.S"
830#include "tsb.S"
1da177e4
LT		 831
832/*
c9c10830 833 * The following skip makes sure the trap table in ttable.S is aligned
1da177e4 834 * on a 32K boundary as required by the v9 specs for TBA register.
2f7ee7c6
DM		 835 *
836 * We align to a 32K boundary, then we have the 32K kernel TSB,
2d9e2763 837 * the 64K kernel 4MB TSB, and then the 32K aligned trap table.
1da177e4 838 */
c9c10830
DM		 8391:
840 .skip 0x4000 + _start - 1b
1da177e4 841
2d9e2763
DM		 842! 0x0000000000408000
843
2f7ee7c6
DM		 844 .globl swapper_tsb
845swapper_tsb:
846 .skip (32 * 1024)
1da177e4 847
2d9e2763
DM		 848 .globl swapper_4m_tsb
849swapper_4m_tsb:
850 .skip (64 * 1024)
851
852! 0x0000000000420000
1da177e4 853
2d9e2763
DM		 854 /* Some care needs to be exercised if you try to move the
855 * location of the trap table relative to other things. For
856 * one thing there are br* instructions in some of the
857 * trap table entires which branch back to code in ktlb.S
858 * Those instructions can only handle a signed 16-bit
859 * displacement.
860 *
861 * There is a binutils bug (bugzilla #4558) which causes
862 * the relocation overflow checks for such instructions to
863 * not be done correctly. So bintuils will not notice the
864 * error and will instead write junk into the relocation and
865 * you'll have an unbootable kernel.
866 */
1da177e4 867#include "ttable.S"
1da177e4 868
2d9e2763
DM		 869! 0x0000000000428000
870
074d82cf
DM		 871#include "systbls.S"
872
1da177e4
LT		 873 .data
874 .align 8
875 .globl prom_tba, tlb_type
876prom_tba: .xword 0
877tlb_type: .word 0 /* Must NOT end up in BSS */
878 .section ".fixup",#alloc,#execinstr
5fd29752
DM		 879
880 .globl __ret_efault, __retl_efault
1da177e4
LT		 881__ret_efault:
882 ret
883 restore %g0, -EFAULT, %o0
5fd29752
DM		 884__retl_efault:
885 retl
886 mov -EFAULT, %o0
Linux 6.x block layer and io_uring tree(s)