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sparc: kernel: GRPCI2: Remove a useless memset
[linux-2.6-block.git] / arch / sparc / kernel / leon_pci_grpci2.c
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5d07b786
DH		 1/*
2 * leon_pci_grpci2.c: GRPCI2 Host PCI driver
3 *
4 * Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
5 *
6 */
7
8#include <linux/of_device.h>
9#include <linux/kernel.h>
10#include <linux/pci.h>
d6250ee2 11#include <linux/slab.h>
5d07b786 12#include <linux/delay.h>
066bcaca 13#include <linux/export.h>
5d07b786
DH		 14#include <asm/io.h>
15#include <asm/leon.h>
16#include <asm/vaddrs.h>
17#include <asm/sections.h>
18#include <asm/leon_pci.h>
19
20#include "irq.h"
21
22struct grpci2_barcfg {
23 unsigned long pciadr; /* PCI Space Address */
24 unsigned long ahbadr; /* PCI Base address mapped to this AHB addr */
25};
26
27/* Device Node Configuration options:
28 * - barcfgs : Custom Configuration of Host's 6 target BARs
29 * - irq_mask : Limit which PCI interrupts are enabled
30 * - do_reset : Force PCI Reset on startup
31 *
32 * barcfgs
33 * =======
34 *
35 * Optional custom Target BAR configuration (see struct grpci2_barcfg). All
36 * addresses are physical. Array always contains 6 elements (len=2*4*6 bytes)
37 *
38 * -1 means not configured (let host driver do default setup).
39 *
40 * [i*2+0] = PCI Address of BAR[i] on target interface
41 * [i*2+1] = Accessing PCI address of BAR[i] result in this AMBA address
42 *
43 *
44 * irq_mask
45 * ========
46 *
47 * Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
48 * all are enabled. Use this when PCI interrupt pins are floating on PCB.
49 * int, len=4.
50 * bit0 = PCI INTA#
51 * bit1 = PCI INTB#
52 * bit2 = PCI INTC#
53 * bit3 = PCI INTD#
54 *
55 *
56 * reset
57 * =====
58 *
59 * Force PCI reset on startup. int, len=4
60 */
61
62/* Enable Debugging Configuration Space Access */
63#undef GRPCI2_DEBUG_CFGACCESS
64
65/*
66 * GRPCI2 APB Register MAP
67 */
68struct grpci2_regs {
69 unsigned int ctrl; /* 0x00 Control */
70 unsigned int sts_cap; /* 0x04 Status / Capabilities */
71 int res1; /* 0x08 */
72 unsigned int io_map; /* 0x0C I/O Map address */
73 unsigned int dma_ctrl; /* 0x10 DMA */
74 unsigned int dma_bdbase; /* 0x14 DMA */
75 int res2[2]; /* 0x18 */
76 unsigned int bars[6]; /* 0x20 read-only PCI BARs */
77 int res3[2]; /* 0x38 */
78 unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */
79
80 /* PCI Trace Buffer Registers (OPTIONAL) */
81 unsigned int t_ctrl; /* 0x80 */
82 unsigned int t_cnt; /* 0x84 */
83 unsigned int t_adpat; /* 0x88 */
84 unsigned int t_admask; /* 0x8C */
85 unsigned int t_sigpat; /* 0x90 */
86 unsigned int t_sigmask; /* 0x94 */
87 unsigned int t_adstate; /* 0x98 */
88 unsigned int t_sigstate; /* 0x9C */
89};
90
91#define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a))))
92#define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
93
94#define CTRL_BUS_BIT 16
95
96#define CTRL_RESET (1<<31)
97#define CTRL_SI (1<<27)
98#define CTRL_PE (1<<26)
99#define CTRL_EI (1<<25)
100#define CTRL_ER (1<<24)
101#define CTRL_BUS (0xff<<CTRL_BUS_BIT)
102#define CTRL_HOSTINT 0xf
103
104#define STS_HOST_BIT 31
105#define STS_MST_BIT 30
106#define STS_TAR_BIT 29
107#define STS_DMA_BIT 28
108#define STS_DI_BIT 27
109#define STS_HI_BIT 26
110#define STS_IRQMODE_BIT 24
111#define STS_TRACE_BIT 23
112#define STS_CFGERRVALID_BIT 20
113#define STS_CFGERR_BIT 19
114#define STS_INTTYPE_BIT 12
115#define STS_INTSTS_BIT 8
116#define STS_FDEPTH_BIT 2
117#define STS_FNUM_BIT 0
118
119#define STS_HOST (1<<STS_HOST_BIT)
120#define STS_MST (1<<STS_MST_BIT)
121#define STS_TAR (1<<STS_TAR_BIT)
122#define STS_DMA (1<<STS_DMA_BIT)
123#define STS_DI (1<<STS_DI_BIT)
124#define STS_HI (1<<STS_HI_BIT)
125#define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
126#define STS_TRACE (1<<STS_TRACE_BIT)
127#define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
128#define STS_CFGERR (1<<STS_CFGERR_BIT)
129#define STS_INTTYPE (0x3f<<STS_INTTYPE_BIT)
130#define STS_INTSTS (0xf<<STS_INTSTS_BIT)
131#define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
132#define STS_FNUM (0x3<<STS_FNUM_BIT)
133
134#define STS_ISYSERR (1<<17)
135#define STS_IDMA (1<<16)
136#define STS_IDMAERR (1<<15)
137#define STS_IMSTABRT (1<<14)
138#define STS_ITGTABRT (1<<13)
139#define STS_IPARERR (1<<12)
140
141#define STS_ERR_IRQ (STS_ISYSERR | STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR)
142
143struct grpci2_bd_chan {
144 unsigned int ctrl; /* 0x00 DMA Control */
145 unsigned int nchan; /* 0x04 Next DMA Channel Address */
146 unsigned int nbd; /* 0x08 Next Data Descriptor in chan */
147 unsigned int res; /* 0x0C Reserved */
148};
149
150#define BD_CHAN_EN 0x80000000
151#define BD_CHAN_TYPE 0x00300000
152#define BD_CHAN_BDCNT 0x0000ffff
153#define BD_CHAN_EN_BIT 31
154#define BD_CHAN_TYPE_BIT 20
155#define BD_CHAN_BDCNT_BIT 0
156
157struct grpci2_bd_data {
158 unsigned int ctrl; /* 0x00 DMA Data Control */
159 unsigned int pci_adr; /* 0x04 PCI Start Address */
160 unsigned int ahb_adr; /* 0x08 AHB Start address */
161 unsigned int next; /* 0x0C Next Data Descriptor in chan */
162};
163
164#define BD_DATA_EN 0x80000000
165#define BD_DATA_IE 0x40000000
166#define BD_DATA_DR 0x20000000
167#define BD_DATA_TYPE 0x00300000
168#define BD_DATA_ER 0x00080000
169#define BD_DATA_LEN 0x0000ffff
170#define BD_DATA_EN_BIT 31
171#define BD_DATA_IE_BIT 30
172#define BD_DATA_DR_BIT 29
173#define BD_DATA_TYPE_BIT 20
174#define BD_DATA_ER_BIT 19
175#define BD_DATA_LEN_BIT 0
176
177/* GRPCI2 Capability */
178struct grpci2_cap_first {
179 unsigned int ctrl;
180 unsigned int pci2ahb_map[6];
181 unsigned int ext2ahb_map;
182 unsigned int io_map;
183 unsigned int pcibar_size[6];
184};
185#define CAP9_CTRL_OFS 0
186#define CAP9_BAR_OFS 0x4
187#define CAP9_IOMAP_OFS 0x20
188#define CAP9_BARSIZE_OFS 0x24
189
a2956428
DH		 190#define TGT 256
191
5d07b786
DH		 192struct grpci2_priv {
193 struct leon_pci_info info; /* must be on top of this structure */
3731e199 194 struct grpci2_regs __iomem *regs;
5d07b786
DH		 195 char irq;
196 char irq_mode; /* IRQ Mode from CAPSTS REG */
197 char bt_enabled;
198 char do_reset;
199 char irq_mask;
200 u32 pciid; /* PCI ID of Host */
201 unsigned char irq_map[4];
202
203 /* Virtual IRQ numbers */
204 unsigned int virq_err;
205 unsigned int virq_dma;
206
207 /* AHB PCI Windows */
208 unsigned long pci_area; /* MEMORY */
209 unsigned long pci_area_end;
210 unsigned long pci_io; /* I/O */
211 unsigned long pci_conf; /* CONFIGURATION */
212 unsigned long pci_conf_end;
213 unsigned long pci_io_va;
214
215 struct grpci2_barcfg tgtbars[6];
216};
217
3731e199
SR		 218static DEFINE_SPINLOCK(grpci2_dev_lock);
219static struct grpci2_priv *grpci2priv;
5d07b786 220
3731e199 221static int grpci2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
5d07b786
DH		 222{
223 struct grpci2_priv *priv = dev->bus->sysdata;
224 int irq_group;
225
226 /* Use default IRQ decoding on PCI BUS0 according slot numbering */
227 irq_group = slot & 0x3;
228 pin = ((pin - 1) + irq_group) & 0x3;
229
230 return priv->irq_map[pin];
231}
232
233static int grpci2_cfg_r32(struct grpci2_priv *priv, unsigned int bus,
234 unsigned int devfn, int where, u32 *val)
235{
236 unsigned int *pci_conf;
237 unsigned long flags;
238 u32 tmp;
239
240 if (where & 0x3)
241 return -EINVAL;
242
a2956428
DH		 243 if (bus == 0) {
244 devfn += (0x8 * 6); /* start at AD16=Device0 */
245 } else if (bus == TGT) {
246 bus = 0;
247 devfn = 0; /* special case: bridge controller itself */
248 }
5d07b786
DH		 249
250 /* Select bus */
251 spin_lock_irqsave(&grpci2_dev_lock, flags);
252 REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
253 (bus << 16));
254 spin_unlock_irqrestore(&grpci2_dev_lock, flags);
255
256 /* clear old status */
257 REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
258
259 pci_conf = (unsigned int *) (priv->pci_conf |
260 (devfn << 8) | (where & 0xfc));
261 tmp = LEON3_BYPASS_LOAD_PA(pci_conf);
262
263 /* Wait until GRPCI2 signals that CFG access is done, it should be
264 * done instantaneously unless a DMA operation is ongoing...
265 */
266 while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
267 ;
268
269 if (REGLOAD(priv->regs->sts_cap) & STS_CFGERR) {
270 *val = 0xffffffff;
271 } else {
272 /* Bus always little endian (unaffected by byte-swapping) */
01c6505d 273 *val = swab32(tmp);
5d07b786
DH		 274 }
275
276 return 0;
277}
278
279static int grpci2_cfg_r16(struct grpci2_priv *priv, unsigned int bus,
280 unsigned int devfn, int where, u32 *val)
281{
282 u32 v;
283 int ret;
284
285 if (where & 0x1)
286 return -EINVAL;
287 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
288 *val = 0xffff & (v >> (8 * (where & 0x3)));
289 return ret;
290}
291
292static int grpci2_cfg_r8(struct grpci2_priv *priv, unsigned int bus,
293 unsigned int devfn, int where, u32 *val)
294{
295 u32 v;
296 int ret;
297
298 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
299 *val = 0xff & (v >> (8 * (where & 3)));
300
301 return ret;
302}
303
304static int grpci2_cfg_w32(struct grpci2_priv *priv, unsigned int bus,
305 unsigned int devfn, int where, u32 val)
306{
307 unsigned int *pci_conf;
308 unsigned long flags;
309
310 if (where & 0x3)
311 return -EINVAL;
312
a2956428
DH		 313 if (bus == 0) {
314 devfn += (0x8 * 6); /* start at AD16=Device0 */
315 } else if (bus == TGT) {
316 bus = 0;
317 devfn = 0; /* special case: bridge controller itself */
318 }
5d07b786
DH		 319
320 /* Select bus */
321 spin_lock_irqsave(&grpci2_dev_lock, flags);
322 REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
323 (bus << 16));
324 spin_unlock_irqrestore(&grpci2_dev_lock, flags);
325
326 /* clear old status */
327 REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
328
329 pci_conf = (unsigned int *) (priv->pci_conf |
330 (devfn << 8) | (where & 0xfc));
01c6505d 331 LEON3_BYPASS_STORE_PA(pci_conf, swab32(val));
5d07b786
DH		 332
333 /* Wait until GRPCI2 signals that CFG access is done, it should be
334 * done instantaneously unless a DMA operation is ongoing...
335 */
336 while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
337 ;
338
339 return 0;
340}
341
342static int grpci2_cfg_w16(struct grpci2_priv *priv, unsigned int bus,
343 unsigned int devfn, int where, u32 val)
344{
345 int ret;
346 u32 v;
347
348 if (where & 0x1)
349 return -EINVAL;
350 ret = grpci2_cfg_r32(priv, bus, devfn, where&~3, &v);
351 if (ret)
352 return ret;
353 v = (v & ~(0xffff << (8 * (where & 0x3)))) |
354 ((0xffff & val) << (8 * (where & 0x3)));
355 return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
356}
357
358static int grpci2_cfg_w8(struct grpci2_priv *priv, unsigned int bus,
359 unsigned int devfn, int where, u32 val)
360{
361 int ret;
362 u32 v;
363
364 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
365 if (ret != 0)
366 return ret;
367 v = (v & ~(0xff << (8 * (where & 0x3)))) |
368 ((0xff & val) << (8 * (where & 0x3)));
369 return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
370}
371
372/* Read from Configuration Space. When entering here the PCI layer has taken
373 * the pci_lock spinlock and IRQ is off.
374 */
375static int grpci2_read_config(struct pci_bus *bus, unsigned int devfn,
376 int where, int size, u32 *val)
377{
378 struct grpci2_priv *priv = grpci2priv;
379 unsigned int busno = bus->number;
380 int ret;
381
a2956428 382 if (PCI_SLOT(devfn) > 15 || busno > 255) {
5d07b786
DH		 383 *val = ~0;
384 return 0;
385 }
386
387 switch (size) {
388 case 1:
389 ret = grpci2_cfg_r8(priv, busno, devfn, where, val);
390 break;
391 case 2:
392 ret = grpci2_cfg_r16(priv, busno, devfn, where, val);
393 break;
394 case 4:
395 ret = grpci2_cfg_r32(priv, busno, devfn, where, val);
396 break;
397 default:
398 ret = -EINVAL;
399 break;
400 }
401
402#ifdef GRPCI2_DEBUG_CFGACCESS
403 printk(KERN_INFO "grpci2_read_config: [%02x:%02x:%x] ofs=%d val=%x "
404 "size=%d\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where,
405 *val, size);
406#endif
407
408 return ret;
409}
410
411/* Write to Configuration Space. When entering here the PCI layer has taken
412 * the pci_lock spinlock and IRQ is off.
413 */
414static int grpci2_write_config(struct pci_bus *bus, unsigned int devfn,
415 int where, int size, u32 val)
416{
417 struct grpci2_priv *priv = grpci2priv;
418 unsigned int busno = bus->number;
419
a2956428 420 if (PCI_SLOT(devfn) > 15 || busno > 255)
5d07b786
DH		 421 return 0;
422
423#ifdef GRPCI2_DEBUG_CFGACCESS
424 printk(KERN_INFO "grpci2_write_config: [%02x:%02x:%x] ofs=%d size=%d "
425 "val=%x\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn),
426 where, size, val);
427#endif
428
429 switch (size) {
430 default:
431 return -EINVAL;
432 case 1:
433 return grpci2_cfg_w8(priv, busno, devfn, where, val);
434 case 2:
435 return grpci2_cfg_w16(priv, busno, devfn, where, val);
436 case 4:
437 return grpci2_cfg_w32(priv, busno, devfn, where, val);
438 }
439}
440
441static struct pci_ops grpci2_ops = {
442 .read = grpci2_read_config,
443 .write = grpci2_write_config,
444};
445
446/* GENIRQ IRQ chip implementation for GRPCI2 irqmode=0..2. In configuration
447 * 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller
448 * this is not needed and the standard IRQ controller can be used.
449 */
450
451static void grpci2_mask_irq(struct irq_data *data)
452{
453 unsigned long flags;
454 unsigned int irqidx;
455 struct grpci2_priv *priv = grpci2priv;
456
457 irqidx = (unsigned int)data->chip_data - 1;
458 if (irqidx > 3) /* only mask PCI interrupts here */
459 return;
460
461 spin_lock_irqsave(&grpci2_dev_lock, flags);
462 REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) & ~(1 << irqidx));
463 spin_unlock_irqrestore(&grpci2_dev_lock, flags);
464}
465
466static void grpci2_unmask_irq(struct irq_data *data)
467{
468 unsigned long flags;
469 unsigned int irqidx;
470 struct grpci2_priv *priv = grpci2priv;
471
472 irqidx = (unsigned int)data->chip_data - 1;
473 if (irqidx > 3) /* only unmask PCI interrupts here */
474 return;
475
476 spin_lock_irqsave(&grpci2_dev_lock, flags);
477 REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) | (1 << irqidx));
478 spin_unlock_irqrestore(&grpci2_dev_lock, flags);
479}
480
481static unsigned int grpci2_startup_irq(struct irq_data *data)
482{
483 grpci2_unmask_irq(data);
484 return 0;
485}
486
487static void grpci2_shutdown_irq(struct irq_data *data)
488{
489 grpci2_mask_irq(data);
490}
491
492static struct irq_chip grpci2_irq = {
493 .name = "grpci2",
494 .irq_startup = grpci2_startup_irq,
495 .irq_shutdown = grpci2_shutdown_irq,
496 .irq_mask = grpci2_mask_irq,
497 .irq_unmask = grpci2_unmask_irq,
498};
499
500/* Handle one or multiple IRQs from the PCI core */
501static void grpci2_pci_flow_irq(unsigned int irq, struct irq_desc *desc)
502{
503 struct grpci2_priv *priv = grpci2priv;
504 int i, ack = 0;
505 unsigned int ctrl, sts_cap, pci_ints;
506
507 ctrl = REGLOAD(priv->regs->ctrl);
508 sts_cap = REGLOAD(priv->regs->sts_cap);
509
510 /* Error Interrupt? */
511 if (sts_cap & STS_ERR_IRQ) {
512 generic_handle_irq(priv->virq_err);
513 ack = 1;
514 }
515
516 /* PCI Interrupt? */
517 pci_ints = ((~sts_cap) >> STS_INTSTS_BIT) & ctrl & CTRL_HOSTINT;
518 if (pci_ints) {
519 /* Call respective PCI Interrupt handler */
520 for (i = 0; i < 4; i++) {
521 if (pci_ints & (1 << i))
522 generic_handle_irq(priv->irq_map[i]);
523 }
524 ack = 1;
525 }
526
527 /*
528 * Decode DMA Interrupt only when shared with Err and PCI INTX#, when
529 * the DMA is a unique IRQ the DMA interrupts doesn't end up here, they
530 * goes directly to DMA ISR.
531 */
532 if ((priv->irq_mode == 0) && (sts_cap & (STS_IDMA | STS_IDMAERR))) {
533 generic_handle_irq(priv->virq_dma);
534 ack = 1;
535 }
536
537 /*
538 * Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ
539 * Controller, this must be done after IRQ sources have been handled to
540 * avoid double IRQ generation
541 */
542 if (ack)
543 desc->irq_data.chip->irq_eoi(&desc->irq_data);
544}
545
546/* Create a virtual IRQ */
547static unsigned int grpci2_build_device_irq(unsigned int irq)
548{
549 unsigned int virq = 0, pil;
550
551 pil = 1 << 8;
552 virq = irq_alloc(irq, pil);
553 if (virq == 0)
554 goto out;
555
556 irq_set_chip_and_handler_name(virq, &grpci2_irq, handle_simple_irq,
557 "pcilvl");
558 irq_set_chip_data(virq, (void *)irq);
559
560out:
561 return virq;
562}
563
3731e199 564static void grpci2_hw_init(struct grpci2_priv *priv)
5d07b786
DH		 565{
566 u32 ahbadr, pciadr, bar_sz, capptr, io_map, data;
3731e199 567 struct grpci2_regs __iomem *regs = priv->regs;
5d07b786
DH		 568 int i;
569 struct grpci2_barcfg *barcfg = priv->tgtbars;
570
571 /* Reset any earlier setup */
572 if (priv->do_reset) {
573 printk(KERN_INFO "GRPCI2: Resetting PCI bus\n");
574 REGSTORE(regs->ctrl, CTRL_RESET);
575 ssleep(1); /* Wait for boards to settle */
576 }
577 REGSTORE(regs->ctrl, 0);
578 REGSTORE(regs->sts_cap, ~0); /* Clear Status */
579 REGSTORE(regs->dma_ctrl, 0);
580 REGSTORE(regs->dma_bdbase, 0);
581
582 /* Translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */
583 REGSTORE(regs->io_map, REGLOAD(regs->io_map) & 0x0000ffff);
584
585 /* set 1:1 mapping between AHB -> PCI memory space, for all Masters
586 * Each AHB master has it's own mapping registers. Max 16 AHB masters.
587 */
588 for (i = 0; i < 16; i++)
589 REGSTORE(regs->ahbmst_map[i], priv->pci_area);
590
591 /* Get the GRPCI2 Host PCI ID */
a2956428 592 grpci2_cfg_r32(priv, TGT, 0, PCI_VENDOR_ID, &priv->pciid);
5d07b786
DH		 593
594 /* Get address to first (always defined) capability structure */
a2956428 595 grpci2_cfg_r8(priv, TGT, 0, PCI_CAPABILITY_LIST, &capptr);
5d07b786
DH		 596
597 /* Enable/Disable Byte twisting */
a2956428 598 grpci2_cfg_r32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, &io_map);
5d07b786 599 io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
a2956428 600 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, io_map);
5d07b786
DH		 601
602 /* Setup the Host's PCI Target BARs for other peripherals to access,
603 * and do DMA to the host's memory. The target BARs can be sized and
604 * enabled individually.
605 *
606 * User may set custom target BARs, but default is:
607 * The first BARs is used to map kernel low (DMA is part of normal
608 * region on sparc which is SRMMU_MAXMEM big) main memory 1:1 to the
609 * PCI bus, the other BARs are disabled. We assume that the first BAR
610 * is always available.
611 */
612 for (i = 0; i < 6; i++) {
613 if (barcfg[i].pciadr != ~0 && barcfg[i].ahbadr != ~0) {
614 /* Target BARs must have the proper alignment */
615 ahbadr = barcfg[i].ahbadr;
616 pciadr = barcfg[i].pciadr;
617 bar_sz = ((pciadr - 1) & ~pciadr) + 1;
618 } else {
619 if (i == 0) {
620 /* Map main memory */
621 bar_sz = 0xf0000008; /* 256MB prefetchable */
622 ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN(
623 (unsigned long) &_end));
624 pciadr = ahbadr;
625 } else {
626 bar_sz = 0;
627 ahbadr = 0;
628 pciadr = 0;
629 }
630 }
a2956428
DH		 631 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BARSIZE_OFS+i*4,
632 bar_sz);
633 grpci2_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
634 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr);
5d07b786
DH		 635 printk(KERN_INFO " TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n",
636 i, pciadr, ahbadr);
637 }
638
639 /* set as bus master and enable pci memory responses */
a2956428 640 grpci2_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data);
5d07b786 641 data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
a2956428 642 grpci2_cfg_w32(priv, TGT, 0, PCI_COMMAND, data);
5d07b786
DH		 643
644 /* Enable Error respone (CPU-TRAP) on illegal memory access. */
645 REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE);
646}
647
648static irqreturn_t grpci2_jump_interrupt(int irq, void *arg)
649{
650 printk(KERN_ERR "GRPCI2: Jump IRQ happened\n");
651 return IRQ_NONE;
652}
653
654/* Handle GRPCI2 Error Interrupt */
655static irqreturn_t grpci2_err_interrupt(int irq, void *arg)
656{
657 struct grpci2_priv *priv = arg;
3731e199 658 struct grpci2_regs __iomem *regs = priv->regs;
5d07b786
DH		 659 unsigned int status;
660
661 status = REGLOAD(regs->sts_cap);
662 if ((status & STS_ERR_IRQ) == 0)
663 return IRQ_NONE;
664
665 if (status & STS_IPARERR)
666 printk(KERN_ERR "GRPCI2: Parity Error\n");
667
668 if (status & STS_ITGTABRT)
669 printk(KERN_ERR "GRPCI2: Target Abort\n");
670
671 if (status & STS_IMSTABRT)
672 printk(KERN_ERR "GRPCI2: Master Abort\n");
673
674 if (status & STS_ISYSERR)
675 printk(KERN_ERR "GRPCI2: System Error\n");
676
677 /* Clear handled INT TYPE IRQs */
678 REGSTORE(regs->sts_cap, status & STS_ERR_IRQ);
679
680 return IRQ_HANDLED;
681}
682
7c9503b8 683static int grpci2_of_probe(struct platform_device *ofdev)
5d07b786 684{
3731e199 685 struct grpci2_regs __iomem *regs;
5d07b786
DH		 686 struct grpci2_priv *priv;
687 int err, i, len;
688 const int *tmp;
689 unsigned int capability;
690
691 if (grpci2priv) {
692 printk(KERN_ERR "GRPCI2: only one GRPCI2 core supported\n");
693 return -ENODEV;
694 }
695
696 if (ofdev->num_resources < 3) {
697 printk(KERN_ERR "GRPCI2: not enough APB/AHB resources\n");
698 return -EIO;
699 }
700
701 /* Find Device Address */
702 regs = of_ioremap(&ofdev->resource[0], 0,
703 resource_size(&ofdev->resource[0]),
704 "grlib-grpci2 regs");
705 if (regs == NULL) {
706 printk(KERN_ERR "GRPCI2: ioremap failed\n");
707 return -EIO;
708 }
709
710 /*
711 * Check that we're in Host Slot and that we can act as a Host Bridge
712 * and not only as target.
713 */
714 capability = REGLOAD(regs->sts_cap);
715 if ((capability & STS_HOST) || !(capability & STS_MST)) {
716 printk(KERN_INFO "GRPCI2: not in host system slot\n");
717 err = -EIO;
718 goto err1;
719 }
720
721 priv = grpci2priv = kzalloc(sizeof(struct grpci2_priv), GFP_KERNEL);
722 if (grpci2priv == NULL) {
723 err = -ENOMEM;
724 goto err1;
725 }
5d07b786
DH		 726 priv->regs = regs;
727 priv->irq = ofdev->archdata.irqs[0]; /* BASE IRQ */
728 priv->irq_mode = (capability & STS_IRQMODE) >> STS_IRQMODE_BIT;
729
730 printk(KERN_INFO "GRPCI2: host found at %p, irq%d\n", regs, priv->irq);
731
732 /* Byte twisting should be made configurable from kernel command line */
733 priv->bt_enabled = 1;
734
735 /* Let user do custom Target BAR assignment */
736 tmp = of_get_property(ofdev->dev.of_node, "barcfg", &len);
737 if (tmp && (len == 2*4*6))
738 memcpy(priv->tgtbars, tmp, 2*4*6);
739 else
740 memset(priv->tgtbars, -1, 2*4*6);
741
742 /* Limit IRQ unmasking in irq_mode 2 and 3 */
743 tmp = of_get_property(ofdev->dev.of_node, "irq_mask", &len);
744 if (tmp && (len == 4))
745 priv->do_reset = *tmp;
746 else
747 priv->irq_mask = 0xf;
748
749 /* Optional PCI reset. Force PCI reset on startup */
750 tmp = of_get_property(ofdev->dev.of_node, "reset", &len);
751 if (tmp && (len == 4))
752 priv->do_reset = *tmp;
753 else
754 priv->do_reset = 0;
755
756 /* Find PCI Memory, I/O and Configuration Space Windows */
757 priv->pci_area = ofdev->resource[1].start;
758 priv->pci_area_end = ofdev->resource[1].end+1;
759 priv->pci_io = ofdev->resource[2].start;
760 priv->pci_conf = ofdev->resource[2].start + 0x10000;
761 priv->pci_conf_end = priv->pci_conf + 0x10000;
762 priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000);
763 if (!priv->pci_io_va) {
764 err = -EIO;
765 goto err2;
766 }
767
768 printk(KERN_INFO
769 "GRPCI2: MEMORY SPACE [0x%08lx - 0x%08lx]\n"
770 " I/O SPACE [0x%08lx - 0x%08lx]\n"
771 " CONFIG SPACE [0x%08lx - 0x%08lx]\n",
772 priv->pci_area, priv->pci_area_end-1,
773 priv->pci_io, priv->pci_conf-1,
774 priv->pci_conf, priv->pci_conf_end-1);
775
776 /*
777 * I/O Space resources in I/O Window mapped into Virtual Adr Space
778 * We never use low 4KB because some devices seem have problems using
779 * address 0.
780 */
781 memset(&priv->info.io_space, 0, sizeof(struct resource));
782 priv->info.io_space.name = "GRPCI2 PCI I/O Space";
783 priv->info.io_space.start = priv->pci_io_va + 0x1000;
784 priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1;
785 priv->info.io_space.flags = IORESOURCE_IO;
786
787 /*
788 * GRPCI2 has no prefetchable memory, map everything as
789 * non-prefetchable memory
790 */
791 memset(&priv->info.mem_space, 0, sizeof(struct resource));
792 priv->info.mem_space.name = "GRPCI2 PCI MEM Space";
793 priv->info.mem_space.start = priv->pci_area;
794 priv->info.mem_space.end = priv->pci_area_end - 1;
795 priv->info.mem_space.flags = IORESOURCE_MEM;
796
797 if (request_resource(&iomem_resource, &priv->info.mem_space) < 0)
798 goto err3;
799 if (request_resource(&ioport_resource, &priv->info.io_space) < 0)
800 goto err4;
801
aa90b694
DH		 802 /* setup maximum supported PCI buses */
803 priv->info.busn.name = "GRPCI2 busn";
804 priv->info.busn.start = 0;
805 priv->info.busn.end = 255;
806
5d07b786
DH		 807 grpci2_hw_init(priv);
808
809 /*
810 * Get PCI Interrupt to System IRQ mapping and setup IRQ handling
811 * Error IRQ always on PCI INTA.
812 */
813 if (priv->irq_mode < 2) {
814 /* All PCI interrupts are shared using the same system IRQ */
815 leon_update_virq_handling(priv->irq, grpci2_pci_flow_irq,
816 "pcilvl", 0);
817
818 priv->irq_map[0] = grpci2_build_device_irq(1);
819 priv->irq_map[1] = grpci2_build_device_irq(2);
820 priv->irq_map[2] = grpci2_build_device_irq(3);
821 priv->irq_map[3] = grpci2_build_device_irq(4);
822
823 priv->virq_err = grpci2_build_device_irq(5);
824 if (priv->irq_mode & 1)
825 priv->virq_dma = ofdev->archdata.irqs[1];
826 else
827 priv->virq_dma = grpci2_build_device_irq(6);
828
829 /* Enable IRQs on LEON IRQ controller */
830 err = request_irq(priv->irq, grpci2_jump_interrupt, 0,
831 "GRPCI2_JUMP", priv);
832 if (err)
833 printk(KERN_ERR "GRPCI2: ERR IRQ request failed\n");
834 } else {
835 /* All PCI interrupts have an unique IRQ interrupt */
836 for (i = 0; i < 4; i++) {
837 /* Make LEON IRQ layer handle level IRQ by acking */
838 leon_update_virq_handling(ofdev->archdata.irqs[i],
839 handle_fasteoi_irq, "pcilvl",
840 1);
841 priv->irq_map[i] = ofdev->archdata.irqs[i];
842 }
843 priv->virq_err = priv->irq_map[0];
844 if (priv->irq_mode & 1)
845 priv->virq_dma = ofdev->archdata.irqs[4];
846 else
847 priv->virq_dma = priv->irq_map[0];
848
849 /* Unmask all PCI interrupts, request_irq will not do that */
850 REGSTORE(regs->ctrl, REGLOAD(regs->ctrl)|(priv->irq_mask&0xf));
851 }
852
853 /* Setup IRQ handler for non-configuration space access errors */
854 err = request_irq(priv->virq_err, grpci2_err_interrupt, IRQF_SHARED,
855 "GRPCI2_ERR", priv);
856 if (err) {
857 printk(KERN_DEBUG "GRPCI2: ERR VIRQ request failed: %d\n", err);
858 goto err5;
859 }
860
861 /*
862 * Enable Error Interrupts. PCI interrupts are unmasked once request_irq
863 * is called by the PCI Device drivers
864 */
865 REGSTORE(regs->ctrl, REGLOAD(regs->ctrl) | CTRL_EI | CTRL_SI);
866
867 /* Init common layer and scan buses */
868 priv->info.ops = &grpci2_ops;
869 priv->info.map_irq = grpci2_map_irq;
870 leon_pci_init(ofdev, &priv->info);
871
872 return 0;
873
874err5:
875 release_resource(&priv->info.io_space);
876err4:
877 release_resource(&priv->info.mem_space);
878err3:
879 err = -ENOMEM;
3731e199 880 iounmap((void __iomem *)priv->pci_io_va);
5d07b786
DH		 881err2:
882 kfree(priv);
883err1:
884 of_iounmap(&ofdev->resource[0], regs,
885 resource_size(&ofdev->resource[0]));
886 return err;
887}
888
889static struct of_device_id grpci2_of_match[] = {
890 {
891 .name = "GAISLER_GRPCI2",
892 },
893 {
894 .name = "01_07c",
895 },
896 {},
897};
898
899static struct platform_driver grpci2_of_driver = {
900 .driver = {
901 .name = "grpci2",
5d07b786
DH		 902 .of_match_table = grpci2_of_match,
903 },
904 .probe = grpci2_of_probe,
905};
906
907static int __init grpci2_init(void)
908{
909 return platform_driver_register(&grpci2_of_driver);
910}
911
912subsys_initcall(grpci2_init);
Linux 6.x block layer and io_uring tree(s)