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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
88278ca2 | 2 | /* |
fd49bf48 SR |
3 | * Interrupt request handling routines. On the |
4 | * Sparc the IRQs are basically 'cast in stone' | |
5 | * and you are supposed to probe the prom's device | |
6 | * node trees to find out who's got which IRQ. | |
1da177e4 LT |
7 | * |
8 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | |
9 | * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx) | |
10 | * Copyright (C) 1995,2002 Pete A. Zaitcev (zaitcev@yahoo.com) | |
11 | * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk) | |
12 | * Copyright (C) 1998-2000 Anton Blanchard (anton@samba.org) | |
13 | */ | |
14 | ||
1da177e4 | 15 | #include <linux/kernel_stat.h> |
1da177e4 | 16 | #include <linux/seq_file.h> |
7b64db60 | 17 | #include <linux/export.h> |
1da177e4 | 18 | |
a2a211cb | 19 | #include <asm/cacheflush.h> |
6baa9b20 | 20 | #include <asm/cpudata.h> |
fbb86383 | 21 | #include <asm/setup.h> |
1da177e4 | 22 | #include <asm/pcic.h> |
0fd7ef1f | 23 | #include <asm/leon.h> |
1da177e4 | 24 | |
81265fd9 | 25 | #include "kernel.h" |
32231a66 AV |
26 | #include "irq.h" |
27 | ||
bbdc2661 | 28 | /* platform specific irq setup */ |
472bc4f2 | 29 | struct sparc_config sparc_config; |
bbdc2661 | 30 | |
df9ee292 | 31 | unsigned long arch_local_irq_save(void) |
1da177e4 LT |
32 | { |
33 | unsigned long retval; | |
34 | unsigned long tmp; | |
35 | ||
36 | __asm__ __volatile__( | |
37 | "rd %%psr, %0\n\t" | |
1da177e4 LT |
38 | "or %0, %2, %1\n\t" |
39 | "wr %1, 0, %%psr\n\t" | |
40 | "nop; nop; nop\n" | |
41 | : "=&r" (retval), "=r" (tmp) | |
42 | : "i" (PSR_PIL) | |
43 | : "memory"); | |
44 | ||
45 | return retval; | |
46 | } | |
df9ee292 | 47 | EXPORT_SYMBOL(arch_local_irq_save); |
1da177e4 | 48 | |
df9ee292 | 49 | void arch_local_irq_enable(void) |
1da177e4 LT |
50 | { |
51 | unsigned long tmp; | |
52 | ||
53 | __asm__ __volatile__( | |
54 | "rd %%psr, %0\n\t" | |
1da177e4 LT |
55 | "andn %0, %1, %0\n\t" |
56 | "wr %0, 0, %%psr\n\t" | |
57 | "nop; nop; nop\n" | |
58 | : "=&r" (tmp) | |
59 | : "i" (PSR_PIL) | |
60 | : "memory"); | |
61 | } | |
df9ee292 | 62 | EXPORT_SYMBOL(arch_local_irq_enable); |
1da177e4 | 63 | |
df9ee292 | 64 | void arch_local_irq_restore(unsigned long old_psr) |
1da177e4 LT |
65 | { |
66 | unsigned long tmp; | |
67 | ||
68 | __asm__ __volatile__( | |
69 | "rd %%psr, %0\n\t" | |
70 | "and %2, %1, %2\n\t" | |
1da177e4 LT |
71 | "andn %0, %1, %0\n\t" |
72 | "wr %0, %2, %%psr\n\t" | |
73 | "nop; nop; nop\n" | |
74 | : "=&r" (tmp) | |
75 | : "i" (PSR_PIL), "r" (old_psr) | |
76 | : "memory"); | |
77 | } | |
df9ee292 | 78 | EXPORT_SYMBOL(arch_local_irq_restore); |
1da177e4 LT |
79 | |
80 | /* | |
81 | * Dave Redman (djhr@tadpole.co.uk) | |
82 | * | |
83 | * IRQ numbers.. These are no longer restricted to 15.. | |
84 | * | |
85 | * this is done to enable SBUS cards and onboard IO to be masked | |
86 | * correctly. using the interrupt level isn't good enough. | |
87 | * | |
88 | * For example: | |
89 | * A device interrupting at sbus level6 and the Floppy both come in | |
90 | * at IRQ11, but enabling and disabling them requires writing to | |
91 | * different bits in the SLAVIO/SEC. | |
92 | * | |
93 | * As a result of these changes sun4m machines could now support | |
94 | * directed CPU interrupts using the existing enable/disable irq code | |
95 | * with tweaks. | |
96 | * | |
6baa9b20 SR |
97 | * Sun4d complicates things even further. IRQ numbers are arbitrary |
98 | * 32-bit values in that case. Since this is similar to sparc64, | |
99 | * we adopt a virtual IRQ numbering scheme as is done there. | |
100 | * Virutal interrupt numbers are allocated by build_irq(). So NR_IRQS | |
101 | * just becomes a limit of how many interrupt sources we can handle in | |
102 | * a single system. Even fully loaded SS2000 machines top off at | |
103 | * about 32 interrupt sources or so, therefore a NR_IRQS value of 64 | |
104 | * is more than enough. | |
105 | * | |
106 | * We keep a map of per-PIL enable interrupts. These get wired | |
107 | * up via the irq_chip->startup() method which gets invoked by | |
108 | * the generic IRQ layer during request_irq(). | |
1da177e4 LT |
109 | */ |
110 | ||
1da177e4 | 111 | |
6baa9b20 SR |
112 | /* Table of allocated irqs. Unused entries has irq == 0 */ |
113 | static struct irq_bucket irq_table[NR_IRQS]; | |
114 | /* Protect access to irq_table */ | |
115 | static DEFINE_SPINLOCK(irq_table_lock); | |
1da177e4 | 116 | |
6baa9b20 SR |
117 | /* Map between the irq identifier used in hw to the irq_bucket. */ |
118 | struct irq_bucket *irq_map[SUN4D_MAX_IRQ]; | |
119 | /* Protect access to irq_map */ | |
120 | static DEFINE_SPINLOCK(irq_map_lock); | |
1da177e4 | 121 | |
6baa9b20 SR |
122 | /* Allocate a new irq from the irq_table */ |
123 | unsigned int irq_alloc(unsigned int real_irq, unsigned int pil) | |
1da177e4 | 124 | { |
1da177e4 | 125 | unsigned long flags; |
6baa9b20 SR |
126 | unsigned int i; |
127 | ||
128 | spin_lock_irqsave(&irq_table_lock, flags); | |
129 | for (i = 1; i < NR_IRQS; i++) { | |
130 | if (irq_table[i].real_irq == real_irq && irq_table[i].pil == pil) | |
131 | goto found; | |
132 | } | |
1da177e4 | 133 | |
6baa9b20 SR |
134 | for (i = 1; i < NR_IRQS; i++) { |
135 | if (!irq_table[i].irq) | |
136 | break; | |
137 | } | |
fd49bf48 | 138 | |
1da177e4 | 139 | if (i < NR_IRQS) { |
6baa9b20 SR |
140 | irq_table[i].real_irq = real_irq; |
141 | irq_table[i].irq = i; | |
142 | irq_table[i].pil = pil; | |
143 | } else { | |
144 | printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); | |
145 | i = 0; | |
1da177e4 | 146 | } |
6baa9b20 SR |
147 | found: |
148 | spin_unlock_irqrestore(&irq_table_lock, flags); | |
149 | ||
150 | return i; | |
1da177e4 LT |
151 | } |
152 | ||
6baa9b20 SR |
153 | /* Based on a single pil handler_irq may need to call several |
154 | * interrupt handlers. Use irq_map as entry to irq_table, | |
155 | * and let each entry in irq_table point to the next entry. | |
156 | */ | |
157 | void irq_link(unsigned int irq) | |
1da177e4 | 158 | { |
6baa9b20 | 159 | struct irq_bucket *p; |
fd49bf48 | 160 | unsigned long flags; |
6baa9b20 | 161 | unsigned int pil; |
fd49bf48 | 162 | |
6baa9b20 | 163 | BUG_ON(irq >= NR_IRQS); |
1da177e4 | 164 | |
6baa9b20 | 165 | spin_lock_irqsave(&irq_map_lock, flags); |
1da177e4 | 166 | |
6baa9b20 SR |
167 | p = &irq_table[irq]; |
168 | pil = p->pil; | |
fa160828 | 169 | BUG_ON(pil >= SUN4D_MAX_IRQ); |
6baa9b20 SR |
170 | p->next = irq_map[pil]; |
171 | irq_map[pil] = p; | |
1da177e4 | 172 | |
6baa9b20 SR |
173 | spin_unlock_irqrestore(&irq_map_lock, flags); |
174 | } | |
1da177e4 | 175 | |
6baa9b20 SR |
176 | void irq_unlink(unsigned int irq) |
177 | { | |
178 | struct irq_bucket *p, **pnext; | |
179 | unsigned long flags; | |
1da177e4 | 180 | |
6baa9b20 | 181 | BUG_ON(irq >= NR_IRQS); |
1da177e4 | 182 | |
6baa9b20 | 183 | spin_lock_irqsave(&irq_map_lock, flags); |
1da177e4 | 184 | |
6baa9b20 | 185 | p = &irq_table[irq]; |
fa160828 | 186 | BUG_ON(p->pil >= SUN4D_MAX_IRQ); |
6baa9b20 SR |
187 | pnext = &irq_map[p->pil]; |
188 | while (*pnext != p) | |
189 | pnext = &(*pnext)->next; | |
190 | *pnext = p->next; | |
1da177e4 | 191 | |
6baa9b20 | 192 | spin_unlock_irqrestore(&irq_map_lock, flags); |
1da177e4 | 193 | } |
1da177e4 | 194 | |
a54123e2 | 195 | |
6baa9b20 SR |
196 | /* /proc/interrupts printing */ |
197 | int arch_show_interrupts(struct seq_file *p, int prec) | |
1da177e4 | 198 | { |
6baa9b20 | 199 | int j; |
fd49bf48 | 200 | |
d6d04819 DH |
201 | #ifdef CONFIG_SMP |
202 | seq_printf(p, "RES: "); | |
203 | for_each_online_cpu(j) | |
204 | seq_printf(p, "%10u ", cpu_data(j).irq_resched_count); | |
205 | seq_printf(p, " IPI rescheduling interrupts\n"); | |
206 | seq_printf(p, "CAL: "); | |
207 | for_each_online_cpu(j) | |
208 | seq_printf(p, "%10u ", cpu_data(j).irq_call_count); | |
209 | seq_printf(p, " IPI function call interrupts\n"); | |
210 | #endif | |
6baa9b20 SR |
211 | seq_printf(p, "NMI: "); |
212 | for_each_online_cpu(j) | |
213 | seq_printf(p, "%10u ", cpu_data(j).counter); | |
214 | seq_printf(p, " Non-maskable interrupts\n"); | |
215 | return 0; | |
1da177e4 LT |
216 | } |
217 | ||
6baa9b20 | 218 | void handler_irq(unsigned int pil, struct pt_regs *regs) |
1da177e4 | 219 | { |
0d84438d | 220 | struct pt_regs *old_regs; |
6baa9b20 | 221 | struct irq_bucket *p; |
1da177e4 | 222 | |
6baa9b20 | 223 | BUG_ON(pil > 15); |
0d84438d | 224 | old_regs = set_irq_regs(regs); |
1da177e4 | 225 | irq_enter(); |
6baa9b20 SR |
226 | |
227 | p = irq_map[pil]; | |
228 | while (p) { | |
229 | struct irq_bucket *next = p->next; | |
230 | ||
231 | generic_handle_irq(p->irq); | |
232 | p = next; | |
233 | } | |
1da177e4 | 234 | irq_exit(); |
0d84438d | 235 | set_irq_regs(old_regs); |
1da177e4 LT |
236 | } |
237 | ||
0a808a31 | 238 | #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE) |
6baa9b20 | 239 | static unsigned int floppy_irq; |
1da177e4 | 240 | |
6baa9b20 | 241 | int sparc_floppy_request_irq(unsigned int irq, irq_handler_t irq_handler) |
1da177e4 | 242 | { |
1da177e4 | 243 | unsigned int cpu_irq; |
6baa9b20 SR |
244 | int err; |
245 | ||
1da177e4 | 246 | |
6baa9b20 SR |
247 | err = request_irq(irq, irq_handler, 0, "floppy", NULL); |
248 | if (err) | |
249 | return -1; | |
1da177e4 | 250 | |
6baa9b20 SR |
251 | /* Save for later use in floppy interrupt handler */ |
252 | floppy_irq = irq; | |
1da177e4 | 253 | |
6baa9b20 | 254 | cpu_irq = (irq & (NR_IRQS - 1)); |
1da177e4 LT |
255 | |
256 | /* Dork with trap table if we get this far. */ | |
257 | #define INSTANTIATE(table) \ | |
258 | table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_one = SPARC_RD_PSR_L0; \ | |
259 | table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_two = \ | |
6baa9b20 | 260 | SPARC_BRANCH((unsigned long) floppy_hardint, \ |
1da177e4 LT |
261 | (unsigned long) &table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_two);\ |
262 | table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_three = SPARC_RD_WIM_L3; \ | |
263 | table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_four = SPARC_NOP; | |
264 | ||
265 | INSTANTIATE(sparc_ttable) | |
b08b5c9c SR |
266 | |
267 | #if defined CONFIG_SMP | |
268 | if (sparc_cpu_model != sparc_leon) { | |
269 | struct tt_entry *trap_table; | |
270 | ||
271 | trap_table = &trapbase_cpu1; | |
272 | INSTANTIATE(trap_table) | |
273 | trap_table = &trapbase_cpu2; | |
274 | INSTANTIATE(trap_table) | |
275 | trap_table = &trapbase_cpu3; | |
276 | INSTANTIATE(trap_table) | |
277 | } | |
1da177e4 LT |
278 | #endif |
279 | #undef INSTANTIATE | |
280 | /* | |
281 | * XXX Correct thing whould be to flush only I- and D-cache lines | |
282 | * which contain the handler in question. But as of time of the | |
283 | * writing we have no CPU-neutral interface to fine-grained flushes. | |
284 | */ | |
285 | flush_cache_all(); | |
6baa9b20 | 286 | return 0; |
1da177e4 | 287 | } |
6baa9b20 | 288 | EXPORT_SYMBOL(sparc_floppy_request_irq); |
1da177e4 | 289 | |
fd49bf48 SR |
290 | /* |
291 | * These variables are used to access state from the assembler | |
0a808a31 DM |
292 | * interrupt handler, floppy_hardint, so we cannot put these in |
293 | * the floppy driver image because that would not work in the | |
294 | * modular case. | |
295 | */ | |
296 | volatile unsigned char *fdc_status; | |
297 | EXPORT_SYMBOL(fdc_status); | |
298 | ||
299 | char *pdma_vaddr; | |
300 | EXPORT_SYMBOL(pdma_vaddr); | |
301 | ||
302 | unsigned long pdma_size; | |
303 | EXPORT_SYMBOL(pdma_size); | |
304 | ||
305 | volatile int doing_pdma; | |
306 | EXPORT_SYMBOL(doing_pdma); | |
307 | ||
308 | char *pdma_base; | |
309 | EXPORT_SYMBOL(pdma_base); | |
310 | ||
311 | unsigned long pdma_areasize; | |
312 | EXPORT_SYMBOL(pdma_areasize); | |
313 | ||
6baa9b20 SR |
314 | /* Use the generic irq support to call floppy_interrupt |
315 | * which was setup using request_irq() in sparc_floppy_request_irq(). | |
316 | * We only have one floppy interrupt so we do not need to check | |
317 | * for additional handlers being wired up by irq_link() | |
318 | */ | |
0a808a31 DM |
319 | void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs) |
320 | { | |
321 | struct pt_regs *old_regs; | |
0a808a31 DM |
322 | |
323 | old_regs = set_irq_regs(regs); | |
0a808a31 | 324 | irq_enter(); |
6baa9b20 | 325 | generic_handle_irq(floppy_irq); |
0a808a31 | 326 | irq_exit(); |
0a808a31 | 327 | set_irq_regs(old_regs); |
0a808a31 | 328 | } |
0a808a31 DM |
329 | #endif |
330 | ||
1da177e4 LT |
331 | /* djhr |
332 | * This could probably be made indirect too and assigned in the CPU | |
333 | * bits of the code. That would be much nicer I think and would also | |
334 | * fit in with the idea of being able to tune your kernel for your machine | |
335 | * by removing unrequired machine and device support. | |
336 | * | |
337 | */ | |
338 | ||
339 | void __init init_IRQ(void) | |
340 | { | |
fd49bf48 | 341 | switch (sparc_cpu_model) { |
1da177e4 | 342 | case sun4m: |
1da177e4 | 343 | pcic_probe(); |
06010fb5 | 344 | if (pcic_present()) |
1da177e4 | 345 | sun4m_pci_init_IRQ(); |
06010fb5 SR |
346 | else |
347 | sun4m_init_IRQ(); | |
1da177e4 | 348 | break; |
fd49bf48 | 349 | |
1da177e4 LT |
350 | case sun4d: |
351 | sun4d_init_IRQ(); | |
352 | break; | |
353 | ||
0fd7ef1f KE |
354 | case sparc_leon: |
355 | leon_init_IRQ(); | |
356 | break; | |
357 | ||
1da177e4 | 358 | default: |
d1a78c32 | 359 | prom_printf("Cannot initialize IRQs on this Sun machine..."); |
1da177e4 LT |
360 | break; |
361 | } | |
1da177e4 LT |
362 | } |
363 |