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f5e706ad SR |
1 | #ifndef __SPARC64_PCI_H |
2 | #define __SPARC64_PCI_H | |
3 | ||
4 | #ifdef __KERNEL__ | |
5 | ||
6 | #include <linux/dma-mapping.h> | |
7 | ||
8 | /* Can be used to override the logic in pci_scan_bus for skipping | |
9 | * already-configured bus numbers - to be used for buggy BIOSes | |
10 | * or architectures with incomplete PCI setup by the loader. | |
11 | */ | |
12 | #define pcibios_assign_all_busses() 0 | |
f5e706ad SR |
13 | |
14 | #define PCIBIOS_MIN_IO 0UL | |
15 | #define PCIBIOS_MIN_MEM 0UL | |
16 | ||
17 | #define PCI_IRQ_NONE 0xffffffff | |
18 | ||
f5e706ad SR |
19 | static inline void pcibios_set_master(struct pci_dev *dev) |
20 | { | |
21 | /* No special bus mastering setup handling */ | |
22 | } | |
23 | ||
24 | static inline void pcibios_penalize_isa_irq(int irq, int active) | |
25 | { | |
26 | /* We don't do dynamic PCI IRQ allocation */ | |
27 | } | |
28 | ||
29 | /* The PCI address space does not equal the physical memory | |
30 | * address space. The networking and block device layers use | |
31 | * this boolean for bounce buffer decisions. | |
32 | */ | |
33 | #define PCI_DMA_BUS_IS_PHYS (0) | |
34 | ||
f5e706ad SR |
35 | /* PCI IOMMU mapping bypass support. */ |
36 | ||
37 | /* PCI 64-bit addressing works for all slots on all controller | |
38 | * types on sparc64. However, it requires that the device | |
39 | * can drive enough of the 64 bits. | |
40 | */ | |
41 | #define PCI64_REQUIRED_MASK (~(dma64_addr_t)0) | |
42 | #define PCI64_ADDR_BASE 0xfffc000000000000UL | |
43 | ||
f5e706ad SR |
44 | #ifdef CONFIG_PCI |
45 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, | |
46 | enum pci_dma_burst_strategy *strat, | |
47 | unsigned long *strategy_parameter) | |
48 | { | |
49 | unsigned long cacheline_size; | |
50 | u8 byte; | |
51 | ||
52 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); | |
53 | if (byte == 0) | |
54 | cacheline_size = 1024; | |
55 | else | |
56 | cacheline_size = (int) byte * 4; | |
57 | ||
58 | *strat = PCI_DMA_BURST_BOUNDARY; | |
59 | *strategy_parameter = cacheline_size; | |
60 | } | |
61 | #endif | |
62 | ||
63 | /* Return the index of the PCI controller for device PDEV. */ | |
64 | ||
65 | extern int pci_domain_nr(struct pci_bus *bus); | |
66 | static inline int pci_proc_domain(struct pci_bus *bus) | |
67 | { | |
68 | return 1; | |
69 | } | |
70 | ||
71 | /* Platform support for /proc/bus/pci/X/Y mmap()s. */ | |
72 | ||
73 | #define HAVE_PCI_MMAP | |
74 | #define HAVE_ARCH_PCI_GET_UNMAPPED_AREA | |
75 | #define get_pci_unmapped_area get_fb_unmapped_area | |
76 | ||
77 | extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
78 | enum pci_mmap_state mmap_state, | |
79 | int write_combine); | |
80 | ||
81 | extern void | |
82 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | |
83 | struct resource *res); | |
84 | ||
85 | extern void | |
86 | pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | |
87 | struct pci_bus_region *region); | |
88 | ||
f5e706ad SR |
89 | static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) |
90 | { | |
91 | return PCI_IRQ_NONE; | |
92 | } | |
93 | ||
94 | struct device_node; | |
95 | extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev); | |
96 | ||
97 | #define HAVE_ARCH_PCI_RESOURCE_TO_USER | |
98 | extern void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
99 | const struct resource *rsrc, | |
100 | resource_size_t *start, resource_size_t *end); | |
101 | #endif /* __KERNEL__ */ | |
102 | ||
103 | #endif /* __SPARC64_PCI_H */ |