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sh: sh4 scif pdata (sh7750/sh7760/sh4-202)
[linux-2.6-block.git] / arch / sh / kernel / cpu / sh4a / setup-sh7724.c
CommitLineData
0207a2ef
KM		 1/*
2 * SH7724 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * Based on SH7723 Setup
9 * Copyright (C) 2008 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/platform_device.h>
16#include <linux/init.h>
17#include <linux/serial.h>
18#include <linux/mm.h>
19#include <linux/serial_sci.h>
20#include <linux/uio_driver.h>
46a12f74 21#include <linux/sh_timer.h>
0207a2ef 22#include <linux/io.h>
da14909e
MD		 23#include <linux/notifier.h>
24#include <asm/suspend.h>
0207a2ef
KM		 25#include <asm/clock.h>
26#include <asm/mmzone.h>
593a0c89 27#include <cpu/sh7724.h>
0207a2ef
KM		 28
29/* Serial */
30static struct plat_sci_port sci_platform_data[] = {
31 {
32 .mapbase = 0xffe00000,
33 .flags = UPF_BOOT_AUTOCONF,
34 .type = PORT_SCIF,
35 .irqs = { 80, 80, 80, 80 },
3b226e15 36 .clk = "scif0",
0207a2ef
KM		 37 }, {
38 .mapbase = 0xffe10000,
39 .flags = UPF_BOOT_AUTOCONF,
40 .type = PORT_SCIF,
41 .irqs = { 81, 81, 81, 81 },
3b226e15 42 .clk = "scif1",
0207a2ef
KM		 43 }, {
44 .mapbase = 0xffe20000,
45 .flags = UPF_BOOT_AUTOCONF,
46 .type = PORT_SCIF,
47 .irqs = { 82, 82, 82, 82 },
3b226e15 48 .clk = "scif2",
0207a2ef
KM		 49 }, {
50 .mapbase = 0xa4e30000,
51 .flags = UPF_BOOT_AUTOCONF,
52 .type = PORT_SCIFA,
53 .irqs = { 56, 56, 56, 56 },
3b226e15 54 .clk = "scif3",
0207a2ef
KM		 55 }, {
56 .mapbase = 0xa4e40000,
57 .flags = UPF_BOOT_AUTOCONF,
58 .type = PORT_SCIFA,
59 .irqs = { 88, 88, 88, 88 },
3b226e15 60 .clk = "scif4",
0207a2ef
KM		 61 }, {
62 .mapbase = 0xa4e50000,
63 .flags = UPF_BOOT_AUTOCONF,
64 .type = PORT_SCIFA,
65 .irqs = { 109, 109, 109, 109 },
3b226e15 66 .clk = "scif5",
0207a2ef
KM		 67 }, {
68 .flags = 0,
69 }
70};
71
72static struct platform_device sci_device = {
73 .name = "sh-sci",
74 .id = -1,
75 .dev = {
76 .platform_data = sci_platform_data,
77 },
78};
79
80/* RTC */
81static struct resource rtc_resources[] = {
82 [0] = {
83 .start = 0xa465fec0,
84 .end = 0xa465fec0 + 0x58 - 1,
85 .flags = IORESOURCE_IO,
86 },
87 [1] = {
88 /* Period IRQ */
89 .start = 69,
90 .flags = IORESOURCE_IRQ,
91 },
92 [2] = {
93 /* Carry IRQ */
94 .start = 70,
95 .flags = IORESOURCE_IRQ,
96 },
97 [3] = {
98 /* Alarm IRQ */
99 .start = 68,
100 .flags = IORESOURCE_IRQ,
101 },
102};
103
104static struct platform_device rtc_device = {
105 .name = "sh-rtc",
106 .id = -1,
107 .num_resources = ARRAY_SIZE(rtc_resources),
108 .resource = rtc_resources,
593a0c89
MD		 109 .archdata = {
110 .hwblk_id = HWBLK_RTC,
111 },
0207a2ef
KM		 112};
113
40c7e8be
KM		 114/* I2C0 */
115static struct resource iic0_resources[] = {
116 [0] = {
117 .name = "IIC0",
118 .start = 0x04470000,
119 .end = 0x04470018 - 1,
120 .flags = IORESOURCE_MEM,
121 },
122 [1] = {
123 .start = 96,
124 .end = 99,
125 .flags = IORESOURCE_IRQ,
126 },
127};
128
129static struct platform_device iic0_device = {
130 .name = "i2c-sh_mobile",
131 .id = 0, /* "i2c0" clock */
132 .num_resources = ARRAY_SIZE(iic0_resources),
133 .resource = iic0_resources,
593a0c89
MD		 134 .archdata = {
135 .hwblk_id = HWBLK_IIC0,
136 },
40c7e8be
KM		 137};
138
139/* I2C1 */
140static struct resource iic1_resources[] = {
141 [0] = {
142 .name = "IIC1",
143 .start = 0x04750000,
144 .end = 0x04750018 - 1,
145 .flags = IORESOURCE_MEM,
146 },
147 [1] = {
148 .start = 92,
149 .end = 95,
150 .flags = IORESOURCE_IRQ,
151 },
152};
153
154static struct platform_device iic1_device = {
155 .name = "i2c-sh_mobile",
156 .id = 1, /* "i2c1" clock */
157 .num_resources = ARRAY_SIZE(iic1_resources),
158 .resource = iic1_resources,
593a0c89
MD		 159 .archdata = {
160 .hwblk_id = HWBLK_IIC1,
161 },
40c7e8be
KM		 162};
163
cd5b9ef7
KM		 164/* VPU */
165static struct uio_info vpu_platform_data = {
166 .name = "VPU5F",
167 .version = "0",
168 .irq = 60,
169};
170
171static struct resource vpu_resources[] = {
172 [0] = {
173 .name = "VPU",
174 .start = 0xfe900000,
175 .end = 0xfe902807,
176 .flags = IORESOURCE_MEM,
177 },
178 [1] = {
179 /* place holder for contiguous memory */
180 },
181};
182
183static struct platform_device vpu_device = {
184 .name = "uio_pdrv_genirq",
185 .id = 0,
186 .dev = {
187 .platform_data = &vpu_platform_data,
188 },
189 .resource = vpu_resources,
190 .num_resources = ARRAY_SIZE(vpu_resources),
593a0c89
MD		 191 .archdata = {
192 .hwblk_id = HWBLK_VPU,
193 },
cd5b9ef7
KM		 194};
195
ad95b78c
KM		 196/* VEU0 */
197static struct uio_info veu0_platform_data = {
198 .name = "VEU3F0",
199 .version = "0",
200 .irq = 83,
201};
202
203static struct resource veu0_resources[] = {
204 [0] = {
205 .name = "VEU3F0",
206 .start = 0xfe920000,
7e213481 207 .end = 0xfe9200cb,
ad95b78c
KM		 208 .flags = IORESOURCE_MEM,
209 },
210 [1] = {
211 /* place holder for contiguous memory */
212 },
213};
214
215static struct platform_device veu0_device = {
216 .name = "uio_pdrv_genirq",
217 .id = 1,
218 .dev = {
219 .platform_data = &veu0_platform_data,
220 },
221 .resource = veu0_resources,
222 .num_resources = ARRAY_SIZE(veu0_resources),
593a0c89
MD		 223 .archdata = {
224 .hwblk_id = HWBLK_VEU0,
225 },
ad95b78c
KM		 226};
227
228/* VEU1 */
229static struct uio_info veu1_platform_data = {
230 .name = "VEU3F1",
231 .version = "0",
232 .irq = 54,
233};
234
235static struct resource veu1_resources[] = {
236 [0] = {
237 .name = "VEU3F1",
238 .start = 0xfe924000,
7e213481 239 .end = 0xfe9240cb,
ad95b78c
KM		 240 .flags = IORESOURCE_MEM,
241 },
242 [1] = {
243 /* place holder for contiguous memory */
244 },
245};
246
247static struct platform_device veu1_device = {
248 .name = "uio_pdrv_genirq",
249 .id = 2,
250 .dev = {
251 .platform_data = &veu1_platform_data,
252 },
253 .resource = veu1_resources,
254 .num_resources = ARRAY_SIZE(veu1_resources),
593a0c89
MD		 255 .archdata = {
256 .hwblk_id = HWBLK_VEU1,
257 },
ad95b78c
KM		 258};
259
46a12f74 260static struct sh_timer_config cmt_platform_data = {
6a3395be
PM		 261 .name = "CMT",
262 .channel_offset = 0x60,
263 .timer_bit = 5,
264 .clk = "cmt0",
265 .clockevent_rating = 125,
266 .clocksource_rating = 200,
267};
268
269static struct resource cmt_resources[] = {
270 [0] = {
271 .name = "CMT",
272 .start = 0x044a0060,
273 .end = 0x044a006b,
274 .flags = IORESOURCE_MEM,
275 },
276 [1] = {
277 .start = 104,
278 .flags = IORESOURCE_IRQ,
279 },
280};
281
282static struct platform_device cmt_device = {
283 .name = "sh_cmt",
284 .id = 0,
285 .dev = {
286 .platform_data = &cmt_platform_data,
287 },
288 .resource = cmt_resources,
289 .num_resources = ARRAY_SIZE(cmt_resources),
593a0c89
MD		 290 .archdata = {
291 .hwblk_id = HWBLK_CMT,
292 },
6a3395be
PM		 293};
294
6a3501b6
MD		 295static struct sh_timer_config tmu0_platform_data = {
296 .name = "TMU0",
297 .channel_offset = 0x04,
298 .timer_bit = 0,
299 .clk = "tmu0",
300 .clockevent_rating = 200,
301};
302
303static struct resource tmu0_resources[] = {
304 [0] = {
305 .name = "TMU0",
306 .start = 0xffd80008,
307 .end = 0xffd80013,
308 .flags = IORESOURCE_MEM,
309 },
310 [1] = {
311 .start = 16,
312 .flags = IORESOURCE_IRQ,
313 },
314};
315
316static struct platform_device tmu0_device = {
317 .name = "sh_tmu",
318 .id = 0,
319 .dev = {
320 .platform_data = &tmu0_platform_data,
321 },
322 .resource = tmu0_resources,
323 .num_resources = ARRAY_SIZE(tmu0_resources),
593a0c89
MD		 324 .archdata = {
325 .hwblk_id = HWBLK_TMU0,
326 },
6a3501b6
MD		 327};
328
329static struct sh_timer_config tmu1_platform_data = {
330 .name = "TMU1",
331 .channel_offset = 0x10,
332 .timer_bit = 1,
333 .clk = "tmu0",
334 .clocksource_rating = 200,
335};
336
337static struct resource tmu1_resources[] = {
338 [0] = {
339 .name = "TMU1",
340 .start = 0xffd80014,
341 .end = 0xffd8001f,
342 .flags = IORESOURCE_MEM,
343 },
344 [1] = {
345 .start = 17,
346 .flags = IORESOURCE_IRQ,
347 },
348};
349
350static struct platform_device tmu1_device = {
351 .name = "sh_tmu",
352 .id = 1,
353 .dev = {
354 .platform_data = &tmu1_platform_data,
355 },
356 .resource = tmu1_resources,
357 .num_resources = ARRAY_SIZE(tmu1_resources),
593a0c89
MD		 358 .archdata = {
359 .hwblk_id = HWBLK_TMU0,
360 },
6a3501b6
MD		 361};
362
363static struct sh_timer_config tmu2_platform_data = {
364 .name = "TMU2",
365 .channel_offset = 0x1c,
366 .timer_bit = 2,
367 .clk = "tmu0",
368};
369
370static struct resource tmu2_resources[] = {
371 [0] = {
372 .name = "TMU2",
373 .start = 0xffd80020,
374 .end = 0xffd8002b,
375 .flags = IORESOURCE_MEM,
376 },
377 [1] = {
378 .start = 18,
379 .flags = IORESOURCE_IRQ,
380 },
381};
382
383static struct platform_device tmu2_device = {
384 .name = "sh_tmu",
385 .id = 2,
386 .dev = {
387 .platform_data = &tmu2_platform_data,
388 },
389 .resource = tmu2_resources,
390 .num_resources = ARRAY_SIZE(tmu2_resources),
593a0c89
MD		 391 .archdata = {
392 .hwblk_id = HWBLK_TMU0,
393 },
6a3501b6
MD		 394};
395
396
397static struct sh_timer_config tmu3_platform_data = {
398 .name = "TMU3",
399 .channel_offset = 0x04,
400 .timer_bit = 0,
401 .clk = "tmu1",
402};
403
404static struct resource tmu3_resources[] = {
405 [0] = {
406 .name = "TMU3",
407 .start = 0xffd90008,
408 .end = 0xffd90013,
409 .flags = IORESOURCE_MEM,
410 },
411 [1] = {
412 .start = 57,
413 .flags = IORESOURCE_IRQ,
414 },
415};
416
417static struct platform_device tmu3_device = {
418 .name = "sh_tmu",
419 .id = 3,
420 .dev = {
421 .platform_data = &tmu3_platform_data,
422 },
423 .resource = tmu3_resources,
424 .num_resources = ARRAY_SIZE(tmu3_resources),
593a0c89
MD		 425 .archdata = {
426 .hwblk_id = HWBLK_TMU1,
427 },
6a3501b6
MD		 428};
429
430static struct sh_timer_config tmu4_platform_data = {
431 .name = "TMU4",
432 .channel_offset = 0x10,
433 .timer_bit = 1,
434 .clk = "tmu1",
435};
436
437static struct resource tmu4_resources[] = {
438 [0] = {
439 .name = "TMU4",
440 .start = 0xffd90014,
441 .end = 0xffd9001f,
442 .flags = IORESOURCE_MEM,
443 },
444 [1] = {
445 .start = 58,
446 .flags = IORESOURCE_IRQ,
447 },
448};
449
450static struct platform_device tmu4_device = {
451 .name = "sh_tmu",
452 .id = 4,
453 .dev = {
454 .platform_data = &tmu4_platform_data,
455 },
456 .resource = tmu4_resources,
457 .num_resources = ARRAY_SIZE(tmu4_resources),
593a0c89
MD		 458 .archdata = {
459 .hwblk_id = HWBLK_TMU1,
460 },
6a3501b6
MD		 461};
462
463static struct sh_timer_config tmu5_platform_data = {
464 .name = "TMU5",
465 .channel_offset = 0x1c,
466 .timer_bit = 2,
467 .clk = "tmu1",
468};
469
470static struct resource tmu5_resources[] = {
471 [0] = {
472 .name = "TMU5",
473 .start = 0xffd90020,
474 .end = 0xffd9002b,
475 .flags = IORESOURCE_MEM,
476 },
477 [1] = {
478 .start = 57,
479 .flags = IORESOURCE_IRQ,
480 },
481};
482
483static struct platform_device tmu5_device = {
484 .name = "sh_tmu",
485 .id = 5,
486 .dev = {
487 .platform_data = &tmu5_platform_data,
488 },
489 .resource = tmu5_resources,
490 .num_resources = ARRAY_SIZE(tmu5_resources),
593a0c89
MD		 491 .archdata = {
492 .hwblk_id = HWBLK_TMU1,
493 },
6a3501b6
MD		 494};
495
f168dd00
KM		 496/* JPU */
497static struct uio_info jpu_platform_data = {
498 .name = "JPU",
499 .version = "0",
500 .irq = 27,
501};
502
503static struct resource jpu_resources[] = {
504 [0] = {
505 .name = "JPU",
506 .start = 0xfe980000,
507 .end = 0xfe9902d3,
508 .flags = IORESOURCE_MEM,
509 },
510 [1] = {
511 /* place holder for contiguous memory */
512 },
513};
514
515static struct platform_device jpu_device = {
516 .name = "uio_pdrv_genirq",
517 .id = 3,
518 .dev = {
519 .platform_data = &jpu_platform_data,
520 },
521 .resource = jpu_resources,
522 .num_resources = ARRAY_SIZE(jpu_resources),
593a0c89
MD		 523 .archdata = {
524 .hwblk_id = HWBLK_JPU,
525 },
f168dd00
KM		 526};
527
2de33923
KM		 528/* SPU2DSP0 */
529static struct uio_info spu0_platform_data = {
530 .name = "SPU2DSP0",
531 .version = "0",
532 .irq = 86,
533};
534
535static struct resource spu0_resources[] = {
536 [0] = {
537 .name = "SPU2DSP0",
538 .start = 0xFE200000,
539 .end = 0xFE2FFFFF,
540 .flags = IORESOURCE_MEM,
541 },
542 [1] = {
543 /* place holder for contiguous memory */
544 },
545};
546
547static struct platform_device spu0_device = {
548 .name = "uio_pdrv_genirq",
549 .id = 4,
550 .dev = {
551 .platform_data = &spu0_platform_data,
552 },
553 .resource = spu0_resources,
554 .num_resources = ARRAY_SIZE(spu0_resources),
555 .archdata = {
556 .hwblk_id = HWBLK_SPU,
557 },
558};
559
560/* SPU2DSP1 */
561static struct uio_info spu1_platform_data = {
562 .name = "SPU2DSP1",
563 .version = "0",
564 .irq = 87,
565};
566
567static struct resource spu1_resources[] = {
568 [0] = {
569 .name = "SPU2DSP1",
570 .start = 0xFE300000,
571 .end = 0xFE3FFFFF,
572 .flags = IORESOURCE_MEM,
573 },
574 [1] = {
575 /* place holder for contiguous memory */
576 },
577};
578
579static struct platform_device spu1_device = {
580 .name = "uio_pdrv_genirq",
581 .id = 5,
582 .dev = {
583 .platform_data = &spu1_platform_data,
584 },
585 .resource = spu1_resources,
586 .num_resources = ARRAY_SIZE(spu1_resources),
587 .archdata = {
588 .hwblk_id = HWBLK_SPU,
589 },
590};
591
0207a2ef 592static struct platform_device *sh7724_devices[] __initdata = {
6a3395be 593 &cmt_device,
6a3501b6
MD		 594 &tmu0_device,
595 &tmu1_device,
596 &tmu2_device,
597 &tmu3_device,
598 &tmu4_device,
599 &tmu5_device,
0207a2ef
KM		 600 &sci_device,
601 &rtc_device,
40c7e8be
KM		 602 &iic0_device,
603 &iic1_device,
cd5b9ef7 604 &vpu_device,
ad95b78c
KM		 605 &veu0_device,
606 &veu1_device,
f168dd00 607 &jpu_device,
2de33923
KM		 608 &spu0_device,
609 &spu1_device,
0207a2ef
KM		 610};
611
612static int __init sh7724_devices_setup(void)
613{
cd5b9ef7 614 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
ad95b78c
KM		 615 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
616 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
f168dd00 617 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
2de33923
KM		 618 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
619 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
0207a2ef
KM		 620
621 return platform_add_devices(sh7724_devices,
622 ARRAY_SIZE(sh7724_devices));
623}
955c9863 624arch_initcall(sh7724_devices_setup);
0207a2ef 625
8fb2bae4
PM		 626static struct platform_device *sh7724_early_devices[] __initdata = {
627 &cmt_device,
6a3501b6
MD		 628 &tmu0_device,
629 &tmu1_device,
630 &tmu2_device,
631 &tmu3_device,
632 &tmu4_device,
633 &tmu5_device,
8fb2bae4
PM		 634};
635
636void __init plat_early_device_setup(void)
637{
638 early_platform_add_devices(sh7724_early_devices,
639 ARRAY_SIZE(sh7724_early_devices));
640}
641
b4bd9eb0
KM		 642#define RAMCR_CACHE_L2FC 0x0002
643#define RAMCR_CACHE_L2E 0x0001
644#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
645void __uses_jump_to_uncached l2_cache_init(void)
646{
647 /* Enable L2 cache */
648 ctrl_outl(L2_CACHE_ENABLE, RAMCR);
649}
650
0207a2ef
KM		 651enum {
652 UNUSED = 0,
653
654 /* interrupt sources */
655 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
656 HUDI,
657 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
c5eeff1f 658 _2DG_TRI, _2DG_INI, _2DG_CEI,
0207a2ef 659 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
c5eeff1f
KM		 660 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
661 SCIFA3,
662 VPU,
663 TPU,
664 CEU1,
665 BEU1,
666 USB0, USB1,
0207a2ef
KM		 667 ATAPI,
668 RTC_ATI, RTC_PRI, RTC_CUI,
669 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
670 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
c5eeff1f 671 KEYSC,
0207a2ef 672 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
c5eeff1f 673 VEU0,
0207a2ef
KM		 674 MSIOF_MSIOFI0, MSIOF_MSIOFI1,
675 SPU_SPUI0, SPU_SPUI1,
c5eeff1f
KM		 676 SCIFA4,
677 ICB,
0207a2ef
KM		 678 ETHI,
679 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
680 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
c5eeff1f
KM		 681 SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3,
682 CMT,
683 TSIF,
684 FSI,
685 SCIFA5,
0207a2ef 686 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
c5eeff1f 687 IRDA,
0207a2ef 688 SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
c5eeff1f
KM		 689 JPU,
690 _2DDMAC,
691 MMC_MMC2I, MMC_MMC3I,
692 LCDC,
0207a2ef
KM		 693 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
694
695 /* interrupt groups */
c5eeff1f
KM		 696 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
697 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
0207a2ef
KM		 698};
699
700static struct intc_vect vectors[] __initdata = {
701 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
702 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
703 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
704 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
705
706 INTC_VECT(DMAC1A_DEI0, 0x700),
707 INTC_VECT(DMAC1A_DEI1, 0x720),
708 INTC_VECT(DMAC1A_DEI2, 0x740),
709 INTC_VECT(DMAC1A_DEI3, 0x760),
710
711 INTC_VECT(_2DG_TRI, 0x780),
712 INTC_VECT(_2DG_INI, 0x7A0),
713 INTC_VECT(_2DG_CEI, 0x7C0),
0207a2ef
KM		 714
715 INTC_VECT(DMAC0A_DEI0, 0x800),
716 INTC_VECT(DMAC0A_DEI1, 0x820),
717 INTC_VECT(DMAC0A_DEI2, 0x840),
718 INTC_VECT(DMAC0A_DEI3, 0x860),
719
c5eeff1f
KM		 720 INTC_VECT(VIO_CEU0, 0x880),
721 INTC_VECT(VIO_BEU0, 0x8A0),
722 INTC_VECT(VIO_VEU1, 0x8C0),
723 INTC_VECT(VIO_VOU, 0x8E0),
0207a2ef 724
c5eeff1f
KM		 725 INTC_VECT(SCIFA3, 0x900),
726 INTC_VECT(VPU, 0x980),
727 INTC_VECT(TPU, 0x9A0),
728 INTC_VECT(CEU1, 0x9E0),
729 INTC_VECT(BEU1, 0xA00),
730 INTC_VECT(USB0, 0xA20),
731 INTC_VECT(USB1, 0xA40),
732 INTC_VECT(ATAPI, 0xA60),
0207a2ef
KM		 733
734 INTC_VECT(RTC_ATI, 0xA80),
735 INTC_VECT(RTC_PRI, 0xAA0),
736 INTC_VECT(RTC_CUI, 0xAC0),
737
738 INTC_VECT(DMAC1B_DEI4, 0xB00),
739 INTC_VECT(DMAC1B_DEI5, 0xB20),
740 INTC_VECT(DMAC1B_DADERR, 0xB40),
741
742 INTC_VECT(DMAC0B_DEI4, 0xB80),
743 INTC_VECT(DMAC0B_DEI5, 0xBA0),
744 INTC_VECT(DMAC0B_DADERR, 0xBC0),
745
c5eeff1f 746 INTC_VECT(KEYSC, 0xBE0),
0207a2ef
KM		 747 INTC_VECT(SCIF_SCIF0, 0xC00),
748 INTC_VECT(SCIF_SCIF1, 0xC20),
749 INTC_VECT(SCIF_SCIF2, 0xC40),
c5eeff1f 750 INTC_VECT(VEU0, 0xC60),
0207a2ef
KM		 751 INTC_VECT(MSIOF_MSIOFI0, 0xC80),
752 INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
753 INTC_VECT(SPU_SPUI0, 0xCC0),
754 INTC_VECT(SPU_SPUI1, 0xCE0),
c5eeff1f 755 INTC_VECT(SCIFA4, 0xD00),
0207a2ef 756
c5eeff1f 757 INTC_VECT(ICB, 0xD20),
0207a2ef
KM		 758 INTC_VECT(ETHI, 0xD60),
759
760 INTC_VECT(I2C1_ALI, 0xD80),
761 INTC_VECT(I2C1_TACKI, 0xDA0),
762 INTC_VECT(I2C1_WAITI, 0xDC0),
763 INTC_VECT(I2C1_DTEI, 0xDE0),
764
765 INTC_VECT(I2C0_ALI, 0xE00),
766 INTC_VECT(I2C0_TACKI, 0xE20),
767 INTC_VECT(I2C0_WAITI, 0xE40),
768 INTC_VECT(I2C0_DTEI, 0xE60),
769
770 INTC_VECT(SDHI0_SDHII0, 0xE80),
771 INTC_VECT(SDHI0_SDHII1, 0xEA0),
772 INTC_VECT(SDHI0_SDHII2, 0xEC0),
c5eeff1f 773 INTC_VECT(SDHI0_SDHII3, 0xEE0),
0207a2ef 774
c5eeff1f
KM		 775 INTC_VECT(CMT, 0xF00),
776 INTC_VECT(TSIF, 0xF20),
777 INTC_VECT(FSI, 0xF80),
778 INTC_VECT(SCIFA5, 0xFA0),
0207a2ef
KM		 779
780 INTC_VECT(TMU0_TUNI0, 0x400),
781 INTC_VECT(TMU0_TUNI1, 0x420),
782 INTC_VECT(TMU0_TUNI2, 0x440),
783
c5eeff1f 784 INTC_VECT(IRDA, 0x480),
0207a2ef
KM		 785
786 INTC_VECT(SDHI1_SDHII0, 0x4E0),
787 INTC_VECT(SDHI1_SDHII1, 0x500),
788 INTC_VECT(SDHI1_SDHII2, 0x520),
789
c5eeff1f
KM		 790 INTC_VECT(JPU, 0x560),
791 INTC_VECT(_2DDMAC, 0x4A0),
0207a2ef 792
c5eeff1f
KM		 793 INTC_VECT(MMC_MMC2I, 0x5A0),
794 INTC_VECT(MMC_MMC3I, 0x5C0),
0207a2ef 795
c5eeff1f 796 INTC_VECT(LCDC, 0xF40),
0207a2ef
KM		 797
798 INTC_VECT(TMU1_TUNI0, 0x920),
799 INTC_VECT(TMU1_TUNI1, 0x940),
800 INTC_VECT(TMU1_TUNI2, 0x960),
801};
802
803static struct intc_group groups[] __initdata = {
804 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
c5eeff1f 805 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
0207a2ef 806 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
c5eeff1f
KM		 807 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
808 INTC_GROUP(USB, USB0, USB1),
0207a2ef
KM		 809 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
810 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
811 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
812 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
813 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
c5eeff1f 814 INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3),
0207a2ef
KM		 815 INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
816 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
c5eeff1f 817 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
0207a2ef
KM		 818};
819
0207a2ef
KM		 820static struct intc_mask_reg mask_registers[] __initdata = {
821 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
822 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
c5eeff1f 823 0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
0207a2ef 824 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
c5eeff1f 825 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
0207a2ef
KM		 826 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
827 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
c5eeff1f 828 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
0207a2ef
KM		 829 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
830 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
c5eeff1f 831 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
0207a2ef
KM		 832 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
833 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
c5eeff1f 834 JPU, 0, 0, LCDC } },
0207a2ef 835 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
c5eeff1f
KM		 836 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
837 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
0207a2ef 838 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
c5eeff1f
KM		 839 { 0, 0, ICB, SCIFA4,
840 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
0207a2ef
KM		 841 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
842 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
843 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
844 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
c5eeff1f
KM		 845 { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
846 0, 0, SCIFA5, FSI } },
0207a2ef 847 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
c5eeff1f 848 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
0207a2ef
KM		 849 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
850 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
c5eeff1f 851 0, RTC_CUI, RTC_PRI, RTC_ATI } },
0207a2ef 852 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
c5eeff1f
KM		 853 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
854 0, TPU, 0, TSIF } },
0207a2ef 855 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
c5eeff1f 856 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
0207a2ef
KM		 857 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
858 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
859};
860
861static struct intc_prio_reg prio_registers[] __initdata = {
862 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
c5eeff1f
KM		 863 TMU0_TUNI2, IRDA } },
864 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
0207a2ef
KM		 865 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
866 TMU1_TUNI2, SPU } },
c5eeff1f
KM		 867 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
868 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
869 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
0207a2ef 870 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
c5eeff1f 871 SCIF_SCIF2, VEU0 } },
0207a2ef
KM		 872 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
873 I2C1, I2C0 } },
c5eeff1f
KM		 874 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
875 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
876 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
877 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
0207a2ef
KM		 878 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
879 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
880};
881
882static struct intc_sense_reg sense_registers[] __initdata = {
883 { 0xa414001c, 16, 2, /* ICR1 */
884 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
885};
886
887static struct intc_mask_reg ack_registers[] __initdata = {
888 { 0xa4140024, 0, 8, /* INTREQ00 */
889 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
890};
891
892static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
893 mask_registers, prio_registers, sense_registers,
894 ack_registers);
895
896void __init plat_irq_setup(void)
897{
898 register_intc_controller(&intc_desc);
899}
da14909e
MD		 900
901static struct {
902 /* BSC */
903 unsigned long mmselr;
904 unsigned long cs0bcr;
905 unsigned long cs4bcr;
906 unsigned long cs5abcr;
907 unsigned long cs5bbcr;
908 unsigned long cs6abcr;
909 unsigned long cs6bbcr;
910 unsigned long cs4wcr;
911 unsigned long cs5awcr;
912 unsigned long cs5bwcr;
913 unsigned long cs6awcr;
914 unsigned long cs6bwcr;
915 /* INTC */
916 unsigned short ipra;
917 unsigned short iprb;
918 unsigned short iprc;
919 unsigned short iprd;
920 unsigned short ipre;
921 unsigned short iprf;
922 unsigned short iprg;
923 unsigned short iprh;
924 unsigned short ipri;
925 unsigned short iprj;
926 unsigned short iprk;
927 unsigned short iprl;
928 unsigned char imr0;
929 unsigned char imr1;
930 unsigned char imr2;
931 unsigned char imr3;
932 unsigned char imr4;
933 unsigned char imr5;
934 unsigned char imr6;
935 unsigned char imr7;
936 unsigned char imr8;
937 unsigned char imr9;
938 unsigned char imr10;
939 unsigned char imr11;
940 unsigned char imr12;
c4b973f5
MD		 941 /* RWDT */
942 unsigned short rwtcnt;
943 unsigned short rwtcsr;
2ebe0ff7
MD		 944 /* CPG */
945 unsigned long irdaclk;
946 unsigned long spuclk;
da14909e
MD		 947} sh7724_rstandby_state;
948
949static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
950 unsigned long flags, void *unused)
951{
952 if (!(flags & SUSP_SH_RSTANDBY))
953 return NOTIFY_DONE;
954
955 /* BCR */
956 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
957 sh7724_rstandby_state.mmselr |= 0xa5a50000;
958 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
959 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
960 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
961 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
962 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
963 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
964 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
965 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
966 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
967 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
968 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
969
970 /* INTC */
971 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
972 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
973 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
974 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
975 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
976 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
977 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
978 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
979 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
980 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
981 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
982 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
983 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
984 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
985 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
986 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
987 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
988 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
989 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
990 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
991 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
992 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
993 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
994 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
995 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
996
c4b973f5
MD		 997 /* RWDT */
998 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
999 sh7724_rstandby_state.rwtcnt |= 0x5a00;
1000 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
1001 sh7724_rstandby_state.rwtcsr |= 0xa500;
1002 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1003
2ebe0ff7
MD		 1004 /* CPG */
1005 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
1006 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
1007
da14909e
MD		 1008 return NOTIFY_DONE;
1009}
1010
1011static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1012 unsigned long flags, void *unused)
1013{
1014 if (!(flags & SUSP_SH_RSTANDBY))
1015 return NOTIFY_DONE;
1016
1017 /* BCR */
1018 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
1019 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
1020 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
1021 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
1022 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
1023 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
1024 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
1025 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
1026 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
1027 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
1028 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
1029 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
1030
1031 /* INTC */
1032 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
1033 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
1034 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
1035 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
1036 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
1037 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
1038 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
1039 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
1040 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
1041 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
1042 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
1043 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
1044 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
1045 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
1046 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
1047 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
1048 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
1049 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
1050 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
1051 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
1052 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
1053 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
1054 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
1055 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
1056 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
1057
c4b973f5
MD		 1058 /* RWDT */
1059 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
1060 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
1061
2ebe0ff7
MD		 1062 /* CPG */
1063 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
1064 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
1065
da14909e
MD		 1066 return NOTIFY_DONE;
1067}
1068
1069static struct notifier_block sh7724_pre_sleep_notifier = {
1070 .notifier_call = sh7724_pre_sleep_notifier_call,
1071 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1072};
1073
1074static struct notifier_block sh7724_post_sleep_notifier = {
1075 .notifier_call = sh7724_post_sleep_notifier_call,
1076 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1077};
1078
1079static int __init sh7724_sleep_setup(void)
1080{
1081 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1082 &sh7724_pre_sleep_notifier);
1083
1084 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1085 &sh7724_post_sleep_notifier);
1086 return 0;
1087}
1088arch_initcall(sh7724_sleep_setup);
1089
Linux 6.x block layer and io_uring tree(s)