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i2c: change i2c-sh_mobile.c module_init() to subsys_initcall()
[linux-2.6-block.git] / arch / sh / kernel / cpu / sh4a / setup-sh7724.c
CommitLineData
0207a2ef
KM		 1/*
2 * SH7724 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * Based on SH7723 Setup
9 * Copyright (C) 2008 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/platform_device.h>
16#include <linux/init.h>
17#include <linux/serial.h>
18#include <linux/mm.h>
19#include <linux/serial_sci.h>
20#include <linux/uio_driver.h>
46a12f74 21#include <linux/sh_timer.h>
0207a2ef
KM		 22#include <linux/io.h>
23#include <asm/clock.h>
24#include <asm/mmzone.h>
25
26/* Serial */
27static struct plat_sci_port sci_platform_data[] = {
28 {
29 .mapbase = 0xffe00000,
30 .flags = UPF_BOOT_AUTOCONF,
31 .type = PORT_SCIF,
32 .irqs = { 80, 80, 80, 80 },
3b226e15 33 .clk = "scif0",
0207a2ef
KM		 34 }, {
35 .mapbase = 0xffe10000,
36 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF,
38 .irqs = { 81, 81, 81, 81 },
3b226e15 39 .clk = "scif1",
0207a2ef
KM		 40 }, {
41 .mapbase = 0xffe20000,
42 .flags = UPF_BOOT_AUTOCONF,
43 .type = PORT_SCIF,
44 .irqs = { 82, 82, 82, 82 },
3b226e15 45 .clk = "scif2",
0207a2ef
KM		 46 }, {
47 .mapbase = 0xa4e30000,
48 .flags = UPF_BOOT_AUTOCONF,
49 .type = PORT_SCIFA,
50 .irqs = { 56, 56, 56, 56 },
3b226e15 51 .clk = "scif3",
0207a2ef
KM		 52 }, {
53 .mapbase = 0xa4e40000,
54 .flags = UPF_BOOT_AUTOCONF,
55 .type = PORT_SCIFA,
56 .irqs = { 88, 88, 88, 88 },
3b226e15 57 .clk = "scif4",
0207a2ef
KM		 58 }, {
59 .mapbase = 0xa4e50000,
60 .flags = UPF_BOOT_AUTOCONF,
61 .type = PORT_SCIFA,
62 .irqs = { 109, 109, 109, 109 },
3b226e15 63 .clk = "scif5",
0207a2ef
KM		 64 }, {
65 .flags = 0,
66 }
67};
68
69static struct platform_device sci_device = {
70 .name = "sh-sci",
71 .id = -1,
72 .dev = {
73 .platform_data = sci_platform_data,
74 },
75};
76
77/* RTC */
78static struct resource rtc_resources[] = {
79 [0] = {
80 .start = 0xa465fec0,
81 .end = 0xa465fec0 + 0x58 - 1,
82 .flags = IORESOURCE_IO,
83 },
84 [1] = {
85 /* Period IRQ */
86 .start = 69,
87 .flags = IORESOURCE_IRQ,
88 },
89 [2] = {
90 /* Carry IRQ */
91 .start = 70,
92 .flags = IORESOURCE_IRQ,
93 },
94 [3] = {
95 /* Alarm IRQ */
96 .start = 68,
97 .flags = IORESOURCE_IRQ,
98 },
99};
100
101static struct platform_device rtc_device = {
102 .name = "sh-rtc",
103 .id = -1,
104 .num_resources = ARRAY_SIZE(rtc_resources),
105 .resource = rtc_resources,
106};
107
40c7e8be
KM		 108/* I2C0 */
109static struct resource iic0_resources[] = {
110 [0] = {
111 .name = "IIC0",
112 .start = 0x04470000,
113 .end = 0x04470018 - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 [1] = {
117 .start = 96,
118 .end = 99,
119 .flags = IORESOURCE_IRQ,
120 },
121};
122
123static struct platform_device iic0_device = {
124 .name = "i2c-sh_mobile",
125 .id = 0, /* "i2c0" clock */
126 .num_resources = ARRAY_SIZE(iic0_resources),
127 .resource = iic0_resources,
128};
129
130/* I2C1 */
131static struct resource iic1_resources[] = {
132 [0] = {
133 .name = "IIC1",
134 .start = 0x04750000,
135 .end = 0x04750018 - 1,
136 .flags = IORESOURCE_MEM,
137 },
138 [1] = {
139 .start = 92,
140 .end = 95,
141 .flags = IORESOURCE_IRQ,
142 },
143};
144
145static struct platform_device iic1_device = {
146 .name = "i2c-sh_mobile",
147 .id = 1, /* "i2c1" clock */
148 .num_resources = ARRAY_SIZE(iic1_resources),
149 .resource = iic1_resources,
150};
151
cd5b9ef7
KM		 152/* VPU */
153static struct uio_info vpu_platform_data = {
154 .name = "VPU5F",
155 .version = "0",
156 .irq = 60,
157};
158
159static struct resource vpu_resources[] = {
160 [0] = {
161 .name = "VPU",
162 .start = 0xfe900000,
163 .end = 0xfe902807,
164 .flags = IORESOURCE_MEM,
165 },
166 [1] = {
167 /* place holder for contiguous memory */
168 },
169};
170
171static struct platform_device vpu_device = {
172 .name = "uio_pdrv_genirq",
173 .id = 0,
174 .dev = {
175 .platform_data = &vpu_platform_data,
176 },
177 .resource = vpu_resources,
178 .num_resources = ARRAY_SIZE(vpu_resources),
179};
180
ad95b78c
KM		 181/* VEU0 */
182static struct uio_info veu0_platform_data = {
183 .name = "VEU3F0",
184 .version = "0",
185 .irq = 83,
186};
187
188static struct resource veu0_resources[] = {
189 [0] = {
190 .name = "VEU3F0",
191 .start = 0xfe920000,
192 .end = 0xfe9200cb - 1,
193 .flags = IORESOURCE_MEM,
194 },
195 [1] = {
196 /* place holder for contiguous memory */
197 },
198};
199
200static struct platform_device veu0_device = {
201 .name = "uio_pdrv_genirq",
202 .id = 1,
203 .dev = {
204 .platform_data = &veu0_platform_data,
205 },
206 .resource = veu0_resources,
207 .num_resources = ARRAY_SIZE(veu0_resources),
208};
209
210/* VEU1 */
211static struct uio_info veu1_platform_data = {
212 .name = "VEU3F1",
213 .version = "0",
214 .irq = 54,
215};
216
217static struct resource veu1_resources[] = {
218 [0] = {
219 .name = "VEU3F1",
220 .start = 0xfe924000,
221 .end = 0xfe9240cb - 1,
222 .flags = IORESOURCE_MEM,
223 },
224 [1] = {
225 /* place holder for contiguous memory */
226 },
227};
228
229static struct platform_device veu1_device = {
230 .name = "uio_pdrv_genirq",
231 .id = 2,
232 .dev = {
233 .platform_data = &veu1_platform_data,
234 },
235 .resource = veu1_resources,
236 .num_resources = ARRAY_SIZE(veu1_resources),
237};
238
46a12f74 239static struct sh_timer_config cmt_platform_data = {
6a3395be
PM		 240 .name = "CMT",
241 .channel_offset = 0x60,
242 .timer_bit = 5,
243 .clk = "cmt0",
244 .clockevent_rating = 125,
245 .clocksource_rating = 200,
246};
247
248static struct resource cmt_resources[] = {
249 [0] = {
250 .name = "CMT",
251 .start = 0x044a0060,
252 .end = 0x044a006b,
253 .flags = IORESOURCE_MEM,
254 },
255 [1] = {
256 .start = 104,
257 .flags = IORESOURCE_IRQ,
258 },
259};
260
261static struct platform_device cmt_device = {
262 .name = "sh_cmt",
263 .id = 0,
264 .dev = {
265 .platform_data = &cmt_platform_data,
266 },
267 .resource = cmt_resources,
268 .num_resources = ARRAY_SIZE(cmt_resources),
269};
270
6a3501b6
MD		 271static struct sh_timer_config tmu0_platform_data = {
272 .name = "TMU0",
273 .channel_offset = 0x04,
274 .timer_bit = 0,
275 .clk = "tmu0",
276 .clockevent_rating = 200,
277};
278
279static struct resource tmu0_resources[] = {
280 [0] = {
281 .name = "TMU0",
282 .start = 0xffd80008,
283 .end = 0xffd80013,
284 .flags = IORESOURCE_MEM,
285 },
286 [1] = {
287 .start = 16,
288 .flags = IORESOURCE_IRQ,
289 },
290};
291
292static struct platform_device tmu0_device = {
293 .name = "sh_tmu",
294 .id = 0,
295 .dev = {
296 .platform_data = &tmu0_platform_data,
297 },
298 .resource = tmu0_resources,
299 .num_resources = ARRAY_SIZE(tmu0_resources),
300};
301
302static struct sh_timer_config tmu1_platform_data = {
303 .name = "TMU1",
304 .channel_offset = 0x10,
305 .timer_bit = 1,
306 .clk = "tmu0",
307 .clocksource_rating = 200,
308};
309
310static struct resource tmu1_resources[] = {
311 [0] = {
312 .name = "TMU1",
313 .start = 0xffd80014,
314 .end = 0xffd8001f,
315 .flags = IORESOURCE_MEM,
316 },
317 [1] = {
318 .start = 17,
319 .flags = IORESOURCE_IRQ,
320 },
321};
322
323static struct platform_device tmu1_device = {
324 .name = "sh_tmu",
325 .id = 1,
326 .dev = {
327 .platform_data = &tmu1_platform_data,
328 },
329 .resource = tmu1_resources,
330 .num_resources = ARRAY_SIZE(tmu1_resources),
331};
332
333static struct sh_timer_config tmu2_platform_data = {
334 .name = "TMU2",
335 .channel_offset = 0x1c,
336 .timer_bit = 2,
337 .clk = "tmu0",
338};
339
340static struct resource tmu2_resources[] = {
341 [0] = {
342 .name = "TMU2",
343 .start = 0xffd80020,
344 .end = 0xffd8002b,
345 .flags = IORESOURCE_MEM,
346 },
347 [1] = {
348 .start = 18,
349 .flags = IORESOURCE_IRQ,
350 },
351};
352
353static struct platform_device tmu2_device = {
354 .name = "sh_tmu",
355 .id = 2,
356 .dev = {
357 .platform_data = &tmu2_platform_data,
358 },
359 .resource = tmu2_resources,
360 .num_resources = ARRAY_SIZE(tmu2_resources),
361};
362
363
364static struct sh_timer_config tmu3_platform_data = {
365 .name = "TMU3",
366 .channel_offset = 0x04,
367 .timer_bit = 0,
368 .clk = "tmu1",
369};
370
371static struct resource tmu3_resources[] = {
372 [0] = {
373 .name = "TMU3",
374 .start = 0xffd90008,
375 .end = 0xffd90013,
376 .flags = IORESOURCE_MEM,
377 },
378 [1] = {
379 .start = 57,
380 .flags = IORESOURCE_IRQ,
381 },
382};
383
384static struct platform_device tmu3_device = {
385 .name = "sh_tmu",
386 .id = 3,
387 .dev = {
388 .platform_data = &tmu3_platform_data,
389 },
390 .resource = tmu3_resources,
391 .num_resources = ARRAY_SIZE(tmu3_resources),
392};
393
394static struct sh_timer_config tmu4_platform_data = {
395 .name = "TMU4",
396 .channel_offset = 0x10,
397 .timer_bit = 1,
398 .clk = "tmu1",
399};
400
401static struct resource tmu4_resources[] = {
402 [0] = {
403 .name = "TMU4",
404 .start = 0xffd90014,
405 .end = 0xffd9001f,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = 58,
410 .flags = IORESOURCE_IRQ,
411 },
412};
413
414static struct platform_device tmu4_device = {
415 .name = "sh_tmu",
416 .id = 4,
417 .dev = {
418 .platform_data = &tmu4_platform_data,
419 },
420 .resource = tmu4_resources,
421 .num_resources = ARRAY_SIZE(tmu4_resources),
422};
423
424static struct sh_timer_config tmu5_platform_data = {
425 .name = "TMU5",
426 .channel_offset = 0x1c,
427 .timer_bit = 2,
428 .clk = "tmu1",
429};
430
431static struct resource tmu5_resources[] = {
432 [0] = {
433 .name = "TMU5",
434 .start = 0xffd90020,
435 .end = 0xffd9002b,
436 .flags = IORESOURCE_MEM,
437 },
438 [1] = {
439 .start = 57,
440 .flags = IORESOURCE_IRQ,
441 },
442};
443
444static struct platform_device tmu5_device = {
445 .name = "sh_tmu",
446 .id = 5,
447 .dev = {
448 .platform_data = &tmu5_platform_data,
449 },
450 .resource = tmu5_resources,
451 .num_resources = ARRAY_SIZE(tmu5_resources),
452};
453
f168dd00
KM		 454/* JPU */
455static struct uio_info jpu_platform_data = {
456 .name = "JPU",
457 .version = "0",
458 .irq = 27,
459};
460
461static struct resource jpu_resources[] = {
462 [0] = {
463 .name = "JPU",
464 .start = 0xfe980000,
465 .end = 0xfe9902d3,
466 .flags = IORESOURCE_MEM,
467 },
468 [1] = {
469 /* place holder for contiguous memory */
470 },
471};
472
473static struct platform_device jpu_device = {
474 .name = "uio_pdrv_genirq",
475 .id = 3,
476 .dev = {
477 .platform_data = &jpu_platform_data,
478 },
479 .resource = jpu_resources,
480 .num_resources = ARRAY_SIZE(jpu_resources),
481};
482
0207a2ef 483static struct platform_device *sh7724_devices[] __initdata = {
6a3395be 484 &cmt_device,
6a3501b6
MD		 485 &tmu0_device,
486 &tmu1_device,
487 &tmu2_device,
488 &tmu3_device,
489 &tmu4_device,
490 &tmu5_device,
0207a2ef
KM		 491 &sci_device,
492 &rtc_device,
40c7e8be
KM		 493 &iic0_device,
494 &iic1_device,
cd5b9ef7 495 &vpu_device,
ad95b78c
KM		 496 &veu0_device,
497 &veu1_device,
f168dd00 498 &jpu_device,
0207a2ef
KM		 499};
500
501static int __init sh7724_devices_setup(void)
502{
cd5b9ef7 503 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
ad95b78c
KM		 504 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
505 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
f168dd00 506 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
0207a2ef
KM		 507
508 return platform_add_devices(sh7724_devices,
509 ARRAY_SIZE(sh7724_devices));
510}
511device_initcall(sh7724_devices_setup);
512
8fb2bae4
PM		 513static struct platform_device *sh7724_early_devices[] __initdata = {
514 &cmt_device,
6a3501b6
MD		 515 &tmu0_device,
516 &tmu1_device,
517 &tmu2_device,
518 &tmu3_device,
519 &tmu4_device,
520 &tmu5_device,
8fb2bae4
PM		 521};
522
523void __init plat_early_device_setup(void)
524{
525 early_platform_add_devices(sh7724_early_devices,
526 ARRAY_SIZE(sh7724_early_devices));
527}
528
b4bd9eb0
KM		 529#define RAMCR_CACHE_L2FC 0x0002
530#define RAMCR_CACHE_L2E 0x0001
531#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
532void __uses_jump_to_uncached l2_cache_init(void)
533{
534 /* Enable L2 cache */
535 ctrl_outl(L2_CACHE_ENABLE, RAMCR);
536}
537
0207a2ef
KM		 538enum {
539 UNUSED = 0,
540
541 /* interrupt sources */
542 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
543 HUDI,
544 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
c5eeff1f 545 _2DG_TRI, _2DG_INI, _2DG_CEI,
0207a2ef 546 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
c5eeff1f
KM		 547 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
548 SCIFA3,
549 VPU,
550 TPU,
551 CEU1,
552 BEU1,
553 USB0, USB1,
0207a2ef
KM		 554 ATAPI,
555 RTC_ATI, RTC_PRI, RTC_CUI,
556 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
557 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
c5eeff1f 558 KEYSC,
0207a2ef 559 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
c5eeff1f 560 VEU0,
0207a2ef
KM		 561 MSIOF_MSIOFI0, MSIOF_MSIOFI1,
562 SPU_SPUI0, SPU_SPUI1,
c5eeff1f
KM		 563 SCIFA4,
564 ICB,
0207a2ef
KM		 565 ETHI,
566 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
567 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
c5eeff1f
KM		 568 SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3,
569 CMT,
570 TSIF,
571 FSI,
572 SCIFA5,
0207a2ef 573 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
c5eeff1f 574 IRDA,
0207a2ef 575 SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
c5eeff1f
KM		 576 JPU,
577 _2DDMAC,
578 MMC_MMC2I, MMC_MMC3I,
579 LCDC,
0207a2ef
KM		 580 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
581
582 /* interrupt groups */
c5eeff1f
KM		 583 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
584 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
0207a2ef
KM		 585};
586
587static struct intc_vect vectors[] __initdata = {
588 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
589 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
590 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
591 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
592
593 INTC_VECT(DMAC1A_DEI0, 0x700),
594 INTC_VECT(DMAC1A_DEI1, 0x720),
595 INTC_VECT(DMAC1A_DEI2, 0x740),
596 INTC_VECT(DMAC1A_DEI3, 0x760),
597
598 INTC_VECT(_2DG_TRI, 0x780),
599 INTC_VECT(_2DG_INI, 0x7A0),
600 INTC_VECT(_2DG_CEI, 0x7C0),
0207a2ef
KM		 601
602 INTC_VECT(DMAC0A_DEI0, 0x800),
603 INTC_VECT(DMAC0A_DEI1, 0x820),
604 INTC_VECT(DMAC0A_DEI2, 0x840),
605 INTC_VECT(DMAC0A_DEI3, 0x860),
606
c5eeff1f
KM		 607 INTC_VECT(VIO_CEU0, 0x880),
608 INTC_VECT(VIO_BEU0, 0x8A0),
609 INTC_VECT(VIO_VEU1, 0x8C0),
610 INTC_VECT(VIO_VOU, 0x8E0),
0207a2ef 611
c5eeff1f
KM		 612 INTC_VECT(SCIFA3, 0x900),
613 INTC_VECT(VPU, 0x980),
614 INTC_VECT(TPU, 0x9A0),
615 INTC_VECT(CEU1, 0x9E0),
616 INTC_VECT(BEU1, 0xA00),
617 INTC_VECT(USB0, 0xA20),
618 INTC_VECT(USB1, 0xA40),
619 INTC_VECT(ATAPI, 0xA60),
0207a2ef
KM		 620
621 INTC_VECT(RTC_ATI, 0xA80),
622 INTC_VECT(RTC_PRI, 0xAA0),
623 INTC_VECT(RTC_CUI, 0xAC0),
624
625 INTC_VECT(DMAC1B_DEI4, 0xB00),
626 INTC_VECT(DMAC1B_DEI5, 0xB20),
627 INTC_VECT(DMAC1B_DADERR, 0xB40),
628
629 INTC_VECT(DMAC0B_DEI4, 0xB80),
630 INTC_VECT(DMAC0B_DEI5, 0xBA0),
631 INTC_VECT(DMAC0B_DADERR, 0xBC0),
632
c5eeff1f 633 INTC_VECT(KEYSC, 0xBE0),
0207a2ef
KM		 634 INTC_VECT(SCIF_SCIF0, 0xC00),
635 INTC_VECT(SCIF_SCIF1, 0xC20),
636 INTC_VECT(SCIF_SCIF2, 0xC40),
c5eeff1f 637 INTC_VECT(VEU0, 0xC60),
0207a2ef
KM		 638 INTC_VECT(MSIOF_MSIOFI0, 0xC80),
639 INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
640 INTC_VECT(SPU_SPUI0, 0xCC0),
641 INTC_VECT(SPU_SPUI1, 0xCE0),
c5eeff1f 642 INTC_VECT(SCIFA4, 0xD00),
0207a2ef 643
c5eeff1f 644 INTC_VECT(ICB, 0xD20),
0207a2ef
KM		 645 INTC_VECT(ETHI, 0xD60),
646
647 INTC_VECT(I2C1_ALI, 0xD80),
648 INTC_VECT(I2C1_TACKI, 0xDA0),
649 INTC_VECT(I2C1_WAITI, 0xDC0),
650 INTC_VECT(I2C1_DTEI, 0xDE0),
651
652 INTC_VECT(I2C0_ALI, 0xE00),
653 INTC_VECT(I2C0_TACKI, 0xE20),
654 INTC_VECT(I2C0_WAITI, 0xE40),
655 INTC_VECT(I2C0_DTEI, 0xE60),
656
657 INTC_VECT(SDHI0_SDHII0, 0xE80),
658 INTC_VECT(SDHI0_SDHII1, 0xEA0),
659 INTC_VECT(SDHI0_SDHII2, 0xEC0),
c5eeff1f 660 INTC_VECT(SDHI0_SDHII3, 0xEE0),
0207a2ef 661
c5eeff1f
KM		 662 INTC_VECT(CMT, 0xF00),
663 INTC_VECT(TSIF, 0xF20),
664 INTC_VECT(FSI, 0xF80),
665 INTC_VECT(SCIFA5, 0xFA0),
0207a2ef
KM		 666
667 INTC_VECT(TMU0_TUNI0, 0x400),
668 INTC_VECT(TMU0_TUNI1, 0x420),
669 INTC_VECT(TMU0_TUNI2, 0x440),
670
c5eeff1f 671 INTC_VECT(IRDA, 0x480),
0207a2ef
KM		 672
673 INTC_VECT(SDHI1_SDHII0, 0x4E0),
674 INTC_VECT(SDHI1_SDHII1, 0x500),
675 INTC_VECT(SDHI1_SDHII2, 0x520),
676
c5eeff1f
KM		 677 INTC_VECT(JPU, 0x560),
678 INTC_VECT(_2DDMAC, 0x4A0),
0207a2ef 679
c5eeff1f
KM		 680 INTC_VECT(MMC_MMC2I, 0x5A0),
681 INTC_VECT(MMC_MMC3I, 0x5C0),
0207a2ef 682
c5eeff1f 683 INTC_VECT(LCDC, 0xF40),
0207a2ef
KM		 684
685 INTC_VECT(TMU1_TUNI0, 0x920),
686 INTC_VECT(TMU1_TUNI1, 0x940),
687 INTC_VECT(TMU1_TUNI2, 0x960),
688};
689
690static struct intc_group groups[] __initdata = {
691 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
c5eeff1f 692 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
0207a2ef 693 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
c5eeff1f
KM		 694 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
695 INTC_GROUP(USB, USB0, USB1),
0207a2ef
KM		 696 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
697 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
698 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
699 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
700 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
c5eeff1f 701 INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3),
0207a2ef
KM		 702 INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
703 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
c5eeff1f 704 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
0207a2ef
KM		 705};
706
0207a2ef
KM		 707static struct intc_mask_reg mask_registers[] __initdata = {
708 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
709 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
c5eeff1f 710 0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
0207a2ef 711 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
c5eeff1f 712 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
0207a2ef
KM		 713 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
714 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
c5eeff1f 715 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
0207a2ef
KM		 716 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
717 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
c5eeff1f 718 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
0207a2ef
KM		 719 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
720 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
c5eeff1f 721 JPU, 0, 0, LCDC } },
0207a2ef 722 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
c5eeff1f
KM		 723 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
724 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
0207a2ef 725 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
c5eeff1f
KM		 726 { 0, 0, ICB, SCIFA4,
727 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
0207a2ef
KM		 728 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
729 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
730 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
731 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
c5eeff1f
KM		 732 { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
733 0, 0, SCIFA5, FSI } },
0207a2ef 734 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
c5eeff1f 735 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
0207a2ef
KM		 736 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
737 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
c5eeff1f 738 0, RTC_CUI, RTC_PRI, RTC_ATI } },
0207a2ef 739 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
c5eeff1f
KM		 740 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
741 0, TPU, 0, TSIF } },
0207a2ef 742 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
c5eeff1f 743 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
0207a2ef
KM		 744 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
745 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
746};
747
748static struct intc_prio_reg prio_registers[] __initdata = {
749 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
c5eeff1f
KM		 750 TMU0_TUNI2, IRDA } },
751 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
0207a2ef
KM		 752 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
753 TMU1_TUNI2, SPU } },
c5eeff1f
KM		 754 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
755 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
756 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
0207a2ef 757 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
c5eeff1f 758 SCIF_SCIF2, VEU0 } },
0207a2ef
KM		 759 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
760 I2C1, I2C0 } },
c5eeff1f
KM		 761 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
762 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
763 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
764 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
0207a2ef
KM		 765 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
766 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
767};
768
769static struct intc_sense_reg sense_registers[] __initdata = {
770 { 0xa414001c, 16, 2, /* ICR1 */
771 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
772};
773
774static struct intc_mask_reg ack_registers[] __initdata = {
775 { 0xa4140024, 0, 8, /* INTREQ00 */
776 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
777};
778
779static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
780 mask_registers, prio_registers, sense_registers,
781 ack_registers);
782
783void __init plat_irq_setup(void)
784{
785 register_intc_controller(&intc_desc);
786}
Linux 6.x block layer and io_uring tree(s)