Commit | Line | Data |
---|---|---|
0207a2ef KM |
1 | /* |
2 | * SH7724 Setup | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * | |
6 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
7 | * | |
8 | * Based on SH7723 Setup | |
9 | * Copyright (C) 2008 Paul Mundt | |
10 | * | |
11 | * This file is subject to the terms and conditions of the GNU General Public | |
12 | * License. See the file "COPYING" in the main directory of this archive | |
13 | * for more details. | |
14 | */ | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/serial.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/serial_sci.h> | |
20 | #include <linux/uio_driver.h> | |
46a12f74 | 21 | #include <linux/sh_timer.h> |
0207a2ef | 22 | #include <linux/io.h> |
da14909e MD |
23 | #include <linux/notifier.h> |
24 | #include <asm/suspend.h> | |
0207a2ef KM |
25 | #include <asm/clock.h> |
26 | #include <asm/mmzone.h> | |
593a0c89 | 27 | #include <cpu/sh7724.h> |
0207a2ef KM |
28 | |
29 | /* Serial */ | |
30 | static struct plat_sci_port sci_platform_data[] = { | |
31 | { | |
32 | .mapbase = 0xffe00000, | |
33 | .flags = UPF_BOOT_AUTOCONF, | |
34 | .type = PORT_SCIF, | |
35 | .irqs = { 80, 80, 80, 80 }, | |
3b226e15 | 36 | .clk = "scif0", |
0207a2ef KM |
37 | }, { |
38 | .mapbase = 0xffe10000, | |
39 | .flags = UPF_BOOT_AUTOCONF, | |
40 | .type = PORT_SCIF, | |
41 | .irqs = { 81, 81, 81, 81 }, | |
3b226e15 | 42 | .clk = "scif1", |
0207a2ef KM |
43 | }, { |
44 | .mapbase = 0xffe20000, | |
45 | .flags = UPF_BOOT_AUTOCONF, | |
46 | .type = PORT_SCIF, | |
47 | .irqs = { 82, 82, 82, 82 }, | |
3b226e15 | 48 | .clk = "scif2", |
0207a2ef KM |
49 | }, { |
50 | .mapbase = 0xa4e30000, | |
51 | .flags = UPF_BOOT_AUTOCONF, | |
52 | .type = PORT_SCIFA, | |
53 | .irqs = { 56, 56, 56, 56 }, | |
3b226e15 | 54 | .clk = "scif3", |
0207a2ef KM |
55 | }, { |
56 | .mapbase = 0xa4e40000, | |
57 | .flags = UPF_BOOT_AUTOCONF, | |
58 | .type = PORT_SCIFA, | |
59 | .irqs = { 88, 88, 88, 88 }, | |
3b226e15 | 60 | .clk = "scif4", |
0207a2ef KM |
61 | }, { |
62 | .mapbase = 0xa4e50000, | |
63 | .flags = UPF_BOOT_AUTOCONF, | |
64 | .type = PORT_SCIFA, | |
65 | .irqs = { 109, 109, 109, 109 }, | |
3b226e15 | 66 | .clk = "scif5", |
0207a2ef KM |
67 | }, { |
68 | .flags = 0, | |
69 | } | |
70 | }; | |
71 | ||
72 | static struct platform_device sci_device = { | |
73 | .name = "sh-sci", | |
74 | .id = -1, | |
75 | .dev = { | |
76 | .platform_data = sci_platform_data, | |
77 | }, | |
78 | }; | |
79 | ||
80 | /* RTC */ | |
81 | static struct resource rtc_resources[] = { | |
82 | [0] = { | |
83 | .start = 0xa465fec0, | |
84 | .end = 0xa465fec0 + 0x58 - 1, | |
85 | .flags = IORESOURCE_IO, | |
86 | }, | |
87 | [1] = { | |
88 | /* Period IRQ */ | |
89 | .start = 69, | |
90 | .flags = IORESOURCE_IRQ, | |
91 | }, | |
92 | [2] = { | |
93 | /* Carry IRQ */ | |
94 | .start = 70, | |
95 | .flags = IORESOURCE_IRQ, | |
96 | }, | |
97 | [3] = { | |
98 | /* Alarm IRQ */ | |
99 | .start = 68, | |
100 | .flags = IORESOURCE_IRQ, | |
101 | }, | |
102 | }; | |
103 | ||
104 | static struct platform_device rtc_device = { | |
105 | .name = "sh-rtc", | |
106 | .id = -1, | |
107 | .num_resources = ARRAY_SIZE(rtc_resources), | |
108 | .resource = rtc_resources, | |
593a0c89 MD |
109 | .archdata = { |
110 | .hwblk_id = HWBLK_RTC, | |
111 | }, | |
0207a2ef KM |
112 | }; |
113 | ||
40c7e8be KM |
114 | /* I2C0 */ |
115 | static struct resource iic0_resources[] = { | |
116 | [0] = { | |
117 | .name = "IIC0", | |
118 | .start = 0x04470000, | |
119 | .end = 0x04470018 - 1, | |
120 | .flags = IORESOURCE_MEM, | |
121 | }, | |
122 | [1] = { | |
123 | .start = 96, | |
124 | .end = 99, | |
125 | .flags = IORESOURCE_IRQ, | |
126 | }, | |
127 | }; | |
128 | ||
129 | static struct platform_device iic0_device = { | |
130 | .name = "i2c-sh_mobile", | |
131 | .id = 0, /* "i2c0" clock */ | |
132 | .num_resources = ARRAY_SIZE(iic0_resources), | |
133 | .resource = iic0_resources, | |
593a0c89 MD |
134 | .archdata = { |
135 | .hwblk_id = HWBLK_IIC0, | |
136 | }, | |
40c7e8be KM |
137 | }; |
138 | ||
139 | /* I2C1 */ | |
140 | static struct resource iic1_resources[] = { | |
141 | [0] = { | |
142 | .name = "IIC1", | |
143 | .start = 0x04750000, | |
144 | .end = 0x04750018 - 1, | |
145 | .flags = IORESOURCE_MEM, | |
146 | }, | |
147 | [1] = { | |
148 | .start = 92, | |
149 | .end = 95, | |
150 | .flags = IORESOURCE_IRQ, | |
151 | }, | |
152 | }; | |
153 | ||
154 | static struct platform_device iic1_device = { | |
155 | .name = "i2c-sh_mobile", | |
156 | .id = 1, /* "i2c1" clock */ | |
157 | .num_resources = ARRAY_SIZE(iic1_resources), | |
158 | .resource = iic1_resources, | |
593a0c89 MD |
159 | .archdata = { |
160 | .hwblk_id = HWBLK_IIC1, | |
161 | }, | |
40c7e8be KM |
162 | }; |
163 | ||
cd5b9ef7 KM |
164 | /* VPU */ |
165 | static struct uio_info vpu_platform_data = { | |
166 | .name = "VPU5F", | |
167 | .version = "0", | |
168 | .irq = 60, | |
169 | }; | |
170 | ||
171 | static struct resource vpu_resources[] = { | |
172 | [0] = { | |
173 | .name = "VPU", | |
174 | .start = 0xfe900000, | |
175 | .end = 0xfe902807, | |
176 | .flags = IORESOURCE_MEM, | |
177 | }, | |
178 | [1] = { | |
179 | /* place holder for contiguous memory */ | |
180 | }, | |
181 | }; | |
182 | ||
183 | static struct platform_device vpu_device = { | |
184 | .name = "uio_pdrv_genirq", | |
185 | .id = 0, | |
186 | .dev = { | |
187 | .platform_data = &vpu_platform_data, | |
188 | }, | |
189 | .resource = vpu_resources, | |
190 | .num_resources = ARRAY_SIZE(vpu_resources), | |
593a0c89 MD |
191 | .archdata = { |
192 | .hwblk_id = HWBLK_VPU, | |
193 | }, | |
cd5b9ef7 KM |
194 | }; |
195 | ||
ad95b78c KM |
196 | /* VEU0 */ |
197 | static struct uio_info veu0_platform_data = { | |
198 | .name = "VEU3F0", | |
199 | .version = "0", | |
200 | .irq = 83, | |
201 | }; | |
202 | ||
203 | static struct resource veu0_resources[] = { | |
204 | [0] = { | |
205 | .name = "VEU3F0", | |
206 | .start = 0xfe920000, | |
207 | .end = 0xfe9200cb - 1, | |
208 | .flags = IORESOURCE_MEM, | |
209 | }, | |
210 | [1] = { | |
211 | /* place holder for contiguous memory */ | |
212 | }, | |
213 | }; | |
214 | ||
215 | static struct platform_device veu0_device = { | |
216 | .name = "uio_pdrv_genirq", | |
217 | .id = 1, | |
218 | .dev = { | |
219 | .platform_data = &veu0_platform_data, | |
220 | }, | |
221 | .resource = veu0_resources, | |
222 | .num_resources = ARRAY_SIZE(veu0_resources), | |
593a0c89 MD |
223 | .archdata = { |
224 | .hwblk_id = HWBLK_VEU0, | |
225 | }, | |
ad95b78c KM |
226 | }; |
227 | ||
228 | /* VEU1 */ | |
229 | static struct uio_info veu1_platform_data = { | |
230 | .name = "VEU3F1", | |
231 | .version = "0", | |
232 | .irq = 54, | |
233 | }; | |
234 | ||
235 | static struct resource veu1_resources[] = { | |
236 | [0] = { | |
237 | .name = "VEU3F1", | |
238 | .start = 0xfe924000, | |
239 | .end = 0xfe9240cb - 1, | |
240 | .flags = IORESOURCE_MEM, | |
241 | }, | |
242 | [1] = { | |
243 | /* place holder for contiguous memory */ | |
244 | }, | |
245 | }; | |
246 | ||
247 | static struct platform_device veu1_device = { | |
248 | .name = "uio_pdrv_genirq", | |
249 | .id = 2, | |
250 | .dev = { | |
251 | .platform_data = &veu1_platform_data, | |
252 | }, | |
253 | .resource = veu1_resources, | |
254 | .num_resources = ARRAY_SIZE(veu1_resources), | |
593a0c89 MD |
255 | .archdata = { |
256 | .hwblk_id = HWBLK_VEU1, | |
257 | }, | |
ad95b78c KM |
258 | }; |
259 | ||
46a12f74 | 260 | static struct sh_timer_config cmt_platform_data = { |
6a3395be PM |
261 | .name = "CMT", |
262 | .channel_offset = 0x60, | |
263 | .timer_bit = 5, | |
264 | .clk = "cmt0", | |
265 | .clockevent_rating = 125, | |
266 | .clocksource_rating = 200, | |
267 | }; | |
268 | ||
269 | static struct resource cmt_resources[] = { | |
270 | [0] = { | |
271 | .name = "CMT", | |
272 | .start = 0x044a0060, | |
273 | .end = 0x044a006b, | |
274 | .flags = IORESOURCE_MEM, | |
275 | }, | |
276 | [1] = { | |
277 | .start = 104, | |
278 | .flags = IORESOURCE_IRQ, | |
279 | }, | |
280 | }; | |
281 | ||
282 | static struct platform_device cmt_device = { | |
283 | .name = "sh_cmt", | |
284 | .id = 0, | |
285 | .dev = { | |
286 | .platform_data = &cmt_platform_data, | |
287 | }, | |
288 | .resource = cmt_resources, | |
289 | .num_resources = ARRAY_SIZE(cmt_resources), | |
593a0c89 MD |
290 | .archdata = { |
291 | .hwblk_id = HWBLK_CMT, | |
292 | }, | |
6a3395be PM |
293 | }; |
294 | ||
6a3501b6 MD |
295 | static struct sh_timer_config tmu0_platform_data = { |
296 | .name = "TMU0", | |
297 | .channel_offset = 0x04, | |
298 | .timer_bit = 0, | |
299 | .clk = "tmu0", | |
300 | .clockevent_rating = 200, | |
301 | }; | |
302 | ||
303 | static struct resource tmu0_resources[] = { | |
304 | [0] = { | |
305 | .name = "TMU0", | |
306 | .start = 0xffd80008, | |
307 | .end = 0xffd80013, | |
308 | .flags = IORESOURCE_MEM, | |
309 | }, | |
310 | [1] = { | |
311 | .start = 16, | |
312 | .flags = IORESOURCE_IRQ, | |
313 | }, | |
314 | }; | |
315 | ||
316 | static struct platform_device tmu0_device = { | |
317 | .name = "sh_tmu", | |
318 | .id = 0, | |
319 | .dev = { | |
320 | .platform_data = &tmu0_platform_data, | |
321 | }, | |
322 | .resource = tmu0_resources, | |
323 | .num_resources = ARRAY_SIZE(tmu0_resources), | |
593a0c89 MD |
324 | .archdata = { |
325 | .hwblk_id = HWBLK_TMU0, | |
326 | }, | |
6a3501b6 MD |
327 | }; |
328 | ||
329 | static struct sh_timer_config tmu1_platform_data = { | |
330 | .name = "TMU1", | |
331 | .channel_offset = 0x10, | |
332 | .timer_bit = 1, | |
333 | .clk = "tmu0", | |
334 | .clocksource_rating = 200, | |
335 | }; | |
336 | ||
337 | static struct resource tmu1_resources[] = { | |
338 | [0] = { | |
339 | .name = "TMU1", | |
340 | .start = 0xffd80014, | |
341 | .end = 0xffd8001f, | |
342 | .flags = IORESOURCE_MEM, | |
343 | }, | |
344 | [1] = { | |
345 | .start = 17, | |
346 | .flags = IORESOURCE_IRQ, | |
347 | }, | |
348 | }; | |
349 | ||
350 | static struct platform_device tmu1_device = { | |
351 | .name = "sh_tmu", | |
352 | .id = 1, | |
353 | .dev = { | |
354 | .platform_data = &tmu1_platform_data, | |
355 | }, | |
356 | .resource = tmu1_resources, | |
357 | .num_resources = ARRAY_SIZE(tmu1_resources), | |
593a0c89 MD |
358 | .archdata = { |
359 | .hwblk_id = HWBLK_TMU0, | |
360 | }, | |
6a3501b6 MD |
361 | }; |
362 | ||
363 | static struct sh_timer_config tmu2_platform_data = { | |
364 | .name = "TMU2", | |
365 | .channel_offset = 0x1c, | |
366 | .timer_bit = 2, | |
367 | .clk = "tmu0", | |
368 | }; | |
369 | ||
370 | static struct resource tmu2_resources[] = { | |
371 | [0] = { | |
372 | .name = "TMU2", | |
373 | .start = 0xffd80020, | |
374 | .end = 0xffd8002b, | |
375 | .flags = IORESOURCE_MEM, | |
376 | }, | |
377 | [1] = { | |
378 | .start = 18, | |
379 | .flags = IORESOURCE_IRQ, | |
380 | }, | |
381 | }; | |
382 | ||
383 | static struct platform_device tmu2_device = { | |
384 | .name = "sh_tmu", | |
385 | .id = 2, | |
386 | .dev = { | |
387 | .platform_data = &tmu2_platform_data, | |
388 | }, | |
389 | .resource = tmu2_resources, | |
390 | .num_resources = ARRAY_SIZE(tmu2_resources), | |
593a0c89 MD |
391 | .archdata = { |
392 | .hwblk_id = HWBLK_TMU0, | |
393 | }, | |
6a3501b6 MD |
394 | }; |
395 | ||
396 | ||
397 | static struct sh_timer_config tmu3_platform_data = { | |
398 | .name = "TMU3", | |
399 | .channel_offset = 0x04, | |
400 | .timer_bit = 0, | |
401 | .clk = "tmu1", | |
402 | }; | |
403 | ||
404 | static struct resource tmu3_resources[] = { | |
405 | [0] = { | |
406 | .name = "TMU3", | |
407 | .start = 0xffd90008, | |
408 | .end = 0xffd90013, | |
409 | .flags = IORESOURCE_MEM, | |
410 | }, | |
411 | [1] = { | |
412 | .start = 57, | |
413 | .flags = IORESOURCE_IRQ, | |
414 | }, | |
415 | }; | |
416 | ||
417 | static struct platform_device tmu3_device = { | |
418 | .name = "sh_tmu", | |
419 | .id = 3, | |
420 | .dev = { | |
421 | .platform_data = &tmu3_platform_data, | |
422 | }, | |
423 | .resource = tmu3_resources, | |
424 | .num_resources = ARRAY_SIZE(tmu3_resources), | |
593a0c89 MD |
425 | .archdata = { |
426 | .hwblk_id = HWBLK_TMU1, | |
427 | }, | |
6a3501b6 MD |
428 | }; |
429 | ||
430 | static struct sh_timer_config tmu4_platform_data = { | |
431 | .name = "TMU4", | |
432 | .channel_offset = 0x10, | |
433 | .timer_bit = 1, | |
434 | .clk = "tmu1", | |
435 | }; | |
436 | ||
437 | static struct resource tmu4_resources[] = { | |
438 | [0] = { | |
439 | .name = "TMU4", | |
440 | .start = 0xffd90014, | |
441 | .end = 0xffd9001f, | |
442 | .flags = IORESOURCE_MEM, | |
443 | }, | |
444 | [1] = { | |
445 | .start = 58, | |
446 | .flags = IORESOURCE_IRQ, | |
447 | }, | |
448 | }; | |
449 | ||
450 | static struct platform_device tmu4_device = { | |
451 | .name = "sh_tmu", | |
452 | .id = 4, | |
453 | .dev = { | |
454 | .platform_data = &tmu4_platform_data, | |
455 | }, | |
456 | .resource = tmu4_resources, | |
457 | .num_resources = ARRAY_SIZE(tmu4_resources), | |
593a0c89 MD |
458 | .archdata = { |
459 | .hwblk_id = HWBLK_TMU1, | |
460 | }, | |
6a3501b6 MD |
461 | }; |
462 | ||
463 | static struct sh_timer_config tmu5_platform_data = { | |
464 | .name = "TMU5", | |
465 | .channel_offset = 0x1c, | |
466 | .timer_bit = 2, | |
467 | .clk = "tmu1", | |
468 | }; | |
469 | ||
470 | static struct resource tmu5_resources[] = { | |
471 | [0] = { | |
472 | .name = "TMU5", | |
473 | .start = 0xffd90020, | |
474 | .end = 0xffd9002b, | |
475 | .flags = IORESOURCE_MEM, | |
476 | }, | |
477 | [1] = { | |
478 | .start = 57, | |
479 | .flags = IORESOURCE_IRQ, | |
480 | }, | |
481 | }; | |
482 | ||
483 | static struct platform_device tmu5_device = { | |
484 | .name = "sh_tmu", | |
485 | .id = 5, | |
486 | .dev = { | |
487 | .platform_data = &tmu5_platform_data, | |
488 | }, | |
489 | .resource = tmu5_resources, | |
490 | .num_resources = ARRAY_SIZE(tmu5_resources), | |
593a0c89 MD |
491 | .archdata = { |
492 | .hwblk_id = HWBLK_TMU1, | |
493 | }, | |
6a3501b6 MD |
494 | }; |
495 | ||
f168dd00 KM |
496 | /* JPU */ |
497 | static struct uio_info jpu_platform_data = { | |
498 | .name = "JPU", | |
499 | .version = "0", | |
500 | .irq = 27, | |
501 | }; | |
502 | ||
503 | static struct resource jpu_resources[] = { | |
504 | [0] = { | |
505 | .name = "JPU", | |
506 | .start = 0xfe980000, | |
507 | .end = 0xfe9902d3, | |
508 | .flags = IORESOURCE_MEM, | |
509 | }, | |
510 | [1] = { | |
511 | /* place holder for contiguous memory */ | |
512 | }, | |
513 | }; | |
514 | ||
515 | static struct platform_device jpu_device = { | |
516 | .name = "uio_pdrv_genirq", | |
517 | .id = 3, | |
518 | .dev = { | |
519 | .platform_data = &jpu_platform_data, | |
520 | }, | |
521 | .resource = jpu_resources, | |
522 | .num_resources = ARRAY_SIZE(jpu_resources), | |
593a0c89 MD |
523 | .archdata = { |
524 | .hwblk_id = HWBLK_JPU, | |
525 | }, | |
f168dd00 KM |
526 | }; |
527 | ||
0207a2ef | 528 | static struct platform_device *sh7724_devices[] __initdata = { |
6a3395be | 529 | &cmt_device, |
6a3501b6 MD |
530 | &tmu0_device, |
531 | &tmu1_device, | |
532 | &tmu2_device, | |
533 | &tmu3_device, | |
534 | &tmu4_device, | |
535 | &tmu5_device, | |
0207a2ef KM |
536 | &sci_device, |
537 | &rtc_device, | |
40c7e8be KM |
538 | &iic0_device, |
539 | &iic1_device, | |
cd5b9ef7 | 540 | &vpu_device, |
ad95b78c KM |
541 | &veu0_device, |
542 | &veu1_device, | |
f168dd00 | 543 | &jpu_device, |
0207a2ef KM |
544 | }; |
545 | ||
546 | static int __init sh7724_devices_setup(void) | |
547 | { | |
cd5b9ef7 | 548 | platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); |
ad95b78c KM |
549 | platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); |
550 | platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); | |
f168dd00 | 551 | platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); |
0207a2ef KM |
552 | |
553 | return platform_add_devices(sh7724_devices, | |
554 | ARRAY_SIZE(sh7724_devices)); | |
555 | } | |
955c9863 | 556 | arch_initcall(sh7724_devices_setup); |
0207a2ef | 557 | |
8fb2bae4 PM |
558 | static struct platform_device *sh7724_early_devices[] __initdata = { |
559 | &cmt_device, | |
6a3501b6 MD |
560 | &tmu0_device, |
561 | &tmu1_device, | |
562 | &tmu2_device, | |
563 | &tmu3_device, | |
564 | &tmu4_device, | |
565 | &tmu5_device, | |
8fb2bae4 PM |
566 | }; |
567 | ||
568 | void __init plat_early_device_setup(void) | |
569 | { | |
570 | early_platform_add_devices(sh7724_early_devices, | |
571 | ARRAY_SIZE(sh7724_early_devices)); | |
572 | } | |
573 | ||
b4bd9eb0 KM |
574 | #define RAMCR_CACHE_L2FC 0x0002 |
575 | #define RAMCR_CACHE_L2E 0x0001 | |
576 | #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) | |
577 | void __uses_jump_to_uncached l2_cache_init(void) | |
578 | { | |
579 | /* Enable L2 cache */ | |
580 | ctrl_outl(L2_CACHE_ENABLE, RAMCR); | |
581 | } | |
582 | ||
0207a2ef KM |
583 | enum { |
584 | UNUSED = 0, | |
585 | ||
586 | /* interrupt sources */ | |
587 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, | |
588 | HUDI, | |
589 | DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3, | |
c5eeff1f | 590 | _2DG_TRI, _2DG_INI, _2DG_CEI, |
0207a2ef | 591 | DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3, |
c5eeff1f KM |
592 | VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU, |
593 | SCIFA3, | |
594 | VPU, | |
595 | TPU, | |
596 | CEU1, | |
597 | BEU1, | |
598 | USB0, USB1, | |
0207a2ef KM |
599 | ATAPI, |
600 | RTC_ATI, RTC_PRI, RTC_CUI, | |
601 | DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR, | |
602 | DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR, | |
c5eeff1f | 603 | KEYSC, |
0207a2ef | 604 | SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2, |
c5eeff1f | 605 | VEU0, |
0207a2ef KM |
606 | MSIOF_MSIOFI0, MSIOF_MSIOFI1, |
607 | SPU_SPUI0, SPU_SPUI1, | |
c5eeff1f KM |
608 | SCIFA4, |
609 | ICB, | |
0207a2ef KM |
610 | ETHI, |
611 | I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, | |
612 | I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, | |
c5eeff1f KM |
613 | SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3, |
614 | CMT, | |
615 | TSIF, | |
616 | FSI, | |
617 | SCIFA5, | |
0207a2ef | 618 | TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, |
c5eeff1f | 619 | IRDA, |
0207a2ef | 620 | SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2, |
c5eeff1f KM |
621 | JPU, |
622 | _2DDMAC, | |
623 | MMC_MMC2I, MMC_MMC3I, | |
624 | LCDC, | |
0207a2ef KM |
625 | TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, |
626 | ||
627 | /* interrupt groups */ | |
c5eeff1f KM |
628 | DMAC1A, _2DG, DMAC0A, VIO, USB, RTC, |
629 | DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF, | |
0207a2ef KM |
630 | }; |
631 | ||
632 | static struct intc_vect vectors[] __initdata = { | |
633 | INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), | |
634 | INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), | |
635 | INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), | |
636 | INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), | |
637 | ||
638 | INTC_VECT(DMAC1A_DEI0, 0x700), | |
639 | INTC_VECT(DMAC1A_DEI1, 0x720), | |
640 | INTC_VECT(DMAC1A_DEI2, 0x740), | |
641 | INTC_VECT(DMAC1A_DEI3, 0x760), | |
642 | ||
643 | INTC_VECT(_2DG_TRI, 0x780), | |
644 | INTC_VECT(_2DG_INI, 0x7A0), | |
645 | INTC_VECT(_2DG_CEI, 0x7C0), | |
0207a2ef KM |
646 | |
647 | INTC_VECT(DMAC0A_DEI0, 0x800), | |
648 | INTC_VECT(DMAC0A_DEI1, 0x820), | |
649 | INTC_VECT(DMAC0A_DEI2, 0x840), | |
650 | INTC_VECT(DMAC0A_DEI3, 0x860), | |
651 | ||
c5eeff1f KM |
652 | INTC_VECT(VIO_CEU0, 0x880), |
653 | INTC_VECT(VIO_BEU0, 0x8A0), | |
654 | INTC_VECT(VIO_VEU1, 0x8C0), | |
655 | INTC_VECT(VIO_VOU, 0x8E0), | |
0207a2ef | 656 | |
c5eeff1f KM |
657 | INTC_VECT(SCIFA3, 0x900), |
658 | INTC_VECT(VPU, 0x980), | |
659 | INTC_VECT(TPU, 0x9A0), | |
660 | INTC_VECT(CEU1, 0x9E0), | |
661 | INTC_VECT(BEU1, 0xA00), | |
662 | INTC_VECT(USB0, 0xA20), | |
663 | INTC_VECT(USB1, 0xA40), | |
664 | INTC_VECT(ATAPI, 0xA60), | |
0207a2ef KM |
665 | |
666 | INTC_VECT(RTC_ATI, 0xA80), | |
667 | INTC_VECT(RTC_PRI, 0xAA0), | |
668 | INTC_VECT(RTC_CUI, 0xAC0), | |
669 | ||
670 | INTC_VECT(DMAC1B_DEI4, 0xB00), | |
671 | INTC_VECT(DMAC1B_DEI5, 0xB20), | |
672 | INTC_VECT(DMAC1B_DADERR, 0xB40), | |
673 | ||
674 | INTC_VECT(DMAC0B_DEI4, 0xB80), | |
675 | INTC_VECT(DMAC0B_DEI5, 0xBA0), | |
676 | INTC_VECT(DMAC0B_DADERR, 0xBC0), | |
677 | ||
c5eeff1f | 678 | INTC_VECT(KEYSC, 0xBE0), |
0207a2ef KM |
679 | INTC_VECT(SCIF_SCIF0, 0xC00), |
680 | INTC_VECT(SCIF_SCIF1, 0xC20), | |
681 | INTC_VECT(SCIF_SCIF2, 0xC40), | |
c5eeff1f | 682 | INTC_VECT(VEU0, 0xC60), |
0207a2ef KM |
683 | INTC_VECT(MSIOF_MSIOFI0, 0xC80), |
684 | INTC_VECT(MSIOF_MSIOFI1, 0xCA0), | |
685 | INTC_VECT(SPU_SPUI0, 0xCC0), | |
686 | INTC_VECT(SPU_SPUI1, 0xCE0), | |
c5eeff1f | 687 | INTC_VECT(SCIFA4, 0xD00), |
0207a2ef | 688 | |
c5eeff1f | 689 | INTC_VECT(ICB, 0xD20), |
0207a2ef KM |
690 | INTC_VECT(ETHI, 0xD60), |
691 | ||
692 | INTC_VECT(I2C1_ALI, 0xD80), | |
693 | INTC_VECT(I2C1_TACKI, 0xDA0), | |
694 | INTC_VECT(I2C1_WAITI, 0xDC0), | |
695 | INTC_VECT(I2C1_DTEI, 0xDE0), | |
696 | ||
697 | INTC_VECT(I2C0_ALI, 0xE00), | |
698 | INTC_VECT(I2C0_TACKI, 0xE20), | |
699 | INTC_VECT(I2C0_WAITI, 0xE40), | |
700 | INTC_VECT(I2C0_DTEI, 0xE60), | |
701 | ||
702 | INTC_VECT(SDHI0_SDHII0, 0xE80), | |
703 | INTC_VECT(SDHI0_SDHII1, 0xEA0), | |
704 | INTC_VECT(SDHI0_SDHII2, 0xEC0), | |
c5eeff1f | 705 | INTC_VECT(SDHI0_SDHII3, 0xEE0), |
0207a2ef | 706 | |
c5eeff1f KM |
707 | INTC_VECT(CMT, 0xF00), |
708 | INTC_VECT(TSIF, 0xF20), | |
709 | INTC_VECT(FSI, 0xF80), | |
710 | INTC_VECT(SCIFA5, 0xFA0), | |
0207a2ef KM |
711 | |
712 | INTC_VECT(TMU0_TUNI0, 0x400), | |
713 | INTC_VECT(TMU0_TUNI1, 0x420), | |
714 | INTC_VECT(TMU0_TUNI2, 0x440), | |
715 | ||
c5eeff1f | 716 | INTC_VECT(IRDA, 0x480), |
0207a2ef KM |
717 | |
718 | INTC_VECT(SDHI1_SDHII0, 0x4E0), | |
719 | INTC_VECT(SDHI1_SDHII1, 0x500), | |
720 | INTC_VECT(SDHI1_SDHII2, 0x520), | |
721 | ||
c5eeff1f KM |
722 | INTC_VECT(JPU, 0x560), |
723 | INTC_VECT(_2DDMAC, 0x4A0), | |
0207a2ef | 724 | |
c5eeff1f KM |
725 | INTC_VECT(MMC_MMC2I, 0x5A0), |
726 | INTC_VECT(MMC_MMC3I, 0x5C0), | |
0207a2ef | 727 | |
c5eeff1f | 728 | INTC_VECT(LCDC, 0xF40), |
0207a2ef KM |
729 | |
730 | INTC_VECT(TMU1_TUNI0, 0x920), | |
731 | INTC_VECT(TMU1_TUNI1, 0x940), | |
732 | INTC_VECT(TMU1_TUNI2, 0x960), | |
733 | }; | |
734 | ||
735 | static struct intc_group groups[] __initdata = { | |
736 | INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3), | |
c5eeff1f | 737 | INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI), |
0207a2ef | 738 | INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3), |
c5eeff1f KM |
739 | INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU), |
740 | INTC_GROUP(USB, USB0, USB1), | |
0207a2ef KM |
741 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
742 | INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR), | |
743 | INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR), | |
744 | INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), | |
745 | INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), | |
c5eeff1f | 746 | INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3), |
0207a2ef KM |
747 | INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2), |
748 | INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1), | |
c5eeff1f | 749 | INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I), |
0207a2ef KM |
750 | }; |
751 | ||
0207a2ef KM |
752 | static struct intc_mask_reg mask_registers[] __initdata = { |
753 | { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ | |
754 | { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, | |
c5eeff1f | 755 | 0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } }, |
0207a2ef | 756 | { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ |
c5eeff1f | 757 | { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, |
0207a2ef KM |
758 | DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, |
759 | { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ | |
c5eeff1f | 760 | { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } }, |
0207a2ef KM |
761 | { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ |
762 | { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0, | |
c5eeff1f | 763 | SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } }, |
0207a2ef KM |
764 | { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ |
765 | { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0, | |
c5eeff1f | 766 | JPU, 0, 0, LCDC } }, |
0207a2ef | 767 | { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ |
c5eeff1f KM |
768 | { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4, |
769 | VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } }, | |
0207a2ef | 770 | { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ |
c5eeff1f KM |
771 | { 0, 0, ICB, SCIFA4, |
772 | CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } }, | |
0207a2ef KM |
773 | { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ |
774 | { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, | |
775 | I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, | |
776 | { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ | |
c5eeff1f KM |
777 | { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0, |
778 | 0, 0, SCIFA5, FSI } }, | |
0207a2ef | 779 | { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ |
c5eeff1f | 780 | { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, |
0207a2ef KM |
781 | { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ |
782 | { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4, | |
c5eeff1f | 783 | 0, RTC_CUI, RTC_PRI, RTC_ATI } }, |
0207a2ef | 784 | { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ |
c5eeff1f KM |
785 | { 0, _2DG_CEI, _2DG_INI, _2DG_TRI, |
786 | 0, TPU, 0, TSIF } }, | |
0207a2ef | 787 | { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ |
c5eeff1f | 788 | { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } }, |
0207a2ef KM |
789 | { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ |
790 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
791 | }; | |
792 | ||
793 | static struct intc_prio_reg prio_registers[] __initdata = { | |
794 | { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, | |
c5eeff1f KM |
795 | TMU0_TUNI2, IRDA } }, |
796 | { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } }, | |
0207a2ef KM |
797 | { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, |
798 | TMU1_TUNI2, SPU } }, | |
c5eeff1f KM |
799 | { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } }, |
800 | { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } }, | |
801 | { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } }, | |
0207a2ef | 802 | { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, |
c5eeff1f | 803 | SCIF_SCIF2, VEU0 } }, |
0207a2ef KM |
804 | { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1, |
805 | I2C1, I2C0 } }, | |
c5eeff1f KM |
806 | { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } }, |
807 | { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } }, | |
808 | { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } }, | |
809 | { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } }, | |
0207a2ef KM |
810 | { 0xa4140010, 0, 32, 4, /* INTPRI00 */ |
811 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
812 | }; | |
813 | ||
814 | static struct intc_sense_reg sense_registers[] __initdata = { | |
815 | { 0xa414001c, 16, 2, /* ICR1 */ | |
816 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
817 | }; | |
818 | ||
819 | static struct intc_mask_reg ack_registers[] __initdata = { | |
820 | { 0xa4140024, 0, 8, /* INTREQ00 */ | |
821 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
822 | }; | |
823 | ||
824 | static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups, | |
825 | mask_registers, prio_registers, sense_registers, | |
826 | ack_registers); | |
827 | ||
828 | void __init plat_irq_setup(void) | |
829 | { | |
830 | register_intc_controller(&intc_desc); | |
831 | } | |
da14909e MD |
832 | |
833 | static struct { | |
834 | /* BSC */ | |
835 | unsigned long mmselr; | |
836 | unsigned long cs0bcr; | |
837 | unsigned long cs4bcr; | |
838 | unsigned long cs5abcr; | |
839 | unsigned long cs5bbcr; | |
840 | unsigned long cs6abcr; | |
841 | unsigned long cs6bbcr; | |
842 | unsigned long cs4wcr; | |
843 | unsigned long cs5awcr; | |
844 | unsigned long cs5bwcr; | |
845 | unsigned long cs6awcr; | |
846 | unsigned long cs6bwcr; | |
847 | /* INTC */ | |
848 | unsigned short ipra; | |
849 | unsigned short iprb; | |
850 | unsigned short iprc; | |
851 | unsigned short iprd; | |
852 | unsigned short ipre; | |
853 | unsigned short iprf; | |
854 | unsigned short iprg; | |
855 | unsigned short iprh; | |
856 | unsigned short ipri; | |
857 | unsigned short iprj; | |
858 | unsigned short iprk; | |
859 | unsigned short iprl; | |
860 | unsigned char imr0; | |
861 | unsigned char imr1; | |
862 | unsigned char imr2; | |
863 | unsigned char imr3; | |
864 | unsigned char imr4; | |
865 | unsigned char imr5; | |
866 | unsigned char imr6; | |
867 | unsigned char imr7; | |
868 | unsigned char imr8; | |
869 | unsigned char imr9; | |
870 | unsigned char imr10; | |
871 | unsigned char imr11; | |
872 | unsigned char imr12; | |
c4b973f5 MD |
873 | /* RWDT */ |
874 | unsigned short rwtcnt; | |
875 | unsigned short rwtcsr; | |
da14909e MD |
876 | } sh7724_rstandby_state; |
877 | ||
878 | static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb, | |
879 | unsigned long flags, void *unused) | |
880 | { | |
881 | if (!(flags & SUSP_SH_RSTANDBY)) | |
882 | return NOTIFY_DONE; | |
883 | ||
884 | /* BCR */ | |
885 | sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */ | |
886 | sh7724_rstandby_state.mmselr |= 0xa5a50000; | |
887 | sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */ | |
888 | sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */ | |
889 | sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */ | |
890 | sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */ | |
891 | sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */ | |
892 | sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */ | |
893 | sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */ | |
894 | sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */ | |
895 | sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */ | |
896 | sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */ | |
897 | sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */ | |
898 | ||
899 | /* INTC */ | |
900 | sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */ | |
901 | sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */ | |
902 | sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */ | |
903 | sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */ | |
904 | sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */ | |
905 | sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */ | |
906 | sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */ | |
907 | sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */ | |
908 | sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */ | |
909 | sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */ | |
910 | sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */ | |
911 | sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */ | |
912 | sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */ | |
913 | sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */ | |
914 | sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */ | |
915 | sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */ | |
916 | sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */ | |
917 | sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */ | |
918 | sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */ | |
919 | sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */ | |
920 | sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */ | |
921 | sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */ | |
922 | sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */ | |
923 | sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */ | |
924 | sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */ | |
925 | ||
c4b973f5 MD |
926 | /* RWDT */ |
927 | sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */ | |
928 | sh7724_rstandby_state.rwtcnt |= 0x5a00; | |
929 | sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */ | |
930 | sh7724_rstandby_state.rwtcsr |= 0xa500; | |
931 | __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004); | |
932 | ||
da14909e MD |
933 | return NOTIFY_DONE; |
934 | } | |
935 | ||
936 | static int sh7724_post_sleep_notifier_call(struct notifier_block *nb, | |
937 | unsigned long flags, void *unused) | |
938 | { | |
939 | if (!(flags & SUSP_SH_RSTANDBY)) | |
940 | return NOTIFY_DONE; | |
941 | ||
942 | /* BCR */ | |
943 | __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */ | |
944 | __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */ | |
945 | __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */ | |
946 | __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */ | |
947 | __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */ | |
948 | __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */ | |
949 | __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */ | |
950 | __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */ | |
951 | __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */ | |
952 | __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */ | |
953 | __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */ | |
954 | __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */ | |
955 | ||
956 | /* INTC */ | |
957 | __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */ | |
958 | __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */ | |
959 | __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */ | |
960 | __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */ | |
961 | __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */ | |
962 | __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */ | |
963 | __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */ | |
964 | __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */ | |
965 | __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */ | |
966 | __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */ | |
967 | __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */ | |
968 | __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */ | |
969 | __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */ | |
970 | __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */ | |
971 | __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */ | |
972 | __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */ | |
973 | __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */ | |
974 | __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */ | |
975 | __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */ | |
976 | __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */ | |
977 | __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */ | |
978 | __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */ | |
979 | __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */ | |
980 | __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */ | |
981 | __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */ | |
982 | ||
c4b973f5 MD |
983 | /* RWDT */ |
984 | __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */ | |
985 | __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */ | |
986 | ||
da14909e MD |
987 | return NOTIFY_DONE; |
988 | } | |
989 | ||
990 | static struct notifier_block sh7724_pre_sleep_notifier = { | |
991 | .notifier_call = sh7724_pre_sleep_notifier_call, | |
992 | .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU), | |
993 | }; | |
994 | ||
995 | static struct notifier_block sh7724_post_sleep_notifier = { | |
996 | .notifier_call = sh7724_post_sleep_notifier_call, | |
997 | .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU), | |
998 | }; | |
999 | ||
1000 | static int __init sh7724_sleep_setup(void) | |
1001 | { | |
1002 | atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list, | |
1003 | &sh7724_pre_sleep_notifier); | |
1004 | ||
1005 | atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list, | |
1006 | &sh7724_post_sleep_notifier); | |
1007 | return 0; | |
1008 | } | |
1009 | arch_initcall(sh7724_sleep_setup); | |
1010 |