[linux-2.6-block.git] / arch / sh / kernel / cpu / sh4a / setup-sh7724.c

/*
 * SH7724 Setup
 *
 * Copyright (C) 2009 Renesas Solutions Corp.
 *
 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
 *
 * Based on SH7723 Setup
 * Copyright (C) 2008  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/mm.h>
#include <linux/serial_sci.h>
#include <linux/uio_driver.h>
#include <linux/sh_cmt.h>
#include <linux/io.h>
#include <asm/clock.h>
#include <asm/mmzone.h>

/* Serial */
static struct plat_sci_port sci_platform_data[] = {
	{
		.mapbase        = 0xffe00000,
		.flags          = UPF_BOOT_AUTOCONF,
		.type           = PORT_SCIF,
		.irqs           = { 80, 80, 80, 80 },
	}, {
		.mapbase        = 0xffe10000,
		.flags          = UPF_BOOT_AUTOCONF,
		.type           = PORT_SCIF,
		.irqs           = { 81, 81, 81, 81 },
	}, {
		.mapbase        = 0xffe20000,
		.flags          = UPF_BOOT_AUTOCONF,
		.type           = PORT_SCIF,
		.irqs           = { 82, 82, 82, 82 },
	}, {
		.mapbase	= 0xa4e30000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIFA,
		.irqs		= { 56, 56, 56, 56 },
	}, {
		.mapbase	= 0xa4e40000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIFA,
		.irqs		= { 88, 88, 88, 88 },
	}, {
		.mapbase	= 0xa4e50000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIFA,
		.irqs		= { 109, 109, 109, 109 },
	}, {
		.flags = 0,
	}
};

static struct platform_device sci_device = {
	.name		= "sh-sci",
	.id		= -1,
	.dev		= {
		.platform_data	= sci_platform_data,
	},
};

/* RTC */
static struct resource rtc_resources[] = {
	[0] = {
		.start	= 0xa465fec0,
		.end	= 0xa465fec0 + 0x58 - 1,
		.flags	= IORESOURCE_IO,
	},
	[1] = {
		/* Period IRQ */
		.start	= 69,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		/* Carry IRQ */
		.start	= 70,
		.flags	= IORESOURCE_IRQ,
	},
	[3] = {
		/* Alarm IRQ */
		.start	= 68,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device rtc_device = {
	.name		= "sh-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(rtc_resources),
	.resource	= rtc_resources,
};

static struct platform_device *sh7724_devices[] __initdata = {
	&sci_device,
	&rtc_device,
};

static int __init sh7724_devices_setup(void)
{
	clk_always_enable("rtc0");   /* RTC */

	return platform_add_devices(sh7724_devices,
				    ARRAY_SIZE(sh7724_devices));
}
device_initcall(sh7724_devices_setup);

enum {
	UNUSED = 0,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	HUDI,
	DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
	_2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK,
	DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
	VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI,
	SCIFA_SCIFA0,
	VPU_VPUI,
	TPU_TPUI,
	CEU21I,
	BEU21I,
	USB_USI0,
	ATAPI,
	RTC_ATI, RTC_PRI, RTC_CUI,
	DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
	DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
	KEYSC_KEYI,
	SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
	VEU3F0I,
	MSIOF_MSIOFI0, MSIOF_MSIOFI1,
	SPU_SPUI0, SPU_SPUI1,
	SCIFA_SCIFA1,
/*	ICB_ICBI, */
	ETHI,
	I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
	I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
	SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2,
	CMT_CMTI,
	TSIF_TSIFI,
/*	ICB_LMBI, */
	FSI_FSI,
	SCIFA_SCIFA2,
	TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
	IRDA_IRDAI,
	SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
	JPU_JPUI,
	MMC_MMCI0, MMC_MMCI1, MMC_MMCI2,
	LCDC_LCDCI,
	TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,

	/* interrupt groups */
	DMAC1A, _2DG, DMAC0A, VIO, RTC,
	DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMC,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),

	INTC_VECT(DMAC1A_DEI0, 0x700),
	INTC_VECT(DMAC1A_DEI1, 0x720),
	INTC_VECT(DMAC1A_DEI2, 0x740),
	INTC_VECT(DMAC1A_DEI3, 0x760),

	INTC_VECT(_2DG_TRI, 0x780),
	INTC_VECT(_2DG_INI, 0x7A0),
	INTC_VECT(_2DG_CEI, 0x7C0),
	INTC_VECT(_2DG_BRK, 0x7E0),

	INTC_VECT(DMAC0A_DEI0, 0x800),
	INTC_VECT(DMAC0A_DEI1, 0x820),
	INTC_VECT(DMAC0A_DEI2, 0x840),
	INTC_VECT(DMAC0A_DEI3, 0x860),

	INTC_VECT(VIO_CEU20I, 0x880),
	INTC_VECT(VIO_BEU20I, 0x8A0),
	INTC_VECT(VIO_VEU3F1, 0x8C0),
	INTC_VECT(VIO_VOUI, 0x8E0),

	INTC_VECT(SCIFA_SCIFA0, 0x900),
	INTC_VECT(VPU_VPUI, 0x980),
	INTC_VECT(TPU_TPUI, 0x9A0),
	INTC_VECT(CEU21I, 0x9E0),
	INTC_VECT(BEU21I, 0xA00),
	INTC_VECT(USB_USI0, 0xA20),
	INTC_VECT(ATAPI, 0xA60),

	INTC_VECT(RTC_ATI, 0xA80),
	INTC_VECT(RTC_PRI, 0xAA0),
	INTC_VECT(RTC_CUI, 0xAC0),

	INTC_VECT(DMAC1B_DEI4, 0xB00),
	INTC_VECT(DMAC1B_DEI5, 0xB20),
	INTC_VECT(DMAC1B_DADERR, 0xB40),

	INTC_VECT(DMAC0B_DEI4, 0xB80),
	INTC_VECT(DMAC0B_DEI5, 0xBA0),
	INTC_VECT(DMAC0B_DADERR, 0xBC0),

	INTC_VECT(KEYSC_KEYI, 0xBE0),
	INTC_VECT(SCIF_SCIF0, 0xC00),
	INTC_VECT(SCIF_SCIF1, 0xC20),
	INTC_VECT(SCIF_SCIF2, 0xC40),
	INTC_VECT(VEU3F0I, 0xC60),
	INTC_VECT(MSIOF_MSIOFI0, 0xC80),
	INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
	INTC_VECT(SPU_SPUI0, 0xCC0),
	INTC_VECT(SPU_SPUI1, 0xCE0),
	INTC_VECT(SCIFA_SCIFA1, 0xD00),

/*	INTC_VECT(ICB_ICBI, 0xD20), */
	INTC_VECT(ETHI, 0xD60),

	INTC_VECT(I2C1_ALI, 0xD80),
	INTC_VECT(I2C1_TACKI, 0xDA0),
	INTC_VECT(I2C1_WAITI, 0xDC0),
	INTC_VECT(I2C1_DTEI, 0xDE0),

	INTC_VECT(I2C0_ALI, 0xE00),
	INTC_VECT(I2C0_TACKI, 0xE20),
	INTC_VECT(I2C0_WAITI, 0xE40),
	INTC_VECT(I2C0_DTEI, 0xE60),

	INTC_VECT(SDHI0_SDHII0, 0xE80),
	INTC_VECT(SDHI0_SDHII1, 0xEA0),
	INTC_VECT(SDHI0_SDHII2, 0xEC0),

	INTC_VECT(CMT_CMTI, 0xF00),
	INTC_VECT(TSIF_TSIFI, 0xF20),
/*	INTC_VECT(ICB_LMBI, 0xF60), */
	INTC_VECT(FSI_FSI, 0xF80),
	INTC_VECT(SCIFA_SCIFA2, 0xFA0),

	INTC_VECT(TMU0_TUNI0, 0x400),
	INTC_VECT(TMU0_TUNI1, 0x420),
	INTC_VECT(TMU0_TUNI2, 0x440),

	INTC_VECT(IRDA_IRDAI, 0x480),

	INTC_VECT(SDHI1_SDHII0, 0x4E0),
	INTC_VECT(SDHI1_SDHII1, 0x500),
	INTC_VECT(SDHI1_SDHII2, 0x520),

	INTC_VECT(JPU_JPUI, 0x560),

	INTC_VECT(MMC_MMCI0, 0x580),
	INTC_VECT(MMC_MMCI1, 0x5A0),
	INTC_VECT(MMC_MMCI2, 0x5C0),

	INTC_VECT(LCDC_LCDCI, 0xF40),

	INTC_VECT(TMU1_TUNI0, 0x920),
	INTC_VECT(TMU1_TUNI1, 0x940),
	INTC_VECT(TMU1_TUNI2, 0x960),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
	INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK),
	INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
	INTC_GROUP(VIO, VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI),
	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
	INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
	INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
	INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
	INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
	INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2),
	INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
	INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
	INTC_GROUP(MMC, MMC_MMCI0, MMC_MMCI1, MMC_MMCI2),
};

/* FIXMEEEEEEEEEEEEEEEEEEE !!!!! */
/* very bad manual !! */
static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
	  { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
	    /*SDHII3?*/0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	  { VIO_VOUI, VIO_VEU3F1, VIO_BEU20I, VIO_CEU20I,
	    DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	  { 0, 0, 0, VPU_VPUI, ATAPI, ETHI, 0, /*SCIFA3*/SCIFA_SCIFA0 } },
	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	  { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
	    SPU_SPUI1, SPU_SPUI0, BEU21I, IRDA_IRDAI } },
	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	  { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
	    JPU_JPUI, 0, 0, LCDC_LCDCI } },
	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	  { KEYSC_KEYI, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
	    VEU3F0I, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	  { 0, 0, /*ICB_ICBI*/0, /*SCIFA4*/SCIFA_SCIFA1,
	    CEU21I, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	  { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
	    I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
	  { /*SDHII3*/0, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
	    0, 0, /*SCIFA5*/SCIFA_SCIFA2, FSI_FSI } },
	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	  { 0, 0, 0, CMT_CMTI, 0, /*USB1*/0, USB_USI0, 0 } },
	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	  { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
	    0, RTC_ATI, RTC_PRI, RTC_CUI } },
	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	  { _2DG_BRK, _2DG_CEI, _2DG_INI, _2DG_TRI,
	    0, TPU_TPUI, /*ICB_LMBI*/0, TSIF_TSIFI } },
	{ 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
	  { 0, 0, 0, 0, 0, 0, 0, 0/*2DDMAC*/ } },
	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
					     TMU0_TUNI2, IRDA_IRDAI } },
	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU_JPUI, LCDC_LCDCI,
					     DMAC1A, BEU21I } },
	{ 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
					     TMU1_TUNI2, SPU } },
	{ 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMC, 0, ATAPI } },
	{ 0xa4080010, 0, 16, 4, /* IPRE */
	  { DMAC0A, /*BEU?VEU?*/VIO, /*SCIFA3*/SCIFA_SCIFA0, /*VPU5F*/
	    VPU_VPUI } },
	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B,
					     USB_USI0, CMT_CMTI } },
	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
					     SCIF_SCIF2, VEU3F0I } },
	{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
					     I2C1, I2C0 } },
	{ 0xa4080020, 0, 16, 4, /* IPRI */ { /*SCIFA4*/SCIFA_SCIFA1, /*ICB*/0,
					     TSIF_TSIFI, _2DG/*ICB?*/ } },
	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU21I, ETHI, FSI_FSI, SDHI1 } },
	{ 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, /*ICB?*/0, SDHI0 } },
	{ 0xa408002c, 0, 16, 4, /* IPRL */ { /*SCIFA5*/SCIFA_SCIFA2, 0,
					     TPU_TPUI, /*2DDMAC*/0 } },
	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_sense_reg sense_registers[] __initdata = {
	{ 0xa414001c, 16, 2, /* ICR1 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_mask_reg ack_registers[] __initdata = {
	{ 0xa4140024, 0, 8, /* INTREQ00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
			     mask_registers, prio_registers, sense_registers,
			     ack_registers);

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}
Commit	Line	Data
0207a2ef KM	1	/*
	2	* SH7724 Setup
	3	*
	4	* Copyright (C) 2009 Renesas Solutions Corp.
	5	*
	6	* Kuninori Morimoto <morimoto.kuninori@renesas.com>
	7	*
	8	* Based on SH7723 Setup
	9	* Copyright (C) 2008 Paul Mundt
	10	*
	11	* This file is subject to the terms and conditions of the GNU General Public
	12	* License. See the file "COPYING" in the main directory of this archive
	13	* for more details.
	14	*/
	15	#include <linux/platform_device.h>
	16	#include <linux/init.h>
	17	#include <linux/serial.h>
	18	#include <linux/mm.h>
	19	#include <linux/serial_sci.h>
	20	#include <linux/uio_driver.h>
	21	#include <linux/sh_cmt.h>
	22	#include <linux/io.h>
	23	#include <asm/clock.h>
	24	#include <asm/mmzone.h>
	25
	26	/* Serial */
	27	static struct plat_sci_port sci_platform_data[] = {
	28	{
	29	.mapbase = 0xffe00000,
	30	.flags = UPF_BOOT_AUTOCONF,
	31	.type = PORT_SCIF,
	32	.irqs = { 80, 80, 80, 80 },
	33	}, {
	34	.mapbase = 0xffe10000,
	35	.flags = UPF_BOOT_AUTOCONF,
	36	.type = PORT_SCIF,
	37	.irqs = { 81, 81, 81, 81 },
	38	}, {
	39	.mapbase = 0xffe20000,
	40	.flags = UPF_BOOT_AUTOCONF,
	41	.type = PORT_SCIF,
	42	.irqs = { 82, 82, 82, 82 },
	43	}, {
	44	.mapbase = 0xa4e30000,
	45	.flags = UPF_BOOT_AUTOCONF,
	46	.type = PORT_SCIFA,
	47	.irqs = { 56, 56, 56, 56 },
	48	}, {
	49	.mapbase = 0xa4e40000,
	50	.flags = UPF_BOOT_AUTOCONF,
	51	.type = PORT_SCIFA,
	52	.irqs = { 88, 88, 88, 88 },
	53	}, {
	54	.mapbase = 0xa4e50000,
	55	.flags = UPF_BOOT_AUTOCONF,
	56	.type = PORT_SCIFA,
	57	.irqs = { 109, 109, 109, 109 },
	58	}, {
	59	.flags = 0,
	60	}
	61	};
	62
	63	static struct platform_device sci_device = {
	64	.name = "sh-sci",
65	.id = -1,
66	.dev = {
67	.platform_data = sci_platform_data,
68	},
69	};
70
71	/* RTC */
72	static struct resource rtc_resources[] = {
73	[0] = {
74	.start = 0xa465fec0,
75	.end = 0xa465fec0 + 0x58 - 1,
76	.flags = IORESOURCE_IO,
77	},
78	[1] = {
79	/* Period IRQ */
80	.start = 69,
81	.flags = IORESOURCE_IRQ,
82	},
83	[2] = {
84	/* Carry IRQ */
85	.start = 70,
86	.flags = IORESOURCE_IRQ,
87	},
88	[3] = {
89	/* Alarm IRQ */
90	.start = 68,
91	.flags = IORESOURCE_IRQ,
92	},
93	};
94
95	static struct platform_device rtc_device = {
96	.name = "sh-rtc",
97	.id = -1,
98	.num_resources = ARRAY_SIZE(rtc_resources),
99	.resource = rtc_resources,
100	};
101
102	static struct platform_device *sh7724_devices[] __initdata = {
103	&sci_device,
104	&rtc_device,
105	};
106
107	static int __init sh7724_devices_setup(void)
108	{
109	clk_always_enable("rtc0"); /* RTC */
110
111	return platform_add_devices(sh7724_devices,
112	ARRAY_SIZE(sh7724_devices));
113	}
114	device_initcall(sh7724_devices_setup);
115
116	enum {
117	UNUSED = 0,
118
119	/* interrupt sources */
120	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
121	HUDI,
122	DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
123	_2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK,
124	DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
125	VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI,
126	SCIFA_SCIFA0,
127	VPU_VPUI,
128	TPU_TPUI,
129	CEU21I,
130	BEU21I,
131	USB_USI0,
132	ATAPI,
133	RTC_ATI, RTC_PRI, RTC_CUI,
134	DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
135	DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
136	KEYSC_KEYI,
137	SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
138	VEU3F0I,
139	MSIOF_MSIOFI0, MSIOF_MSIOFI1,
140	SPU_SPUI0, SPU_SPUI1,
141	SCIFA_SCIFA1,
142	/* ICB_ICBI, */
143	ETHI,
144	I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
145	I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
146	SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2,
147	CMT_CMTI,
148	TSIF_TSIFI,
149	/* ICB_LMBI, */
150	FSI_FSI,
151	SCIFA_SCIFA2,
152	TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
153	IRDA_IRDAI,
154	SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
155	JPU_JPUI,
156	MMC_MMCI0, MMC_MMCI1, MMC_MMCI2,
157	LCDC_LCDCI,
158	TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
159
160	/* interrupt groups */
161	DMAC1A, _2DG, DMAC0A, VIO, RTC,
162	DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMC,
163	};
164
165	static struct intc_vect vectors[] __initdata = {
166	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
167	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
168	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
169	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
170
171	INTC_VECT(DMAC1A_DEI0, 0x700),
172	INTC_VECT(DMAC1A_DEI1, 0x720),
173	INTC_VECT(DMAC1A_DEI2, 0x740),
174	INTC_VECT(DMAC1A_DEI3, 0x760),
175
176	INTC_VECT(_2DG_TRI, 0x780),
177	INTC_VECT(_2DG_INI, 0x7A0),
178	INTC_VECT(_2DG_CEI, 0x7C0),
179	INTC_VECT(_2DG_BRK, 0x7E0),
180
181	INTC_VECT(DMAC0A_DEI0, 0x800),
182	INTC_VECT(DMAC0A_DEI1, 0x820),
183	INTC_VECT(DMAC0A_DEI2, 0x840),
184	INTC_VECT(DMAC0A_DEI3, 0x860),
185
186	INTC_VECT(VIO_CEU20I, 0x880),
187	INTC_VECT(VIO_BEU20I, 0x8A0),
188	INTC_VECT(VIO_VEU3F1, 0x8C0),
189	INTC_VECT(VIO_VOUI, 0x8E0),
190
191	INTC_VECT(SCIFA_SCIFA0, 0x900),
192	INTC_VECT(VPU_VPUI, 0x980),
193	INTC_VECT(TPU_TPUI, 0x9A0),
194	INTC_VECT(CEU21I, 0x9E0),
195	INTC_VECT(BEU21I, 0xA00),
196	INTC_VECT(USB_USI0, 0xA20),
197	INTC_VECT(ATAPI, 0xA60),
198
199	INTC_VECT(RTC_ATI, 0xA80),
200	INTC_VECT(RTC_PRI, 0xAA0),
201	INTC_VECT(RTC_CUI, 0xAC0),
202
203	INTC_VECT(DMAC1B_DEI4, 0xB00),
204	INTC_VECT(DMAC1B_DEI5, 0xB20),
205	INTC_VECT(DMAC1B_DADERR, 0xB40),
206
207	INTC_VECT(DMAC0B_DEI4, 0xB80),
208	INTC_VECT(DMAC0B_DEI5, 0xBA0),
209	INTC_VECT(DMAC0B_DADERR, 0xBC0),
210
211	INTC_VECT(KEYSC_KEYI, 0xBE0),
212	INTC_VECT(SCIF_SCIF0, 0xC00),
213	INTC_VECT(SCIF_SCIF1, 0xC20),
214	INTC_VECT(SCIF_SCIF2, 0xC40),
215	INTC_VECT(VEU3F0I, 0xC60),
216	INTC_VECT(MSIOF_MSIOFI0, 0xC80),
217	INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
218	INTC_VECT(SPU_SPUI0, 0xCC0),
219	INTC_VECT(SPU_SPUI1, 0xCE0),
220	INTC_VECT(SCIFA_SCIFA1, 0xD00),
221
222	/* INTC_VECT(ICB_ICBI, 0xD20), */
223	INTC_VECT(ETHI, 0xD60),
224
225	INTC_VECT(I2C1_ALI, 0xD80),
226	INTC_VECT(I2C1_TACKI, 0xDA0),
227	INTC_VECT(I2C1_WAITI, 0xDC0),
228	INTC_VECT(I2C1_DTEI, 0xDE0),
229
230	INTC_VECT(I2C0_ALI, 0xE00),
231	INTC_VECT(I2C0_TACKI, 0xE20),
232	INTC_VECT(I2C0_WAITI, 0xE40),
233	INTC_VECT(I2C0_DTEI, 0xE60),
234
235	INTC_VECT(SDHI0_SDHII0, 0xE80),
236	INTC_VECT(SDHI0_SDHII1, 0xEA0),
237	INTC_VECT(SDHI0_SDHII2, 0xEC0),
238
239	INTC_VECT(CMT_CMTI, 0xF00),
240	INTC_VECT(TSIF_TSIFI, 0xF20),
241	/* INTC_VECT(ICB_LMBI, 0xF60), */
242	INTC_VECT(FSI_FSI, 0xF80),
243	INTC_VECT(SCIFA_SCIFA2, 0xFA0),
244
245	INTC_VECT(TMU0_TUNI0, 0x400),
246	INTC_VECT(TMU0_TUNI1, 0x420),
247	INTC_VECT(TMU0_TUNI2, 0x440),
248
249	INTC_VECT(IRDA_IRDAI, 0x480),
250
251	INTC_VECT(SDHI1_SDHII0, 0x4E0),
252	INTC_VECT(SDHI1_SDHII1, 0x500),
253	INTC_VECT(SDHI1_SDHII2, 0x520),
254
255	INTC_VECT(JPU_JPUI, 0x560),
256
257	INTC_VECT(MMC_MMCI0, 0x580),
258	INTC_VECT(MMC_MMCI1, 0x5A0),
259	INTC_VECT(MMC_MMCI2, 0x5C0),
260
261	INTC_VECT(LCDC_LCDCI, 0xF40),
262
263	INTC_VECT(TMU1_TUNI0, 0x920),
264	INTC_VECT(TMU1_TUNI1, 0x940),
265	INTC_VECT(TMU1_TUNI2, 0x960),
266	};
267
268	static struct intc_group groups[] __initdata = {
269	INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
270	INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK),
271	INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
272	INTC_GROUP(VIO, VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI),
273	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
274	INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
275	INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
276	INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
277	INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
278	INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2),
279	INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
280	INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
281	INTC_GROUP(MMC, MMC_MMCI0, MMC_MMCI1, MMC_MMCI2),
282	};
283
284	/* FIXMEEEEEEEEEEEEEEEEEEE !!!!! */
285	/* very bad manual !! */
286	static struct intc_mask_reg mask_registers[] __initdata = {
287	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
288	{ 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
289	/SDHII3?/0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
290	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
291	{ VIO_VOUI, VIO_VEU3F1, VIO_BEU20I, VIO_CEU20I,
292	DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
293	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
294	{ 0, 0, 0, VPU_VPUI, ATAPI, ETHI, 0, /SCIFA3/SCIFA_SCIFA0 } },
295	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
296	{ DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
297	SPU_SPUI1, SPU_SPUI0, BEU21I, IRDA_IRDAI } },
298	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
299	{ 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
300	JPU_JPUI, 0, 0, LCDC_LCDCI } },
301	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
302	{ KEYSC_KEYI, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
303	VEU3F0I, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
304	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
305	{ 0, 0, /ICB_ICBI/0, /SCIFA4/SCIFA_SCIFA1,
306	CEU21I, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
307	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
308	{ I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
309	I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
310	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
311	{ /SDHII3/0, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
312	0, 0, /SCIFA5/SCIFA_SCIFA2, FSI_FSI } },
313	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
314	{ 0, 0, 0, CMT_CMTI, 0, /USB1/0, USB_USI0, 0 } },
315	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
316	{ 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
317	0, RTC_ATI, RTC_PRI, RTC_CUI } },
318	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
319	{ _2DG_BRK, _2DG_CEI, _2DG_INI, _2DG_TRI,
320	0, TPU_TPUI, /ICB_LMBI/0, TSIF_TSIFI } },
321	{ 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
322	{ 0, 0, 0, 0, 0, 0, 0, 0/2DDMAC/ } },
323	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
324	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
325	};
326
327	static struct intc_prio_reg prio_registers[] __initdata = {
328	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
329	TMU0_TUNI2, IRDA_IRDAI } },
330	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU_JPUI, LCDC_LCDCI,
331	DMAC1A, BEU21I } },
332	{ 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
333	TMU1_TUNI2, SPU } },
334	{ 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMC, 0, ATAPI } },
335	{ 0xa4080010, 0, 16, 4, /* IPRE */
336	{ DMAC0A, /BEU?VEU?/VIO, /SCIFA3/SCIFA_SCIFA0, /VPU5F/
337	VPU_VPUI } },
338	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B,
339	USB_USI0, CMT_CMTI } },
340	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
341	SCIF_SCIF2, VEU3F0I } },
342	{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
343	I2C1, I2C0 } },
344	{ 0xa4080020, 0, 16, 4, /* IPRI / { /SCIFA4/SCIFA_SCIFA1, /ICB*/0,
345	TSIF_TSIFI, _2DG/ICB?/ } },
346	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU21I, ETHI, FSI_FSI, SDHI1 } },
347	{ 0xa4080028, 0, 16, 4, /* IPRK / { RTC, DMAC1B, /ICB?*/0, SDHI0 } },
348	{ 0xa408002c, 0, 16, 4, /* IPRL / { /SCIFA5*/SCIFA_SCIFA2, 0,
349	TPU_TPUI, /2DDMAC/0 } },
350	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
351	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
352	};
353
354	static struct intc_sense_reg sense_registers[] __initdata = {
355	{ 0xa414001c, 16, 2, /* ICR1 */
356	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
357	};
358
359	static struct intc_mask_reg ack_registers[] __initdata = {
360	{ 0xa4140024, 0, 8, /* INTREQ00 */
361	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
362	};
363
364	static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
365	mask_registers, prio_registers, sense_registers,
366	ack_registers);
367
368	void __init plat_irq_setup(void)
369	{
370	register_intc_controller(&intc_desc);
371	}