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9d4436a6 YS |
1 | /* |
2 | * SH7206 Setup | |
3 | * | |
4 | * Copyright (C) 2006 Yoshinori Sato | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/serial.h> | |
13 | #include <asm/sci.h> | |
14 | ||
15 | static struct plat_sci_port sci_platform_data[] = { | |
16 | { | |
17 | .mapbase = 0xfffe8000, | |
18 | .flags = UPF_BOOT_AUTOCONF, | |
19 | .type = PORT_SCIF, | |
c4773bc2 | 20 | .irqs = { 241, 242, 243, 240 }, |
9d4436a6 YS |
21 | }, { |
22 | .mapbase = 0xfffe8800, | |
23 | .flags = UPF_BOOT_AUTOCONF, | |
24 | .type = PORT_SCIF, | |
c4773bc2 | 25 | .irqs = { 245, 246, 247, 244 }, |
9d4436a6 YS |
26 | }, { |
27 | .mapbase = 0xfffe9000, | |
28 | .flags = UPF_BOOT_AUTOCONF, | |
29 | .type = PORT_SCIF, | |
c4773bc2 | 30 | .irqs = { 249, 250, 251, 248 }, |
9d4436a6 YS |
31 | }, { |
32 | .mapbase = 0xfffe9800, | |
33 | .flags = UPF_BOOT_AUTOCONF, | |
34 | .type = PORT_SCIF, | |
c4773bc2 | 35 | .irqs = { 253, 254, 255, 252 }, |
9d4436a6 YS |
36 | }, { |
37 | .flags = 0, | |
38 | } | |
39 | }; | |
40 | ||
41 | static struct platform_device sci_device = { | |
42 | .name = "sh-sci", | |
43 | .id = -1, | |
44 | .dev = { | |
45 | .platform_data = sci_platform_data, | |
46 | }, | |
47 | }; | |
48 | ||
49 | static struct platform_device *sh7206_devices[] __initdata = { | |
50 | &sci_device, | |
51 | }; | |
52 | ||
53 | static int __init sh7206_devices_setup(void) | |
54 | { | |
55 | return platform_add_devices(sh7206_devices, | |
56 | ARRAY_SIZE(sh7206_devices)); | |
57 | } | |
58 | __initcall(sh7206_devices_setup); | |
780a1568 | 59 | |
68abdbbb | 60 | static struct ipr_data ipr_irq_table[] = { |
5c67cd05 YS |
61 | { 140, 7, 12, 2 }, /* CMI0 */ |
62 | { 164, 8, 4, 2 }, /* MTU2_TGI1A */ | |
63 | { 240, 13, 12, 3 }, /* SCIF0_BRI */ | |
64 | { 241, 13, 12, 3 }, /* SCIF0_ERI */ | |
65 | { 242, 13, 12, 3 }, /* SCIF0_RXI */ | |
66 | { 243, 13, 12, 3 }, /* SCIF0_TXI */ | |
67 | { 244, 13, 8, 3 }, /* SCIF1_BRI */ | |
68 | { 245, 13, 8, 3 }, /* SCIF1_ERI */ | |
69 | { 246, 13, 8, 3 }, /* SCIF1_RXI */ | |
70 | { 247, 13, 8, 3 }, /* SCIF1_TXI */ | |
71 | { 248, 13, 4, 3 }, /* SCIF2_BRI */ | |
72 | { 249, 13, 4, 3 }, /* SCIF2_ERI */ | |
73 | { 250, 13, 4, 3 }, /* SCIF2_RXI */ | |
74 | { 251, 13, 4, 3 }, /* SCIF2_TXI */ | |
75 | { 252, 13, 0, 3 }, /* SCIF3_BRI */ | |
76 | { 253, 13, 0, 3 }, /* SCIF3_ERI */ | |
77 | { 254, 13, 0, 3 }, /* SCIF3_RXI */ | |
78 | { 255, 13, 0, 3 }, /* SCIF3_TXI */ | |
79 | }; | |
80 | ||
68abdbbb | 81 | static unsigned long ipr_offsets[] = { |
5c67cd05 YS |
82 | 0xfffe0818, /* IPR01 */ |
83 | 0xfffe081a, /* IPR02 */ | |
84 | 0, /* unused */ | |
85 | 0, /* unused */ | |
86 | 0xfffe0820, /* IPR05 */ | |
87 | 0xfffe0c00, /* IPR06 */ | |
88 | 0xfffe0c02, /* IPR07 */ | |
89 | 0xfffe0c04, /* IPR08 */ | |
90 | 0xfffe0c06, /* IPR09 */ | |
91 | 0xfffe0c08, /* IPR10 */ | |
92 | 0xfffe0c0a, /* IPR11 */ | |
93 | 0xfffe0c0c, /* IPR12 */ | |
94 | 0xfffe0c0e, /* IPR13 */ | |
95 | 0xfffe0c10, /* IPR14 */ | |
780a1568 YS |
96 | }; |
97 | ||
68abdbbb MD |
98 | static struct ipr_desc ipr_irq_desc = { |
99 | .ipr_offsets = ipr_offsets, | |
100 | .nr_offsets = ARRAY_SIZE(ipr_offsets), | |
101 | ||
102 | .ipr_data = ipr_irq_table, | |
103 | .nr_irqs = ARRAY_SIZE(ipr_irq_table), | |
104 | ||
105 | .chip = { | |
106 | .name = "IPR-sh7206", | |
107 | }, | |
108 | }; | |
5c67cd05 | 109 | |
90015c89 | 110 | void __init plat_irq_setup(void) |
780a1568 | 111 | { |
68abdbbb | 112 | register_ipr_controller(&ipr_irq_desc); |
780a1568 | 113 | } |