sunrpc: Include missing smp_lock.h
[linux-2.6-block.git] / arch / sh / include / asm / processor.h
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1#ifndef __ASM_SH_PROCESSOR_H
2#define __ASM_SH_PROCESSOR_H
1da177e4 3
76168c21 4#include <asm/cpu-features.h>
02f7e627 5#include <asm/segment.h>
81b66995 6#include <asm/cache.h>
76168c21 7
343ac722 8#ifndef __ASSEMBLY__
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9/*
10 * CPU type and hardware bug flags. Kept separately for each CPU.
11 *
12 * Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
de02797a 13 * in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
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14 * for parsing the subtype in get_cpu_subtype().
15 */
16enum cpu_type {
17 /* SH-2 types */
b9601c5e 18 CPU_SH7619,
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19
20 /* SH-2A types */
2825999e 21 CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
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22
23 /* SH-3 types */
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24 CPU_SH7705, CPU_SH7706, CPU_SH7707,
25 CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
9465a54f 26 CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
31a49c4b 27 CPU_SH7720, CPU_SH7721, CPU_SH7729,
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28
29 /* SH-4 types */
30 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
f9669187 31 CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
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32
33 /* SH-4A types */
55ba99eb 34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
c01f0f1a 35 CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3,
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36
37 /* SH4AL-DSP types */
9109a30e 38 CPU_SH7343, CPU_SH7722, CPU_SH7366,
1da177e4 39
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40 /* SH-5 types */
41 CPU_SH5_101, CPU_SH5_103,
42
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43 /* Unknown subtype */
44 CPU_SH_NONE
45};
46
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47enum cpu_family {
48 CPU_FAMILY_SH2,
49 CPU_FAMILY_SH2A,
50 CPU_FAMILY_SH3,
51 CPU_FAMILY_SH4,
52 CPU_FAMILY_SH4A,
53 CPU_FAMILY_SH4AL_DSP,
54 CPU_FAMILY_SH5,
55 CPU_FAMILY_UNKNOWN,
56};
57
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58/*
59 * TLB information structure
60 *
61 * Defined for both I and D tlb, per-processor.
62 */
63struct tlb_info {
64 unsigned long long next;
65 unsigned long long first;
66 unsigned long long last;
67
68 unsigned int entries;
69 unsigned int step;
70
71 unsigned long flags;
72};
73
74struct sh_cpuinfo {
e82da214 75 unsigned int type, family;
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76 int cut_major, cut_minor;
77 unsigned long loops_per_jiffy;
78 unsigned long asid_cache;
79
80 struct cache_info icache; /* Primary I-cache */
81 struct cache_info dcache; /* Primary D-cache */
82 struct cache_info scache; /* Secondary cache */
83
84 /* TLB info */
85 struct tlb_info itlb;
86 struct tlb_info dtlb;
87
88 unsigned long flags;
89} __attribute__ ((aligned(L1_CACHE_BYTES)));
90
91extern struct sh_cpuinfo cpu_data[];
92#define boot_cpu_data cpu_data[0]
93#define current_cpu_data cpu_data[smp_processor_id()]
94#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
95
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96#define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory")
97#define cpu_relax() barrier()
98
343ac722 99/* Forward decl */
fa43972f 100struct seq_operations;
3ef2932b 101struct task_struct;
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102
103extern struct pt_regs fake_swapper_regs;
19f9a34f 104
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105/* arch/sh/kernel/process.c */
106extern unsigned int xstate_size;
107extern void free_thread_xstate(struct task_struct *);
108extern struct kmem_cache *task_xstate_cachep;
109
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110/* arch/sh/mm/alignment.c */
111extern int get_unalign_ctl(struct task_struct *, unsigned long addr);
112extern int set_unalign_ctl(struct task_struct *, unsigned int val);
113
114#define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr))
115#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
116
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117/* arch/sh/mm/init.c */
118extern unsigned int mem_init_done;
119
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120/* arch/sh/kernel/setup.c */
121const char *get_cpu_subtype(struct sh_cpuinfo *c);
fa43972f 122extern const struct seq_operations cpuinfo_op;
11c19656 123
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124/* thread_struct flags */
125#define SH_THREAD_UAC_NOPRINT (1 << 0)
126#define SH_THREAD_UAC_SIGBUS (1 << 1)
127#define SH_THREAD_UAC_MASK (SH_THREAD_UAC_NOPRINT | SH_THREAD_UAC_SIGBUS)
128
eb9b9b56 129/* processor boot mode configuration */
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130#define MODE_PIN0 (1 << 0)
131#define MODE_PIN1 (1 << 1)
132#define MODE_PIN2 (1 << 2)
133#define MODE_PIN3 (1 << 3)
134#define MODE_PIN4 (1 << 4)
135#define MODE_PIN5 (1 << 5)
136#define MODE_PIN6 (1 << 6)
137#define MODE_PIN7 (1 << 7)
138#define MODE_PIN8 (1 << 8)
139#define MODE_PIN9 (1 << 9)
140#define MODE_PIN10 (1 << 10)
141#define MODE_PIN11 (1 << 11)
142#define MODE_PIN12 (1 << 12)
143#define MODE_PIN13 (1 << 13)
144#define MODE_PIN14 (1 << 14)
145#define MODE_PIN15 (1 << 15)
146
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147int generic_mode_pins(void);
148int test_mode_pin(int pin);
149
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150#ifdef CONFIG_VSYSCALL
151int vsyscall_init(void);
152#else
153#define vsyscall_init() do { } while (0)
154#endif
155
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156#endif /* __ASSEMBLY__ */
157
158#ifdef CONFIG_SUPERH32
159# include "processor_32.h"
160#else
161# include "processor_64.h"
162#endif
163
1da177e4 164#endif /* __ASM_SH_PROCESSOR_H */