projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 71b973a4 NI |
1 | /* |
| 2 | * arch/sh/include/asm/dma-sh.h | |
| 3 | * | |
| 4 | * Copyright (C) 2000 Takashi YOSHII | |
| 5 | * Copyright (C) 2003 Paul Mundt | |
| 6 | * | |
| 7 | * This file is subject to the terms and conditions of the GNU General Public | |
| 8 | * License. See the file "COPYING" in the main directory of this archive | |
| 9 | * for more details. | |
| 10 | */ | |
| 11 | #ifndef __DMA_SH_H | |
| 12 | #define __DMA_SH_H | |
| 13 | ||
| 039a718e | 14 | #include <asm/dma.h> |
| 71b973a4 NI |
15 | #include <cpu/dma.h> |
| 16 | ||
| 17 | /* DMAOR contorl: The DMAOR access size is different by CPU.*/ | |
| 18 | #if defined(CONFIG_CPU_SUBTYPE_SH7723) || \ | |
| edc67b29 | 19 | defined(CONFIG_CPU_SUBTYPE_SH7724) || \ |
| 71b973a4 NI |
20 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
| 21 | defined(CONFIG_CPU_SUBTYPE_SH7785) | |
| 22 | #define dmaor_read_reg(n) \ | |
| 23 | (n ? ctrl_inw(SH_DMAC_BASE1 + DMAOR) \ | |
| 24 | : ctrl_inw(SH_DMAC_BASE0 + DMAOR)) | |
| 25 | #define dmaor_write_reg(n, data) \ | |
| 26 | (n ? ctrl_outw(data, SH_DMAC_BASE1 + DMAOR) \ | |
| 27 | : ctrl_outw(data, SH_DMAC_BASE0 + DMAOR)) | |
| 28 | #else /* Other CPU */ | |
| 29 | #define dmaor_read_reg(n) ctrl_inw(SH_DMAC_BASE0 + DMAOR) | |
| 30 | #define dmaor_write_reg(n, data) ctrl_outw(data, SH_DMAC_BASE0 + DMAOR) | |
| 31 | #endif | |
| 32 | ||
| 33 | static int dmte_irq_map[] __maybe_unused = { | |
| 039a718e | 34 | #if (MAX_DMA_CHANNELS >= 4) |
| 71b973a4 NI |
35 | DMTE0_IRQ, |
| 36 | DMTE0_IRQ + 1, | |
| 37 | DMTE0_IRQ + 2, | |
| 38 | DMTE0_IRQ + 3, | |
| 39 | #endif | |
| 039a718e | 40 | #if (MAX_DMA_CHANNELS >= 6) |
| 71b973a4 NI |
41 | DMTE4_IRQ, |
| 42 | DMTE4_IRQ + 1, | |
| 43 | #endif | |
| 039a718e | 44 | #if (MAX_DMA_CHANNELS >= 8) |
| 71b973a4 NI |
45 | DMTE6_IRQ, |
| 46 | DMTE6_IRQ + 1, | |
| 47 | #endif | |
| 039a718e | 48 | #if (MAX_DMA_CHANNELS >= 12) |
| 71b973a4 NI |
49 | DMTE8_IRQ, |
| 50 | DMTE9_IRQ, | |
| 51 | DMTE10_IRQ, | |
| 52 | DMTE11_IRQ, | |
| 53 | #endif | |
| 54 | }; | |
| 55 | ||
| 56 | /* Definitions for the SuperH DMAC */ | |
| 57 | #define REQ_L 0x00000000 | |
| 58 | #define REQ_E 0x00080000 | |
| 59 | #define RACK_H 0x00000000 | |
| 60 | #define RACK_L 0x00040000 | |
| 61 | #define ACK_R 0x00000000 | |
| 62 | #define ACK_W 0x00020000 | |
| 63 | #define ACK_H 0x00000000 | |
| 64 | #define ACK_L 0x00010000 | |
| 65 | #define DM_INC 0x00004000 | |
| 66 | #define DM_DEC 0x00008000 | |
| 67 | #define SM_INC 0x00001000 | |
| 68 | #define SM_DEC 0x00002000 | |
| 69 | #define RS_IN 0x00000200 | |
| 70 | #define RS_OUT 0x00000300 | |
| 71 | #define TS_BLK 0x00000040 | |
| 72 | #define TM_BUR 0x00000020 | |
| 73 | #define CHCR_DE 0x00000001 | |
| 74 | #define CHCR_TE 0x00000002 | |
| 75 | #define CHCR_IE 0x00000004 | |
| 76 | ||
| 77 | /* DMAOR definitions */ | |
| 78 | #define DMAOR_AE 0x00000004 | |
| 79 | #define DMAOR_NMIF 0x00000002 | |
| 80 | #define DMAOR_DME 0x00000001 | |
| 81 | ||
| 82 | /* | |
| 83 | * Define the default configuration for dual address memory-memory transfer. | |
| 84 | * The 0x400 value represents auto-request, external->external. | |
| 85 | */ | |
| 86 | #define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32) | |
| 87 | ||
| 88 | /* DMA base address */ | |
| 89 | static u32 dma_base_addr[] __maybe_unused = { | |
| 039a718e | 90 | #if (MAX_DMA_CHANNELS >= 4) |
| 71b973a4 NI |
91 | SH_DMAC_BASE0 + 0x00, /* channel 0 */ |
| 92 | SH_DMAC_BASE0 + 0x10, | |
| 93 | SH_DMAC_BASE0 + 0x20, | |
| 94 | SH_DMAC_BASE0 + 0x30, | |
| 95 | #endif | |
| 039a718e | 96 | #if (MAX_DMA_CHANNELS >= 6) |
| 71b973a4 NI |
97 | SH_DMAC_BASE0 + 0x50, |
| 98 | SH_DMAC_BASE0 + 0x60, | |
| 99 | #endif | |
| 039a718e | 100 | #if (MAX_DMA_CHANNELS >= 8) |
| 71b973a4 NI |
101 | SH_DMAC_BASE1 + 0x00, |
| 102 | SH_DMAC_BASE1 + 0x10, | |
| 103 | #endif | |
| 039a718e | 104 | #if (MAX_DMA_CHANNELS >= 12) |
| 71b973a4 NI |
105 | SH_DMAC_BASE1 + 0x20, |
| 106 | SH_DMAC_BASE1 + 0x30, | |
| 107 | SH_DMAC_BASE1 + 0x50, | |
| 108 | SH_DMAC_BASE1 + 0x60, /* channel 11 */ | |
| 109 | #endif | |
| 110 | }; | |
| 111 | ||
| 112 | /* DMA register */ | |
| 113 | #define SAR 0x00 | |
| 114 | #define DAR 0x04 | |
| 115 | #define TCR 0x08 | |
| 116 | #define CHCR 0x0C | |
| 117 | #define DMAOR 0x40 | |
| 118 | ||
| d8902adc NI |
119 | /* |
| 120 | * for dma engine | |
| 121 | * | |
| 122 | * SuperH DMA mode | |
| 123 | */ | |
| 124 | #define SHDMA_MIX_IRQ (1 << 1) | |
| 125 | #define SHDMA_DMAOR1 (1 << 2) | |
| 126 | #define SHDMA_DMAE1 (1 << 3) | |
| 127 | ||
| 128 | struct sh_dmae_pdata { | |
| 129 | unsigned int mode; | |
| 130 | }; | |
| 131 | ||
| 71b973a4 | 132 | #endif /* __DMA_SH_H */ |