[linux-2.6-block.git] / arch / s390 / include / asm / processor.h

/*
 *  S390 version
 *    Copyright IBM Corp. 1999
 *    Author(s): Hartmut Penner (hp@de.ibm.com),
 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
 *
 *  Derived from "include/asm-i386/processor.h"
 *    Copyright (C) 1994, Linus Torvalds
 */

#ifndef __ASM_S390_PROCESSOR_H
#define __ASM_S390_PROCESSOR_H

#define CIF_MCCK_PENDING	0	/* machine check handling is pending */
#define CIF_ASCE		1	/* user asce needs fixup / uaccess */
#define CIF_NOHZ_DELAY		2	/* delay HZ disable for a tick */
#define CIF_FPU			3	/* restore vector registers */

#define _CIF_MCCK_PENDING	(1<<CIF_MCCK_PENDING)
#define _CIF_ASCE		(1<<CIF_ASCE)
#define _CIF_NOHZ_DELAY		(1<<CIF_NOHZ_DELAY)
#define _CIF_FPU		(1<<CIF_FPU)

#ifndef __ASSEMBLY__

#include <linux/linkage.h>
#include <linux/irqflags.h>
#include <asm/cpu.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include <asm/setup.h>
#include <asm/runtime_instr.h>
#include <asm/fpu-internal.h>

static inline void set_cpu_flag(int flag)
{
	S390_lowcore.cpu_flags |= (1U << flag);
}

static inline void clear_cpu_flag(int flag)
{
	S390_lowcore.cpu_flags &= ~(1U << flag);
}

static inline int test_cpu_flag(int flag)
{
	return !!(S390_lowcore.cpu_flags & (1U << flag));
}

#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })

static inline void get_cpu_id(struct cpuid *ptr)
{
	asm volatile("stidp %0" : "=Q" (*ptr));
}

extern void s390_adjust_jiffies(void);
extern const struct seq_operations cpuinfo_op;
extern int sysctl_ieee_emulation_warnings;
extern void execve_tail(void);

/*
 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
 */

#define TASK_SIZE_OF(tsk)	((tsk)->mm->context.asce_limit)
#define TASK_UNMAPPED_BASE	(test_thread_flag(TIF_31BIT) ? \
					(1UL << 30) : (1UL << 41))
#define TASK_SIZE		TASK_SIZE_OF(current)
#define TASK_MAX_SIZE		(1UL << 53)

#define STACK_TOP		(1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
#define STACK_TOP_MAX		(1UL << 42)

#define HAVE_ARCH_PICK_MMAP_LAYOUT

typedef struct {
        __u32 ar4;
} mm_segment_t;

/*
 * Thread structure
 */
struct thread_struct {
	struct fpu fpu;			/* FP and VX register save area */
	unsigned int  acrs[NUM_ACRS];
        unsigned long ksp;              /* kernel stack pointer             */
	mm_segment_t mm_segment;
	unsigned long gmap_addr;	/* address of last gmap fault. */
	unsigned int gmap_pfault;	/* signal of a pending guest pfault */
	struct per_regs per_user;	/* User specified PER registers */
	struct per_event per_event;	/* Cause of the last PER trap */
	unsigned long per_flags;	/* Flags to control debug behavior */
        /* pfault_wait is used to block the process on a pfault event */
	unsigned long pfault_wait;
	struct list_head list;
	/* cpu runtime instrumentation */
	struct runtime_instr_cb *ri_cb;
	int ri_signum;
	unsigned char trap_tdb[256];	/* Transaction abort diagnose block */
};

/* Flag to disable transactions. */
#define PER_FLAG_NO_TE			1UL
/* Flag to enable random transaction aborts. */
#define PER_FLAG_TE_ABORT_RAND		2UL
/* Flag to specify random transaction abort mode:
 * - abort each transaction at a random instruction before TEND if set.
 * - abort random transactions at a random instruction if cleared.
 */
#define PER_FLAG_TE_ABORT_RAND_TEND	4UL

typedef struct thread_struct thread_struct;

/*
 * Stack layout of a C stack frame.
 */
#ifndef __PACK_STACK
struct stack_frame {
	unsigned long back_chain;
	unsigned long empty1[5];
	unsigned long gprs[10];
	unsigned int  empty2[8];
};
#else
struct stack_frame {
	unsigned long empty1[5];
	unsigned int  empty2[8];
	unsigned long gprs[10];
	unsigned long back_chain;
};
#endif

#define ARCH_MIN_TASKALIGN	8

#define INIT_THREAD {							\
	.ksp = sizeof(init_stack) + (unsigned long) &init_stack,	\
}

/*
 * Do necessary setup to start up a new thread.
 */
#define start_thread(regs, new_psw, new_stackp) do {			\
	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;	\
	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
	regs->gprs[15]	= new_stackp;					\
	execve_tail();							\
} while (0)

#define start_thread31(regs, new_psw, new_stackp) do {			\
	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_BA;			\
	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
	regs->gprs[15]	= new_stackp;					\
	crst_table_downgrade(current->mm, 1UL << 31);			\
	execve_tail();							\
} while (0)

/* Forward declaration, a strange C thing */
struct task_struct;
struct mm_struct;
struct seq_file;

void show_cacheinfo(struct seq_file *m);

/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);

/*
 * Return saved PC of a blocked thread.
 */
extern unsigned long thread_saved_pc(struct task_struct *t);

unsigned long get_wchan(struct task_struct *p);
#define task_pt_regs(tsk) ((struct pt_regs *) \
        (task_stack_page(tsk) + THREAD_SIZE) - 1)
#define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
#define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])

/* Has task runtime instrumentation enabled ? */
#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)

static inline unsigned short stap(void)
{
	unsigned short cpu_address;

	asm volatile("stap %0" : "=m" (cpu_address));
	return cpu_address;
}

/*
 * Give up the time slice of the virtual PU.
 */
void cpu_relax(void);

#define cpu_relax_lowlatency()  barrier()

static inline void psw_set_key(unsigned int key)
{
	asm volatile("spka 0(%0)" : : "d" (key));
}

/*
 * Set PSW to specified value.
 */
static inline void __load_psw(psw_t psw)
{
	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
}

/*
 * Set PSW mask to specified value, while leaving the
 * PSW addr pointing to the next instruction.
 */
static inline void __load_psw_mask (unsigned long mask)
{
	unsigned long addr;
	psw_t psw;

	psw.mask = mask;

	asm volatile(
		"	larl	%0,1f\n"
		"	stg	%0,%O1+8(%R1)\n"
		"	lpswe	%1\n"
		"1:"
		: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
}

/*
 * Extract current PSW mask
 */
static inline unsigned long __extract_psw(void)
{
	unsigned int reg1, reg2;

	asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
	return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
}

/*
 * Rewind PSW instruction address by specified number of bytes.
 */
static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
{
	unsigned long mask;

	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
					  (1UL << 24) - 1;
	return (psw.addr - ilc) & mask;
}

/*
 * Function to stop a processor until the next interrupt occurs
 */
void enabled_wait(void);

/*
 * Function to drop a processor into disabled wait state
 */
static inline void __noreturn disabled_wait(unsigned long code)
{
        unsigned long ctl_buf;
        psw_t dw_psw;

	dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
        dw_psw.addr = code;
        /* 
         * Store status and then load disabled wait psw,
         * the processor is dead afterwards
         */
	asm volatile(
		"	stctg	0,0,0(%2)\n"
		"	ni	4(%2),0xef\n"	/* switch off protection */
		"	lctlg	0,0,0(%2)\n"
		"	lghi	1,0x1000\n"
		"	stpt	0x328(1)\n"	/* store timer */
		"	stckc	0x330(1)\n"	/* store clock comparator */
		"	stpx	0x318(1)\n"	/* store prefix register */
		"	stam	0,15,0x340(1)\n"/* store access registers */
		"	stfpc	0x31c(1)\n"	/* store fpu control */
		"	std	0,0x200(1)\n"	/* store f0 */
		"	std	1,0x208(1)\n"	/* store f1 */
		"	std	2,0x210(1)\n"	/* store f2 */
		"	std	3,0x218(1)\n"	/* store f3 */
		"	std	4,0x220(1)\n"	/* store f4 */
		"	std	5,0x228(1)\n"	/* store f5 */
		"	std	6,0x230(1)\n"	/* store f6 */
		"	std	7,0x238(1)\n"	/* store f7 */
		"	std	8,0x240(1)\n"	/* store f8 */
		"	std	9,0x248(1)\n"	/* store f9 */
		"	std	10,0x250(1)\n"	/* store f10 */
		"	std	11,0x258(1)\n"	/* store f11 */
		"	std	12,0x260(1)\n"	/* store f12 */
		"	std	13,0x268(1)\n"	/* store f13 */
		"	std	14,0x270(1)\n"	/* store f14 */
		"	std	15,0x278(1)\n"	/* store f15 */
		"	stmg	0,15,0x280(1)\n"/* store general registers */
		"	stctg	0,15,0x380(1)\n"/* store control registers */
		"	oi	0x384(1),0x10\n"/* fake protection bit */
		"	lpswe	0(%1)"
		: "=m" (ctl_buf)
		: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
	while (1);
}

/*
 * Use to set psw mask except for the first byte which
 * won't be changed by this function.
 */
static inline void
__set_psw_mask(unsigned long mask)
{
	__load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
}

#define local_mcck_enable() \
	__set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK)
#define local_mcck_disable() \
	__set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT)

/*
 * Basic Machine Check/Program Check Handler.
 */

extern void s390_base_mcck_handler(void);
extern void s390_base_pgm_handler(void);
extern void s390_base_ext_handler(void);

extern void (*s390_base_mcck_handler_fn)(void);
extern void (*s390_base_pgm_handler_fn)(void);
extern void (*s390_base_ext_handler_fn)(void);

#define ARCH_LOW_ADDRESS_LIMIT	0x7fffffffUL

extern int memcpy_real(void *, void *, size_t);
extern void memcpy_absolute(void *, void *, size_t);

#define mem_assign_absolute(dest, val) {			\
	__typeof__(dest) __tmp = (val);				\
								\
	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));		\
	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));	\
}

#endif /* __ASSEMBLY__ */

#endif /* __ASM_S390_PROCESSOR_H */
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* S390 version
a53c8fab	3	* Copyright IBM Corp. 1999
1da177e4 LT	4	* Author(s): Hartmut Penner (hp@de.ibm.com),
	5	* Martin Schwidefsky (schwidefsky@de.ibm.com)
	6	*
	7	* Derived from "include/asm-i386/processor.h"
	8	* Copyright (C) 1994, Linus Torvalds
	9	*/
	10
	11	#ifndef __ASM_S390_PROCESSOR_H
	12	#define __ASM_S390_PROCESSOR_H
	13
d3a73acb MS	14	#define CIF_MCCK_PENDING 0 /* machine check handling is pending */
d3a73acb MS	15	#define CIF_ASCE 1 /* user asce needs fixup / uaccess */
fe0f4976	16	#define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
9977e886	17	#define CIF_FPU 3 /* restore vector registers */
d3a73acb MS	18
	19	#define _CIF_MCCK_PENDING (1<<CIF_MCCK_PENDING)
	20	#define _CIF_ASCE (1<<CIF_ASCE)
fe0f4976	21	#define _CIF_NOHZ_DELAY (1<<CIF_NOHZ_DELAY)
9977e886	22	#define _CIF_FPU (1<<CIF_FPU)
d3a73acb	23
eb608fb3 HC	24	#ifndef __ASSEMBLY__
eb608fb3 HC	25
edd53787	26	#include <linux/linkage.h>
a0616cde	27	#include <linux/irqflags.h>
e86a6ed6	28	#include <asm/cpu.h>
25097bf1	29	#include <asm/page.h>
1da177e4	30	#include <asm/ptrace.h>
25097bf1	31	#include <asm/setup.h>
e4b8b3f3	32	#include <asm/runtime_instr.h>
904818e2	33	#include <asm/fpu-internal.h>
1da177e4	34
d3a73acb MS	35	static inline void set_cpu_flag(int flag)
	36	{
	37	S390_lowcore.cpu_flags \|= (1U << flag);
	38	}
	39
	40	static inline void clear_cpu_flag(int flag)
	41	{
	42	S390_lowcore.cpu_flags &= ~(1U << flag);
	43	}
	44
	45	static inline int test_cpu_flag(int flag)
	46	{
	47	return !!(S390_lowcore.cpu_flags & (1U << flag));
	48	}
	49
fe0f4976 MS	50	#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
fe0f4976 MS	51
1da177e4 LT	52	/*
	53	* Default implementation of macro that returns current
	54	* instruction pointer ("program counter").
	55	*/
94c12cc7	56	#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
1da177e4	57
e86a6ed6	58	static inline void get_cpu_id(struct cpuid *ptr)
72960a02	59	{
987bcdac	60	asm volatile("stidp %0" : "=Q" (*ptr));
72960a02 MH	61	}
72960a02 MH	62
31ee4b2f	63	extern void s390_adjust_jiffies(void);
638ad34a MS	64	extern const struct seq_operations cpuinfo_op;
638ad34a MS	65	extern int sysctl_ieee_emulation_warnings;
65f22a90	66	extern void execve_tail(void);
1da177e4	67
1da177e4	68	/*
f481bfaf	69	* User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
1da177e4	70	*/
1da177e4	71
f481bfaf	72	#define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
5a216a20 MS	73	#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
	74	(1UL << 30) : (1UL << 41))
	75	#define TASK_SIZE TASK_SIZE_OF(current)
ee6ee55b	76	#define TASK_MAX_SIZE (1UL << 53)
1da177e4	77
6252d702 MS	78	#define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
6252d702 MS	79	#define STACK_TOP_MAX (1UL << 42)
922a70d3	80
1da177e4 LT	81	#define HAVE_ARCH_PICK_MMAP_LAYOUT
	82
	83	typedef struct {
	84	__u32 ar4;
	85	} mm_segment_t;
	86
	87	/*
	88	* Thread structure
	89	*/
	90	struct thread_struct {
904818e2	91	struct fpu fpu; /* FP and VX register save area */
1da177e4 LT	92	unsigned int acrs[NUM_ACRS];
1da177e4 LT	93	unsigned long ksp; /* kernel stack pointer */
1da177e4	94	mm_segment_t mm_segment;
e5992f2e	95	unsigned long gmap_addr; /* address of last gmap fault. */
24eb3a82	96	unsigned int gmap_pfault; /* signal of a pending guest pfault */
5e9a2692 MS	97	struct per_regs per_user; /* User specified PER registers */
5e9a2692 MS	98	struct per_event per_event; /* Cause of the last PER trap */
d35339a4	99	unsigned long per_flags; /* Flags to control debug behavior */
1da177e4 LT	100	/* pfault_wait is used to block the process on a pfault event */
1da177e4 LT	101	unsigned long pfault_wait;
f2db2e6c	102	struct list_head list;
e4b8b3f3 JG	103	/* cpu runtime instrumentation */
	104	struct runtime_instr_cb *ri_cb;
	105	int ri_signum;
d35339a4	106	unsigned char trap_tdb[256]; /* Transaction abort diagnose block */
1da177e4 LT	107	};
1da177e4 LT	108
64597f9d MM	109	/* Flag to disable transactions. */
	110	#define PER_FLAG_NO_TE 1UL
	111	/* Flag to enable random transaction aborts. */
	112	#define PER_FLAG_TE_ABORT_RAND 2UL
	113	/* Flag to specify random transaction abort mode:
	114	* - abort each transaction at a random instruction before TEND if set.
	115	* - abort random transactions at a random instruction if cleared.
	116	*/
	117	#define PER_FLAG_TE_ABORT_RAND_TEND 4UL
d35339a4	118
1da177e4 LT	119	typedef struct thread_struct thread_struct;
	120
	121	/*
	122	* Stack layout of a C stack frame.
	123	*/
	124	#ifndef __PACK_STACK
	125	struct stack_frame {
	126	unsigned long back_chain;
	127	unsigned long empty1[5];
	128	unsigned long gprs[10];
	129	unsigned int empty2[8];
	130	};
	131	#else
	132	struct stack_frame {
	133	unsigned long empty1[5];
	134	unsigned int empty2[8];
	135	unsigned long gprs[10];
	136	unsigned long back_chain;
	137	};
	138	#endif
	139
	140	#define ARCH_MIN_TASKALIGN 8
	141
6f3fa3f0 MS	142	#define INIT_THREAD { \
	143	.ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
	144	}
1da177e4 LT	145
	146	/*
	147	* Do necessary setup to start up a new thread.
	148	*/
b50511e4	149	#define start_thread(regs, new_psw, new_stackp) do { \
e258d719	150	regs->psw.mask = PSW_USER_BITS \| PSW_MASK_EA \| PSW_MASK_BA; \
b50511e4 MS	151	regs->psw.addr = new_psw \| PSW_ADDR_AMODE; \
b50511e4 MS	152	regs->gprs[15] = new_stackp; \
65f22a90	153	execve_tail(); \
63506c41 MS	154	} while (0)
63506c41 MS	155
b50511e4	156	#define start_thread31(regs, new_psw, new_stackp) do { \
e258d719	157	regs->psw.mask = PSW_USER_BITS \| PSW_MASK_BA; \
b50511e4 MS	158	regs->psw.addr = new_psw \| PSW_ADDR_AMODE; \
	159	regs->gprs[15] = new_stackp; \
	160	crst_table_downgrade(current->mm, 1UL << 31); \
65f22a90	161	execve_tail(); \
1da177e4 LT	162	} while (0)
1da177e4 LT	163
1da177e4 LT	164	/* Forward declaration, a strange C thing */
	165	struct task_struct;
	166	struct mm_struct;
df5f8314	167	struct seq_file;
1da177e4	168
5a79859a	169	void show_cacheinfo(struct seq_file *m);
6668022c	170
1da177e4 LT	171	/* Free all resources held by a thread. */
1da177e4 LT	172	extern void release_thread(struct task_struct *);
1da177e4	173
1da177e4 LT	174	/*
	175	* Return saved PC of a blocked thread.
	176	*/
	177	extern unsigned long thread_saved_pc(struct task_struct *t);
	178
1da177e4	179	unsigned long get_wchan(struct task_struct *p);
c7584fb6	180	#define task_pt_regs(tsk) ((struct pt_regs *) \
30af7120	181	(task_stack_page(tsk) + THREAD_SIZE) - 1)
c7584fb6 AV	182	#define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
c7584fb6 AV	183	#define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
1da177e4	184
5ebf250d HC	185	/* Has task runtime instrumentation enabled ? */
	186	#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
	187
a0616cde DH	188	static inline unsigned short stap(void)
	189	{
	190	unsigned short cpu_address;
	191
	192	asm volatile("stap %0" : "=m" (cpu_address));
	193	return cpu_address;
	194	}
	195
1da177e4 LT	196	/*
	197	* Give up the time slice of the virtual PU.
	198	*/
4d92f502	199	void cpu_relax(void);
1da177e4	200
3a6bfbc9	201	#define cpu_relax_lowlatency() barrier()
083986e8	202
dc74d7f9 HC	203	static inline void psw_set_key(unsigned int key)
	204	{
	205	asm volatile("spka 0(%0)" : : "d" (key));
	206	}
	207
77fa2245 HC	208	/*
	209	* Set PSW to specified value.
	210	*/
	211	static inline void __load_psw(psw_t psw)
	212	{
987bcdac	213	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
77fa2245 HC	214	}
77fa2245 HC	215
1da177e4 LT	216	/*
	217	* Set PSW mask to specified value, while leaving the
	218	* PSW addr pointing to the next instruction.
	219	*/
1da177e4 LT	220	static inline void __load_psw_mask (unsigned long mask)
	221	{
	222	unsigned long addr;
1da177e4	223	psw_t psw;
77fa2245	224
1da177e4 LT	225	psw.mask = mask;
1da177e4 LT	226
94c12cc7 MS	227	asm volatile(
94c12cc7 MS	228	" larl %0,1f\n"
987bcdac MS	229	" stg %0,%O1+8(%R1)\n"
987bcdac MS	230	" lpswe %1\n"
1da177e4	231	"1:"
987bcdac	232	: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
1da177e4	233	}
ccf45caf	234
22362a0e MS	235	/*
	236	* Extract current PSW mask
	237	*/
	238	static inline unsigned long __extract_psw(void)
	239	{
	240	unsigned int reg1, reg2;
	241
	242	asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
	243	return (((unsigned long) reg1) << 32) \| ((unsigned long) reg2);
	244	}
	245
ccf45caf MS	246	/*
	247	* Rewind PSW instruction address by specified number of bytes.
	248	*/
	249	static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
	250	{
ccf45caf MS	251	unsigned long mask;
	252
	253	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
	254	(psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
	255	(1UL << 24) - 1;
	256	return (psw.addr - ilc) & mask;
ccf45caf	257	}
b5f87f15 MS	258
	259	/*
	260	* Function to stop a processor until the next interrupt occurs
	261	*/
	262	void enabled_wait(void);
	263
1da177e4 LT	264	/*
	265	* Function to drop a processor into disabled wait state
	266	*/
ff2d8b19	267	static inline void __noreturn disabled_wait(unsigned long code)
1da177e4	268	{
1da177e4	269	unsigned long ctl_buf;
77fa2245	270	psw_t dw_psw;
1da177e4	271
b50511e4	272	dw_psw.mask = PSW_MASK_BASE \| PSW_MASK_WAIT \| PSW_MASK_BA \| PSW_MASK_EA;
77fa2245	273	dw_psw.addr = code;
1da177e4 LT	274	/*
	275	* Store status and then load disabled wait psw,
	276	* the processor is dead afterwards
	277	*/
94c12cc7 MS	278	asm volatile(
	279	" stctg 0,0,0(%2)\n"
	280	" ni 4(%2),0xef\n" /* switch off protection */
	281	" lctlg 0,0,0(%2)\n"
	282	" lghi 1,0x1000\n"
	283	" stpt 0x328(1)\n" /* store timer */
	284	" stckc 0x330(1)\n" /* store clock comparator */
	285	" stpx 0x318(1)\n" /* store prefix register */
	286	" stam 0,15,0x340(1)\n"/* store access registers */
	287	" stfpc 0x31c(1)\n" /* store fpu control */
	288	" std 0,0x200(1)\n" /* store f0 */
	289	" std 1,0x208(1)\n" /* store f1 */
	290	" std 2,0x210(1)\n" /* store f2 */
	291	" std 3,0x218(1)\n" /* store f3 */
	292	" std 4,0x220(1)\n" /* store f4 */
	293	" std 5,0x228(1)\n" /* store f5 */
	294	" std 6,0x230(1)\n" /* store f6 */
	295	" std 7,0x238(1)\n" /* store f7 */
	296	" std 8,0x240(1)\n" /* store f8 */
	297	" std 9,0x248(1)\n" /* store f9 */
	298	" std 10,0x250(1)\n" /* store f10 */
	299	" std 11,0x258(1)\n" /* store f11 */
	300	" std 12,0x260(1)\n" /* store f12 */
	301	" std 13,0x268(1)\n" /* store f13 */
	302	" std 14,0x270(1)\n" /* store f14 */
	303	" std 15,0x278(1)\n" /* store f15 */
	304	" stmg 0,15,0x280(1)\n"/* store general registers */
	305	" stctg 0,15,0x380(1)\n"/* store control registers */
	306	" oi 0x384(1),0x10\n"/* fake protection bit */
	307	" lpswe 0(%1)"
	308	: "=m" (ctl_buf)
bdd42b28	309	: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
edd53787	310	while (1);
1da177e4 LT	311	}
1da177e4 LT	312
a0616cde DH	313	/*
	314	* Use to set psw mask except for the first byte which
	315	* won't be changed by this function.
	316	*/
	317	static inline void
	318	__set_psw_mask(unsigned long mask)
	319	{
	320	__load_psw_mask(mask \| (arch_local_save_flags() & ~(-1UL >> 8)));
	321	}
	322
	323	#define local_mcck_enable() \
e258d719	324	__set_psw_mask(PSW_KERNEL_BITS \| PSW_MASK_DAT \| PSW_MASK_MCHECK)
a0616cde	325	#define local_mcck_disable() \
e258d719	326	__set_psw_mask(PSW_KERNEL_BITS \| PSW_MASK_DAT)
a0616cde	327
ab14de6c HC	328	/*
	329	* Basic Machine Check/Program Check Handler.
	330	*/
	331
	332	extern void s390_base_mcck_handler(void);
	333	extern void s390_base_pgm_handler(void);
	334	extern void s390_base_ext_handler(void);
	335
	336	extern void (*s390_base_mcck_handler_fn)(void);
	337	extern void (*s390_base_pgm_handler_fn)(void);
	338	extern void (*s390_base_ext_handler_fn)(void);
	339
dfd54cbc HC	340	#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
dfd54cbc HC	341
fbe76568 HC	342	extern int memcpy_real(void , void , size_t);
	343	extern void memcpy_absolute(void , void , size_t);
	344
	345	#define mem_assign_absolute(dest, val) { \
	346	__typeof__(dest) __tmp = (val); \
	347	\
	348	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
	349	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
	350	}
	351
eb608fb3 HC	352	#endif /* __ASSEMBLY__ */
	353
	354	#endif /* __ASM_S390_PROCESSOR_H */