Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * S390 version |
a53c8fab | 3 | * Copyright IBM Corp. 1999, 2000 |
1da177e4 LT |
4 | * Author(s): Hartmut Penner (hp@de.ibm.com) |
5 | * Ulrich Weigand (weigand@de.ibm.com) | |
6 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
7 | * | |
8 | * Derived from "include/asm-i386/pgtable.h" | |
9 | */ | |
10 | ||
11 | #ifndef _ASM_S390_PGTABLE_H | |
12 | #define _ASM_S390_PGTABLE_H | |
13 | ||
1da177e4 LT |
14 | /* |
15 | * The Linux memory management assumes a three-level page table setup. For | |
16 | * s390 31 bit we "fold" the mid level into the top-level page table, so | |
17 | * that we physically have the same two-level page table as the s390 mmu | |
18 | * expects in 31 bit mode. For s390 64 bit we use three of the five levels | |
19 | * the hardware provides (region first and region second tables are not | |
20 | * used). | |
21 | * | |
22 | * The "pgd_xxx()" functions are trivial for a folded two-level | |
23 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | |
24 | * into the pgd entry) | |
25 | * | |
26 | * This file contains the functions and defines necessary to modify and use | |
27 | * the S390 page table tree. | |
28 | */ | |
29 | #ifndef __ASSEMBLY__ | |
9789db08 | 30 | #include <linux/sched.h> |
2dcea57a | 31 | #include <linux/mm_types.h> |
abf09bed | 32 | #include <linux/page-flags.h> |
1da177e4 | 33 | #include <asm/bug.h> |
b2fa47e6 | 34 | #include <asm/page.h> |
1da177e4 | 35 | |
1da177e4 LT |
36 | extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); |
37 | extern void paging_init(void); | |
2b67fc46 | 38 | extern void vmem_map_init(void); |
1da177e4 LT |
39 | |
40 | /* | |
41 | * The S390 doesn't have any external MMU info: the kernel page | |
42 | * tables contain all the necessary information. | |
43 | */ | |
4b3073e1 | 44 | #define update_mmu_cache(vma, address, ptep) do { } while (0) |
b113da65 | 45 | #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) |
1da177e4 LT |
46 | |
47 | /* | |
238ec4ef | 48 | * ZERO_PAGE is a global shared page that is always zero; used |
1da177e4 LT |
49 | * for zero-mapped memory areas etc.. |
50 | */ | |
238ec4ef MS |
51 | |
52 | extern unsigned long empty_zero_page; | |
53 | extern unsigned long zero_page_mask; | |
54 | ||
55 | #define ZERO_PAGE(vaddr) \ | |
56 | (virt_to_page((void *)(empty_zero_page + \ | |
57 | (((unsigned long)(vaddr)) &zero_page_mask)))) | |
816422ad | 58 | #define __HAVE_COLOR_ZERO_PAGE |
238ec4ef | 59 | |
4f2e2903 | 60 | /* TODO: s390 cannot support io_remap_pfn_range... */ |
1da177e4 LT |
61 | #endif /* !__ASSEMBLY__ */ |
62 | ||
63 | /* | |
64 | * PMD_SHIFT determines the size of the area a second-level page | |
65 | * table can map | |
66 | * PGDIR_SHIFT determines what a third-level page table entry can map | |
67 | */ | |
f4815ac6 | 68 | #ifndef CONFIG_64BIT |
146e4b3c MS |
69 | # define PMD_SHIFT 20 |
70 | # define PUD_SHIFT 20 | |
71 | # define PGDIR_SHIFT 20 | |
f4815ac6 | 72 | #else /* CONFIG_64BIT */ |
146e4b3c | 73 | # define PMD_SHIFT 20 |
190a1d72 | 74 | # define PUD_SHIFT 31 |
5a216a20 | 75 | # define PGDIR_SHIFT 42 |
f4815ac6 | 76 | #endif /* CONFIG_64BIT */ |
1da177e4 LT |
77 | |
78 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
79 | #define PMD_MASK (~(PMD_SIZE-1)) | |
190a1d72 MS |
80 | #define PUD_SIZE (1UL << PUD_SHIFT) |
81 | #define PUD_MASK (~(PUD_SIZE-1)) | |
5a216a20 MS |
82 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
83 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
1da177e4 LT |
84 | |
85 | /* | |
86 | * entries per page directory level: the S390 is two-level, so | |
87 | * we don't really have any PMD directory physically. | |
88 | * for S390 segment-table entries are combined to one PGD | |
89 | * that leads to 1024 pte per pgd | |
90 | */ | |
146e4b3c | 91 | #define PTRS_PER_PTE 256 |
f4815ac6 | 92 | #ifndef CONFIG_64BIT |
146e4b3c | 93 | #define PTRS_PER_PMD 1 |
5a216a20 | 94 | #define PTRS_PER_PUD 1 |
f4815ac6 | 95 | #else /* CONFIG_64BIT */ |
146e4b3c | 96 | #define PTRS_PER_PMD 2048 |
5a216a20 | 97 | #define PTRS_PER_PUD 2048 |
f4815ac6 | 98 | #endif /* CONFIG_64BIT */ |
146e4b3c | 99 | #define PTRS_PER_PGD 2048 |
1da177e4 | 100 | |
d455a369 HD |
101 | #define FIRST_USER_ADDRESS 0 |
102 | ||
1da177e4 LT |
103 | #define pte_ERROR(e) \ |
104 | printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) | |
105 | #define pmd_ERROR(e) \ | |
106 | printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) | |
190a1d72 MS |
107 | #define pud_ERROR(e) \ |
108 | printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) | |
1da177e4 LT |
109 | #define pgd_ERROR(e) \ |
110 | printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) | |
111 | ||
112 | #ifndef __ASSEMBLY__ | |
113 | /* | |
c972cc60 HC |
114 | * The vmalloc and module area will always be on the topmost area of the kernel |
115 | * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules. | |
116 | * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where | |
117 | * modules will reside. That makes sure that inter module branches always | |
118 | * happen without trampolines and in addition the placement within a 2GB frame | |
119 | * is branch prediction unit friendly. | |
8b62bc96 | 120 | */ |
239a6425 | 121 | extern unsigned long VMALLOC_START; |
14045ebf MS |
122 | extern unsigned long VMALLOC_END; |
123 | extern struct page *vmemmap; | |
239a6425 | 124 | |
14045ebf | 125 | #define VMEM_MAX_PHYS ((unsigned long) vmemmap) |
5fd9c6e2 | 126 | |
c972cc60 HC |
127 | #ifdef CONFIG_64BIT |
128 | extern unsigned long MODULES_VADDR; | |
129 | extern unsigned long MODULES_END; | |
130 | #define MODULES_VADDR MODULES_VADDR | |
131 | #define MODULES_END MODULES_END | |
132 | #define MODULES_LEN (1UL << 31) | |
133 | #endif | |
134 | ||
1da177e4 LT |
135 | /* |
136 | * A 31 bit pagetable entry of S390 has following format: | |
137 | * | PFRA | | OS | | |
138 | * 0 0IP0 | |
139 | * 00000000001111111111222222222233 | |
140 | * 01234567890123456789012345678901 | |
141 | * | |
142 | * I Page-Invalid Bit: Page is not available for address-translation | |
143 | * P Page-Protection Bit: Store access not possible for page | |
144 | * | |
145 | * A 31 bit segmenttable entry of S390 has following format: | |
146 | * | P-table origin | |PTL | |
147 | * 0 IC | |
148 | * 00000000001111111111222222222233 | |
149 | * 01234567890123456789012345678901 | |
150 | * | |
151 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
152 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
153 | * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256) | |
154 | * | |
155 | * The 31 bit segmenttable origin of S390 has following format: | |
156 | * | |
157 | * |S-table origin | | STL | | |
158 | * X **GPS | |
159 | * 00000000001111111111222222222233 | |
160 | * 01234567890123456789012345678901 | |
161 | * | |
162 | * X Space-Switch event: | |
163 | * G Segment-Invalid Bit: * | |
164 | * P Private-Space Bit: Segment is not private (PoP 3-30) | |
165 | * S Storage-Alteration: | |
166 | * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048) | |
167 | * | |
168 | * A 64 bit pagetable entry of S390 has following format: | |
6a985c61 | 169 | * | PFRA |0IPC| OS | |
1da177e4 LT |
170 | * 0000000000111111111122222222223333333333444444444455555555556666 |
171 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
172 | * | |
173 | * I Page-Invalid Bit: Page is not available for address-translation | |
174 | * P Page-Protection Bit: Store access not possible for page | |
6a985c61 | 175 | * C Change-bit override: HW is not required to set change bit |
1da177e4 LT |
176 | * |
177 | * A 64 bit segmenttable entry of S390 has following format: | |
178 | * | P-table origin | TT | |
179 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
180 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
181 | * | |
182 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
183 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
184 | * P Page-Protection Bit: Store access not possible for page | |
185 | * TT Type 00 | |
186 | * | |
187 | * A 64 bit region table entry of S390 has following format: | |
188 | * | S-table origin | TF TTTL | |
189 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
190 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
191 | * | |
192 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
193 | * TT Type 01 | |
194 | * TF | |
190a1d72 | 195 | * TL Table length |
1da177e4 LT |
196 | * |
197 | * The 64 bit regiontable origin of S390 has following format: | |
198 | * | region table origon | DTTL | |
199 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
200 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
201 | * | |
202 | * X Space-Switch event: | |
203 | * G Segment-Invalid Bit: | |
204 | * P Private-Space Bit: | |
205 | * S Storage-Alteration: | |
206 | * R Real space | |
207 | * TL Table-Length: | |
208 | * | |
209 | * A storage key has the following format: | |
210 | * | ACC |F|R|C|0| | |
211 | * 0 3 4 5 6 7 | |
212 | * ACC: access key | |
213 | * F : fetch protection bit | |
214 | * R : referenced bit | |
215 | * C : changed bit | |
216 | */ | |
217 | ||
218 | /* Hardware bits in the page table entry */ | |
6a985c61 | 219 | #define _PAGE_CO 0x100 /* HW Change-bit override */ |
e5098611 | 220 | #define _PAGE_PROTECT 0x200 /* HW read-only bit */ |
83377484 | 221 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ |
e5098611 | 222 | #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ |
3610cce8 MS |
223 | |
224 | /* Software bits in the page table entry */ | |
e5098611 MS |
225 | #define _PAGE_PRESENT 0x001 /* SW pte present bit */ |
226 | #define _PAGE_TYPE 0x002 /* SW pte type bit */ | |
227 | #define _PAGE_YOUNG 0x004 /* SW pte young bit */ | |
228 | #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ | |
0944fe3f MS |
229 | #define _PAGE_READ 0x010 /* SW pte read bit */ |
230 | #define _PAGE_WRITE 0x020 /* SW pte write bit */ | |
231 | #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ | |
b31288fa | 232 | #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ |
a08cb629 | 233 | #define __HAVE_ARCH_PTE_SPECIAL |
1da177e4 | 234 | |
138c9021 | 235 | /* Set of bits not changed in pte_modify */ |
abf09bed | 236 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_CO | \ |
e5098611 | 237 | _PAGE_DIRTY | _PAGE_YOUNG) |
53492b1d | 238 | |
83377484 | 239 | /* |
e5098611 MS |
240 | * handle_pte_fault uses pte_present, pte_none and pte_file to find out the |
241 | * pte type WITHOUT holding the page table lock. The _PAGE_PRESENT bit | |
242 | * is used to distinguish present from not-present ptes. It is changed only | |
243 | * with the page table lock held. | |
83377484 | 244 | * |
e5098611 MS |
245 | * The following table gives the different possible bit combinations for |
246 | * the pte hardware and software bits in the last 12 bits of a pte: | |
83377484 | 247 | * |
0944fe3f MS |
248 | * 842100000000 |
249 | * 000084210000 | |
250 | * 000000008421 | |
251 | * .IR...wrdytp | |
252 | * empty .10...000000 | |
253 | * swap .10...xxxx10 | |
254 | * file .11...xxxxx0 | |
255 | * prot-none, clean, old .11...000001 | |
256 | * prot-none, clean, young .11...000101 | |
257 | * prot-none, dirty, old .10...001001 | |
258 | * prot-none, dirty, young .10...001101 | |
259 | * read-only, clean, old .11...010001 | |
260 | * read-only, clean, young .01...010101 | |
261 | * read-only, dirty, old .11...011001 | |
262 | * read-only, dirty, young .01...011101 | |
263 | * read-write, clean, old .11...110001 | |
264 | * read-write, clean, young .01...110101 | |
265 | * read-write, dirty, old .10...111001 | |
266 | * read-write, dirty, young .00...111101 | |
e5098611 MS |
267 | * |
268 | * pte_present is true for the bit pattern .xx...xxxxx1, (pte & 0x001) == 0x001 | |
269 | * pte_none is true for the bit pattern .10...xxxx00, (pte & 0x603) == 0x400 | |
270 | * pte_file is true for the bit pattern .11...xxxxx0, (pte & 0x601) == 0x600 | |
271 | * pte_swap is true for the bit pattern .10...xxxx10, (pte & 0x603) == 0x402 | |
83377484 MS |
272 | */ |
273 | ||
f4815ac6 | 274 | #ifndef CONFIG_64BIT |
1da177e4 | 275 | |
3610cce8 MS |
276 | /* Bits in the segment table address-space-control-element */ |
277 | #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */ | |
278 | #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */ | |
279 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
280 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
281 | #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */ | |
1da177e4 | 282 | |
3610cce8 | 283 | /* Bits in the segment table entry */ |
0944fe3f | 284 | #define _SEGMENT_ENTRY_BITS 0x7fffffffUL /* Valid segment table bits */ |
3610cce8 | 285 | #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */ |
e5098611 MS |
286 | #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */ |
287 | #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ | |
3610cce8 MS |
288 | #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */ |
289 | #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */ | |
152125b7 MS |
290 | |
291 | #define _SEGMENT_ENTRY_DIRTY 0 /* No sw dirty bit for 31-bit */ | |
292 | #define _SEGMENT_ENTRY_YOUNG 0 /* No sw young bit for 31-bit */ | |
293 | #define _SEGMENT_ENTRY_READ 0 /* No sw read bit for 31-bit */ | |
294 | #define _SEGMENT_ENTRY_WRITE 0 /* No sw write bit for 31-bit */ | |
295 | #define _SEGMENT_ENTRY_LARGE 0 /* No large pages for 31-bit */ | |
296 | #define _SEGMENT_ENTRY_BITS_LARGE 0 | |
297 | #define _SEGMENT_ENTRY_ORIGIN_LARGE 0 | |
1da177e4 | 298 | |
3610cce8 | 299 | #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL) |
e5098611 | 300 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) |
1da177e4 | 301 | |
0944fe3f MS |
302 | /* |
303 | * Segment table entry encoding (I = invalid, R = read-only bit): | |
304 | * ..R...I..... | |
305 | * prot-none ..1...1..... | |
306 | * read-only ..1...0..... | |
307 | * read-write ..0...0..... | |
308 | * empty ..0...1..... | |
309 | */ | |
310 | ||
6c61cfe9 | 311 | /* Page status table bits for virtualization */ |
0d0dafc1 MS |
312 | #define PGSTE_ACC_BITS 0xf0000000UL |
313 | #define PGSTE_FP_BIT 0x08000000UL | |
314 | #define PGSTE_PCL_BIT 0x00800000UL | |
315 | #define PGSTE_HR_BIT 0x00400000UL | |
316 | #define PGSTE_HC_BIT 0x00200000UL | |
317 | #define PGSTE_GR_BIT 0x00040000UL | |
318 | #define PGSTE_GC_BIT 0x00020000UL | |
0a61b222 MS |
319 | #define PGSTE_UC_BIT 0x00008000UL /* user dirty (migration) */ |
320 | #define PGSTE_IN_BIT 0x00004000UL /* IPTE notify bit */ | |
6c61cfe9 | 321 | |
f4815ac6 | 322 | #else /* CONFIG_64BIT */ |
1da177e4 | 323 | |
3610cce8 MS |
324 | /* Bits in the segment/region table address-space-control-element */ |
325 | #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ | |
326 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
327 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
328 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
329 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
330 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
331 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
332 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
333 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
334 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
335 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
336 | ||
337 | /* Bits in the region table entry */ | |
338 | #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ | |
e5098611 MS |
339 | #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ |
340 | #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ | |
3610cce8 MS |
341 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ |
342 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
343 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
344 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
345 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
346 | ||
347 | #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) | |
e5098611 | 348 | #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) |
3610cce8 | 349 | #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) |
e5098611 | 350 | #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) |
3610cce8 | 351 | #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) |
e5098611 | 352 | #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) |
3610cce8 | 353 | |
18da2369 | 354 | #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */ |
1819ed1f HC |
355 | #define _REGION3_ENTRY_RO 0x200 /* page protection bit */ |
356 | #define _REGION3_ENTRY_CO 0x100 /* change-recording override */ | |
18da2369 | 357 | |
1da177e4 | 358 | /* Bits in the segment table entry */ |
0944fe3f | 359 | #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL |
152125b7 | 360 | #define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff0ff33UL |
ea81531d | 361 | #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ |
3610cce8 | 362 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ |
e5098611 MS |
363 | #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */ |
364 | #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ | |
1da177e4 | 365 | |
3610cce8 | 366 | #define _SEGMENT_ENTRY (0) |
e5098611 | 367 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) |
3610cce8 | 368 | |
152125b7 MS |
369 | #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ |
370 | #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ | |
371 | #define _SEGMENT_ENTRY_SPLIT 0x0800 /* THP splitting bit */ | |
372 | #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ | |
373 | #define _SEGMENT_ENTRY_CO 0x0100 /* change-recording override */ | |
374 | #define _SEGMENT_ENTRY_READ 0x0002 /* SW segment read bit */ | |
375 | #define _SEGMENT_ENTRY_WRITE 0x0001 /* SW segment write bit */ | |
0944fe3f MS |
376 | |
377 | /* | |
378 | * Segment table entry encoding (R = read-only, I = invalid, y = young bit): | |
152125b7 MS |
379 | * dy..R...I...wr |
380 | * prot-none, clean, old 00..1...1...00 | |
381 | * prot-none, clean, young 01..1...1...00 | |
382 | * prot-none, dirty, old 10..1...1...00 | |
383 | * prot-none, dirty, young 11..1...1...00 | |
384 | * read-only, clean, old 00..1...1...01 | |
385 | * read-only, clean, young 01..1...0...01 | |
386 | * read-only, dirty, old 10..1...1...01 | |
387 | * read-only, dirty, young 11..1...0...01 | |
388 | * read-write, clean, old 00..1...1...11 | |
389 | * read-write, clean, young 01..1...0...11 | |
390 | * read-write, dirty, old 10..0...1...11 | |
391 | * read-write, dirty, young 11..0...0...11 | |
0944fe3f MS |
392 | * The segment table origin is used to distinguish empty (origin==0) from |
393 | * read-write, old segment table entries (origin!=0) | |
394 | */ | |
e5098611 | 395 | |
152125b7 | 396 | #define _SEGMENT_ENTRY_SPLIT_BIT 11 /* THP splitting bit number */ |
1ae1c1d0 | 397 | |
6c61cfe9 | 398 | /* Page status table bits for virtualization */ |
0d0dafc1 MS |
399 | #define PGSTE_ACC_BITS 0xf000000000000000UL |
400 | #define PGSTE_FP_BIT 0x0800000000000000UL | |
401 | #define PGSTE_PCL_BIT 0x0080000000000000UL | |
402 | #define PGSTE_HR_BIT 0x0040000000000000UL | |
403 | #define PGSTE_HC_BIT 0x0020000000000000UL | |
404 | #define PGSTE_GR_BIT 0x0004000000000000UL | |
405 | #define PGSTE_GC_BIT 0x0002000000000000UL | |
0a61b222 MS |
406 | #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ |
407 | #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ | |
6c61cfe9 | 408 | |
f4815ac6 | 409 | #endif /* CONFIG_64BIT */ |
1da177e4 | 410 | |
b31288fa KW |
411 | /* Guest Page State used for virtualization */ |
412 | #define _PGSTE_GPS_ZERO 0x0000000080000000UL | |
413 | #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL | |
414 | #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL | |
415 | #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL | |
416 | ||
1da177e4 | 417 | /* |
3610cce8 MS |
418 | * A user page table pointer has the space-switch-event bit, the |
419 | * private-space-control bit and the storage-alteration-event-control | |
420 | * bit set. A kernel page table pointer doesn't need them. | |
1da177e4 | 421 | */ |
3610cce8 MS |
422 | #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ |
423 | _ASCE_ALT_EVENT) | |
1da177e4 | 424 | |
1da177e4 | 425 | /* |
9282ed92 | 426 | * Page protection definitions. |
1da177e4 | 427 | */ |
e5098611 | 428 | #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID) |
0944fe3f MS |
429 | #define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_READ | \ |
430 | _PAGE_INVALID | _PAGE_PROTECT) | |
431 | #define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
432 | _PAGE_INVALID | _PAGE_PROTECT) | |
433 | ||
434 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
435 | _PAGE_YOUNG | _PAGE_DIRTY) | |
436 | #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
437 | _PAGE_YOUNG | _PAGE_DIRTY) | |
438 | #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ | |
439 | _PAGE_PROTECT) | |
1da177e4 LT |
440 | |
441 | /* | |
043d0708 MS |
442 | * On s390 the page table entry has an invalid bit and a read-only bit. |
443 | * Read permission implies execute permission and write permission | |
444 | * implies read permission. | |
1da177e4 LT |
445 | */ |
446 | /*xwr*/ | |
9282ed92 | 447 | #define __P000 PAGE_NONE |
e5098611 MS |
448 | #define __P001 PAGE_READ |
449 | #define __P010 PAGE_READ | |
450 | #define __P011 PAGE_READ | |
451 | #define __P100 PAGE_READ | |
452 | #define __P101 PAGE_READ | |
453 | #define __P110 PAGE_READ | |
454 | #define __P111 PAGE_READ | |
9282ed92 GS |
455 | |
456 | #define __S000 PAGE_NONE | |
e5098611 MS |
457 | #define __S001 PAGE_READ |
458 | #define __S010 PAGE_WRITE | |
459 | #define __S011 PAGE_WRITE | |
460 | #define __S100 PAGE_READ | |
461 | #define __S101 PAGE_READ | |
462 | #define __S110 PAGE_WRITE | |
463 | #define __S111 PAGE_WRITE | |
1da177e4 | 464 | |
106c992a GS |
465 | /* |
466 | * Segment entry (large page) protection definitions. | |
467 | */ | |
e5098611 MS |
468 | #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ |
469 | _SEGMENT_ENTRY_PROTECT) | |
152125b7 MS |
470 | #define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_PROTECT | \ |
471 | _SEGMENT_ENTRY_READ) | |
472 | #define SEGMENT_WRITE __pgprot(_SEGMENT_ENTRY_READ | \ | |
473 | _SEGMENT_ENTRY_WRITE) | |
106c992a | 474 | |
b2fa47e6 MS |
475 | static inline int mm_has_pgste(struct mm_struct *mm) |
476 | { | |
477 | #ifdef CONFIG_PGSTE | |
478 | if (unlikely(mm->context.has_pgste)) | |
479 | return 1; | |
480 | #endif | |
481 | return 0; | |
482 | } | |
65eef335 DD |
483 | |
484 | static inline int mm_use_skey(struct mm_struct *mm) | |
485 | { | |
486 | #ifdef CONFIG_PGSTE | |
487 | if (mm->context.use_skey) | |
488 | return 1; | |
489 | #endif | |
490 | return 0; | |
491 | } | |
492 | ||
1da177e4 LT |
493 | /* |
494 | * pgd/pmd/pte query functions | |
495 | */ | |
f4815ac6 | 496 | #ifndef CONFIG_64BIT |
1da177e4 | 497 | |
4448aaf0 AB |
498 | static inline int pgd_present(pgd_t pgd) { return 1; } |
499 | static inline int pgd_none(pgd_t pgd) { return 0; } | |
500 | static inline int pgd_bad(pgd_t pgd) { return 0; } | |
1da177e4 | 501 | |
190a1d72 MS |
502 | static inline int pud_present(pud_t pud) { return 1; } |
503 | static inline int pud_none(pud_t pud) { return 0; } | |
18da2369 | 504 | static inline int pud_large(pud_t pud) { return 0; } |
190a1d72 MS |
505 | static inline int pud_bad(pud_t pud) { return 0; } |
506 | ||
f4815ac6 | 507 | #else /* CONFIG_64BIT */ |
1da177e4 | 508 | |
5a216a20 MS |
509 | static inline int pgd_present(pgd_t pgd) |
510 | { | |
6252d702 MS |
511 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
512 | return 1; | |
5a216a20 MS |
513 | return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; |
514 | } | |
515 | ||
516 | static inline int pgd_none(pgd_t pgd) | |
517 | { | |
6252d702 MS |
518 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
519 | return 0; | |
e5098611 | 520 | return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; |
5a216a20 MS |
521 | } |
522 | ||
523 | static inline int pgd_bad(pgd_t pgd) | |
524 | { | |
6252d702 MS |
525 | /* |
526 | * With dynamic page table levels the pgd can be a region table | |
527 | * entry or a segment table entry. Check for the bit that are | |
528 | * invalid for either table entry. | |
529 | */ | |
5a216a20 | 530 | unsigned long mask = |
e5098611 | 531 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & |
5a216a20 MS |
532 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
533 | return (pgd_val(pgd) & mask) != 0; | |
534 | } | |
190a1d72 MS |
535 | |
536 | static inline int pud_present(pud_t pud) | |
1da177e4 | 537 | { |
6252d702 MS |
538 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
539 | return 1; | |
0d017923 | 540 | return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
541 | } |
542 | ||
190a1d72 | 543 | static inline int pud_none(pud_t pud) |
1da177e4 | 544 | { |
6252d702 MS |
545 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
546 | return 0; | |
e5098611 | 547 | return (pud_val(pud) & _REGION_ENTRY_INVALID) != 0UL; |
1da177e4 LT |
548 | } |
549 | ||
18da2369 HC |
550 | static inline int pud_large(pud_t pud) |
551 | { | |
552 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) | |
553 | return 0; | |
554 | return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); | |
555 | } | |
556 | ||
190a1d72 | 557 | static inline int pud_bad(pud_t pud) |
1da177e4 | 558 | { |
6252d702 MS |
559 | /* |
560 | * With dynamic page table levels the pud can be a region table | |
561 | * entry or a segment table entry. Check for the bit that are | |
562 | * invalid for either table entry. | |
563 | */ | |
5a216a20 | 564 | unsigned long mask = |
e5098611 | 565 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & |
5a216a20 MS |
566 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
567 | return (pud_val(pud) & mask) != 0; | |
1da177e4 LT |
568 | } |
569 | ||
f4815ac6 | 570 | #endif /* CONFIG_64BIT */ |
3610cce8 | 571 | |
4448aaf0 | 572 | static inline int pmd_present(pmd_t pmd) |
1da177e4 | 573 | { |
e5098611 | 574 | return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
575 | } |
576 | ||
4448aaf0 | 577 | static inline int pmd_none(pmd_t pmd) |
1da177e4 | 578 | { |
e5098611 | 579 | return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
580 | } |
581 | ||
378b1e7a HC |
582 | static inline int pmd_large(pmd_t pmd) |
583 | { | |
e5098611 | 584 | return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; |
378b1e7a HC |
585 | } |
586 | ||
152125b7 | 587 | static inline int pmd_pfn(pmd_t pmd) |
0944fe3f | 588 | { |
152125b7 MS |
589 | unsigned long origin_mask; |
590 | ||
591 | origin_mask = _SEGMENT_ENTRY_ORIGIN; | |
592 | if (pmd_large(pmd)) | |
593 | origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; | |
594 | return (pmd_val(pmd) & origin_mask) >> PAGE_SHIFT; | |
0944fe3f MS |
595 | } |
596 | ||
4448aaf0 | 597 | static inline int pmd_bad(pmd_t pmd) |
1da177e4 | 598 | { |
0944fe3f MS |
599 | if (pmd_large(pmd)) |
600 | return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0; | |
0944fe3f | 601 | return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; |
1da177e4 LT |
602 | } |
603 | ||
75077afb GS |
604 | #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH |
605 | extern void pmdp_splitting_flush(struct vm_area_struct *vma, | |
606 | unsigned long addr, pmd_t *pmdp); | |
607 | ||
1ae1c1d0 GS |
608 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
609 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, | |
610 | unsigned long address, pmd_t *pmdp, | |
611 | pmd_t entry, int dirty); | |
612 | ||
613 | #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH | |
614 | extern int pmdp_clear_flush_young(struct vm_area_struct *vma, | |
615 | unsigned long address, pmd_t *pmdp); | |
616 | ||
617 | #define __HAVE_ARCH_PMD_WRITE | |
618 | static inline int pmd_write(pmd_t pmd) | |
619 | { | |
152125b7 MS |
620 | return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; |
621 | } | |
622 | ||
623 | static inline int pmd_dirty(pmd_t pmd) | |
624 | { | |
625 | int dirty = 1; | |
626 | if (pmd_large(pmd)) | |
627 | dirty = (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; | |
628 | return dirty; | |
1ae1c1d0 GS |
629 | } |
630 | ||
631 | static inline int pmd_young(pmd_t pmd) | |
632 | { | |
152125b7 MS |
633 | int young = 1; |
634 | if (pmd_large(pmd)) | |
0944fe3f | 635 | young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; |
0944fe3f | 636 | return young; |
1ae1c1d0 GS |
637 | } |
638 | ||
e5098611 | 639 | static inline int pte_present(pte_t pte) |
1da177e4 | 640 | { |
e5098611 MS |
641 | /* Bit pattern: (pte & 0x001) == 0x001 */ |
642 | return (pte_val(pte) & _PAGE_PRESENT) != 0; | |
1da177e4 LT |
643 | } |
644 | ||
e5098611 | 645 | static inline int pte_none(pte_t pte) |
1da177e4 | 646 | { |
e5098611 MS |
647 | /* Bit pattern: pte == 0x400 */ |
648 | return pte_val(pte) == _PAGE_INVALID; | |
1da177e4 LT |
649 | } |
650 | ||
b31288fa KW |
651 | static inline int pte_swap(pte_t pte) |
652 | { | |
653 | /* Bit pattern: (pte & 0x603) == 0x402 */ | |
654 | return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT | | |
655 | _PAGE_TYPE | _PAGE_PRESENT)) | |
656 | == (_PAGE_INVALID | _PAGE_TYPE); | |
657 | } | |
658 | ||
4448aaf0 | 659 | static inline int pte_file(pte_t pte) |
1da177e4 | 660 | { |
e5098611 MS |
661 | /* Bit pattern: (pte & 0x601) == 0x600 */ |
662 | return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT | _PAGE_PRESENT)) | |
663 | == (_PAGE_INVALID | _PAGE_PROTECT); | |
1da177e4 LT |
664 | } |
665 | ||
7e675137 NP |
666 | static inline int pte_special(pte_t pte) |
667 | { | |
a08cb629 | 668 | return (pte_val(pte) & _PAGE_SPECIAL); |
7e675137 NP |
669 | } |
670 | ||
ba8a9229 | 671 | #define __HAVE_ARCH_PTE_SAME |
b2fa47e6 MS |
672 | static inline int pte_same(pte_t a, pte_t b) |
673 | { | |
674 | return pte_val(a) == pte_val(b); | |
675 | } | |
1da177e4 | 676 | |
b2fa47e6 | 677 | static inline pgste_t pgste_get_lock(pte_t *ptep) |
5b7baf05 | 678 | { |
b2fa47e6 | 679 | unsigned long new = 0; |
5b7baf05 | 680 | #ifdef CONFIG_PGSTE |
b2fa47e6 MS |
681 | unsigned long old; |
682 | ||
5b7baf05 | 683 | preempt_disable(); |
b2fa47e6 MS |
684 | asm( |
685 | " lg %0,%2\n" | |
686 | "0: lgr %1,%0\n" | |
0d0dafc1 MS |
687 | " nihh %0,0xff7f\n" /* clear PCL bit in old */ |
688 | " oihh %1,0x0080\n" /* set PCL bit in new */ | |
b2fa47e6 MS |
689 | " csg %0,%1,%2\n" |
690 | " jl 0b\n" | |
691 | : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) | |
a8f6e7f7 | 692 | : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory"); |
5b7baf05 | 693 | #endif |
b2fa47e6 | 694 | return __pgste(new); |
5b7baf05 CB |
695 | } |
696 | ||
b2fa47e6 | 697 | static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste) |
5b7baf05 CB |
698 | { |
699 | #ifdef CONFIG_PGSTE | |
b2fa47e6 | 700 | asm( |
0d0dafc1 | 701 | " nihh %1,0xff7f\n" /* clear PCL bit */ |
b2fa47e6 MS |
702 | " stg %1,%0\n" |
703 | : "=Q" (ptep[PTRS_PER_PTE]) | |
a8f6e7f7 CB |
704 | : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) |
705 | : "cc", "memory"); | |
5b7baf05 CB |
706 | preempt_enable(); |
707 | #endif | |
708 | } | |
709 | ||
d56c893d MS |
710 | static inline pgste_t pgste_get(pte_t *ptep) |
711 | { | |
712 | unsigned long pgste = 0; | |
713 | #ifdef CONFIG_PGSTE | |
714 | pgste = *(unsigned long *)(ptep + PTRS_PER_PTE); | |
715 | #endif | |
716 | return __pgste(pgste); | |
717 | } | |
718 | ||
3a82603b CB |
719 | static inline void pgste_set(pte_t *ptep, pgste_t pgste) |
720 | { | |
721 | #ifdef CONFIG_PGSTE | |
722 | *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste; | |
723 | #endif | |
724 | } | |
725 | ||
65eef335 DD |
726 | static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste, |
727 | struct mm_struct *mm) | |
5b7baf05 CB |
728 | { |
729 | #ifdef CONFIG_PGSTE | |
0944fe3f | 730 | unsigned long address, bits, skey; |
b2fa47e6 | 731 | |
65eef335 | 732 | if (!mm_use_skey(mm) || pte_val(*ptep) & _PAGE_INVALID) |
09b53883 | 733 | return pgste; |
a43a9d93 | 734 | address = pte_val(*ptep) & PAGE_MASK; |
0944fe3f | 735 | skey = (unsigned long) page_get_storage_key(address); |
b2fa47e6 | 736 | bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED); |
b2fa47e6 | 737 | /* Transfer page changed & referenced bit to guest bits in pgste */ |
0d0dafc1 | 738 | pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */ |
b2fa47e6 | 739 | /* Copy page access key and fetch protection bit to pgste */ |
0944fe3f MS |
740 | pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT); |
741 | pgste_val(pgste) |= (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56; | |
b2fa47e6 MS |
742 | #endif |
743 | return pgste; | |
744 | ||
745 | } | |
746 | ||
65eef335 DD |
747 | static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry, |
748 | struct mm_struct *mm) | |
b2fa47e6 MS |
749 | { |
750 | #ifdef CONFIG_PGSTE | |
a43a9d93 | 751 | unsigned long address; |
338679f7 | 752 | unsigned long nkey; |
b2fa47e6 | 753 | |
65eef335 | 754 | if (!mm_use_skey(mm) || pte_val(entry) & _PAGE_INVALID) |
09b53883 | 755 | return; |
338679f7 | 756 | VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID)); |
09b53883 | 757 | address = pte_val(entry) & PAGE_MASK; |
338679f7 CB |
758 | /* |
759 | * Set page access key and fetch protection bit from pgste. | |
760 | * The guest C/R information is still in the PGSTE, set real | |
761 | * key C/R to 0. | |
762 | */ | |
fe489bf4 | 763 | nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56; |
0a61b222 | 764 | nkey |= (pgste_val(pgste) & (PGSTE_GR_BIT | PGSTE_GC_BIT)) >> 48; |
338679f7 | 765 | page_set_storage_key(address, nkey, 0); |
5b7baf05 CB |
766 | #endif |
767 | } | |
768 | ||
0a61b222 | 769 | static inline pgste_t pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry) |
abf09bed | 770 | { |
0a61b222 MS |
771 | if ((pte_val(entry) & _PAGE_PRESENT) && |
772 | (pte_val(entry) & _PAGE_WRITE) && | |
773 | !(pte_val(entry) & _PAGE_INVALID)) { | |
774 | if (!MACHINE_HAS_ESOP) { | |
775 | /* | |
776 | * Without enhanced suppression-on-protection force | |
777 | * the dirty bit on for all writable ptes. | |
778 | */ | |
779 | pte_val(entry) |= _PAGE_DIRTY; | |
780 | pte_val(entry) &= ~_PAGE_PROTECT; | |
781 | } | |
782 | if (!(pte_val(entry) & _PAGE_PROTECT)) | |
783 | /* This pte allows write access, set user-dirty */ | |
784 | pgste_val(pgste) |= PGSTE_UC_BIT; | |
abf09bed MS |
785 | } |
786 | *ptep = entry; | |
0a61b222 | 787 | return pgste; |
abf09bed MS |
788 | } |
789 | ||
e5992f2e MS |
790 | /** |
791 | * struct gmap_struct - guest address space | |
792 | * @mm: pointer to the parent mm_struct | |
793 | * @table: pointer to the page directory | |
480e5926 | 794 | * @asce: address space control element for gmap page table |
e5992f2e | 795 | * @crst_list: list of all crst tables used in the guest address space |
24eb3a82 | 796 | * @pfault_enabled: defines if pfaults are applicable for the guest |
e5992f2e MS |
797 | */ |
798 | struct gmap { | |
799 | struct list_head list; | |
800 | struct mm_struct *mm; | |
801 | unsigned long *table; | |
480e5926 | 802 | unsigned long asce; |
2c70fe44 | 803 | void *private; |
e5992f2e | 804 | struct list_head crst_list; |
24eb3a82 | 805 | bool pfault_enabled; |
e5992f2e MS |
806 | }; |
807 | ||
808 | /** | |
809 | * struct gmap_rmap - reverse mapping for segment table entries | |
d3383632 | 810 | * @gmap: pointer to the gmap_struct |
e5992f2e | 811 | * @entry: pointer to a segment table entry |
d3383632 | 812 | * @vmaddr: virtual address in the guest address space |
e5992f2e MS |
813 | */ |
814 | struct gmap_rmap { | |
815 | struct list_head list; | |
d3383632 | 816 | struct gmap *gmap; |
e5992f2e | 817 | unsigned long *entry; |
d3383632 | 818 | unsigned long vmaddr; |
e5992f2e MS |
819 | }; |
820 | ||
821 | /** | |
822 | * struct gmap_pgtable - gmap information attached to a page table | |
823 | * @vmaddr: address of the 1MB segment in the process virtual memory | |
d3383632 | 824 | * @mapper: list of segment table entries mapping a page table |
e5992f2e MS |
825 | */ |
826 | struct gmap_pgtable { | |
827 | unsigned long vmaddr; | |
828 | struct list_head mapper; | |
829 | }; | |
830 | ||
d3383632 MS |
831 | /** |
832 | * struct gmap_notifier - notify function block for page invalidation | |
833 | * @notifier_call: address of callback function | |
834 | */ | |
835 | struct gmap_notifier { | |
836 | struct list_head list; | |
837 | void (*notifier_call)(struct gmap *gmap, unsigned long address); | |
838 | }; | |
839 | ||
e5992f2e MS |
840 | struct gmap *gmap_alloc(struct mm_struct *mm); |
841 | void gmap_free(struct gmap *gmap); | |
842 | void gmap_enable(struct gmap *gmap); | |
843 | void gmap_disable(struct gmap *gmap); | |
844 | int gmap_map_segment(struct gmap *gmap, unsigned long from, | |
d3383632 | 845 | unsigned long to, unsigned long len); |
e5992f2e | 846 | int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len); |
c5034945 HC |
847 | unsigned long __gmap_translate(unsigned long address, struct gmap *); |
848 | unsigned long gmap_translate(unsigned long address, struct gmap *); | |
499069e1 | 849 | unsigned long __gmap_fault(unsigned long address, struct gmap *); |
e5992f2e | 850 | unsigned long gmap_fault(unsigned long address, struct gmap *); |
388186bc | 851 | void gmap_discard(unsigned long from, unsigned long to, struct gmap *); |
b31288fa | 852 | void __gmap_zap(unsigned long address, struct gmap *); |
a0bf4f14 DD |
853 | bool gmap_test_and_clear_dirty(unsigned long address, struct gmap *); |
854 | ||
e5992f2e | 855 | |
d3383632 MS |
856 | void gmap_register_ipte_notifier(struct gmap_notifier *); |
857 | void gmap_unregister_ipte_notifier(struct gmap_notifier *); | |
858 | int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len); | |
9da4e380 | 859 | void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *); |
d3383632 MS |
860 | |
861 | static inline pgste_t pgste_ipte_notify(struct mm_struct *mm, | |
55dbbdd9 | 862 | unsigned long addr, |
d3383632 MS |
863 | pte_t *ptep, pgste_t pgste) |
864 | { | |
865 | #ifdef CONFIG_PGSTE | |
0d0dafc1 MS |
866 | if (pgste_val(pgste) & PGSTE_IN_BIT) { |
867 | pgste_val(pgste) &= ~PGSTE_IN_BIT; | |
9da4e380 | 868 | gmap_do_ipte_notify(mm, addr, ptep); |
d3383632 MS |
869 | } |
870 | #endif | |
871 | return pgste; | |
872 | } | |
873 | ||
b2fa47e6 MS |
874 | /* |
875 | * Certain architectures need to do special things when PTEs | |
876 | * within a page table are directly modified. Thus, the following | |
877 | * hook is made available. | |
878 | */ | |
879 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
880 | pte_t *ptep, pte_t entry) | |
881 | { | |
882 | pgste_t pgste; | |
883 | ||
884 | if (mm_has_pgste(mm)) { | |
885 | pgste = pgste_get_lock(ptep); | |
b31288fa | 886 | pgste_val(pgste) &= ~_PGSTE_GPS_ZERO; |
65eef335 | 887 | pgste_set_key(ptep, pgste, entry, mm); |
0a61b222 | 888 | pgste = pgste_set_pte(ptep, pgste, entry); |
b2fa47e6 | 889 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
890 | } else { |
891 | if (!(pte_val(entry) & _PAGE_INVALID) && MACHINE_HAS_EDAT1) | |
892 | pte_val(entry) |= _PAGE_CO; | |
b2fa47e6 | 893 | *ptep = entry; |
abf09bed | 894 | } |
b2fa47e6 MS |
895 | } |
896 | ||
1da177e4 LT |
897 | /* |
898 | * query functions pte_write/pte_dirty/pte_young only work if | |
899 | * pte_present() is true. Undefined behaviour if not.. | |
900 | */ | |
4448aaf0 | 901 | static inline int pte_write(pte_t pte) |
1da177e4 | 902 | { |
e5098611 | 903 | return (pte_val(pte) & _PAGE_WRITE) != 0; |
1da177e4 LT |
904 | } |
905 | ||
4448aaf0 | 906 | static inline int pte_dirty(pte_t pte) |
1da177e4 | 907 | { |
e5098611 | 908 | return (pte_val(pte) & _PAGE_DIRTY) != 0; |
1da177e4 LT |
909 | } |
910 | ||
4448aaf0 | 911 | static inline int pte_young(pte_t pte) |
1da177e4 | 912 | { |
0944fe3f | 913 | return (pte_val(pte) & _PAGE_YOUNG) != 0; |
1da177e4 LT |
914 | } |
915 | ||
b31288fa KW |
916 | #define __HAVE_ARCH_PTE_UNUSED |
917 | static inline int pte_unused(pte_t pte) | |
918 | { | |
919 | return pte_val(pte) & _PAGE_UNUSED; | |
920 | } | |
921 | ||
1da177e4 LT |
922 | /* |
923 | * pgd/pmd/pte modification functions | |
924 | */ | |
925 | ||
b2fa47e6 | 926 | static inline void pgd_clear(pgd_t *pgd) |
5a216a20 | 927 | { |
f4815ac6 | 928 | #ifdef CONFIG_64BIT |
6252d702 MS |
929 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) |
930 | pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; | |
b2fa47e6 | 931 | #endif |
5a216a20 MS |
932 | } |
933 | ||
b2fa47e6 | 934 | static inline void pud_clear(pud_t *pud) |
1da177e4 | 935 | { |
f4815ac6 | 936 | #ifdef CONFIG_64BIT |
6252d702 MS |
937 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) |
938 | pud_val(*pud) = _REGION3_ENTRY_EMPTY; | |
b2fa47e6 | 939 | #endif |
1da177e4 LT |
940 | } |
941 | ||
b2fa47e6 | 942 | static inline void pmd_clear(pmd_t *pmdp) |
1da177e4 | 943 | { |
e5098611 | 944 | pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
945 | } |
946 | ||
4448aaf0 | 947 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
1da177e4 | 948 | { |
e5098611 | 949 | pte_val(*ptep) = _PAGE_INVALID; |
1da177e4 LT |
950 | } |
951 | ||
952 | /* | |
953 | * The following pte modification functions only work if | |
954 | * pte_present() is true. Undefined behaviour if not.. | |
955 | */ | |
4448aaf0 | 956 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
1da177e4 | 957 | { |
138c9021 | 958 | pte_val(pte) &= _PAGE_CHG_MASK; |
1da177e4 | 959 | pte_val(pte) |= pgprot_val(newprot); |
0944fe3f MS |
960 | /* |
961 | * newprot for PAGE_NONE, PAGE_READ and PAGE_WRITE has the | |
962 | * invalid bit set, clear it again for readable, young pages | |
963 | */ | |
964 | if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) | |
965 | pte_val(pte) &= ~_PAGE_INVALID; | |
966 | /* | |
967 | * newprot for PAGE_READ and PAGE_WRITE has the page protection | |
968 | * bit set, clear it again for writable, dirty pages | |
969 | */ | |
e5098611 MS |
970 | if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) |
971 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
972 | return pte; |
973 | } | |
974 | ||
4448aaf0 | 975 | static inline pte_t pte_wrprotect(pte_t pte) |
1da177e4 | 976 | { |
e5098611 MS |
977 | pte_val(pte) &= ~_PAGE_WRITE; |
978 | pte_val(pte) |= _PAGE_PROTECT; | |
1da177e4 LT |
979 | return pte; |
980 | } | |
981 | ||
4448aaf0 | 982 | static inline pte_t pte_mkwrite(pte_t pte) |
1da177e4 | 983 | { |
e5098611 MS |
984 | pte_val(pte) |= _PAGE_WRITE; |
985 | if (pte_val(pte) & _PAGE_DIRTY) | |
986 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
987 | return pte; |
988 | } | |
989 | ||
4448aaf0 | 990 | static inline pte_t pte_mkclean(pte_t pte) |
1da177e4 | 991 | { |
e5098611 MS |
992 | pte_val(pte) &= ~_PAGE_DIRTY; |
993 | pte_val(pte) |= _PAGE_PROTECT; | |
1da177e4 LT |
994 | return pte; |
995 | } | |
996 | ||
4448aaf0 | 997 | static inline pte_t pte_mkdirty(pte_t pte) |
1da177e4 | 998 | { |
e5098611 MS |
999 | pte_val(pte) |= _PAGE_DIRTY; |
1000 | if (pte_val(pte) & _PAGE_WRITE) | |
1001 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
1002 | return pte; |
1003 | } | |
1004 | ||
4448aaf0 | 1005 | static inline pte_t pte_mkold(pte_t pte) |
1da177e4 | 1006 | { |
e5098611 | 1007 | pte_val(pte) &= ~_PAGE_YOUNG; |
0944fe3f | 1008 | pte_val(pte) |= _PAGE_INVALID; |
1da177e4 LT |
1009 | return pte; |
1010 | } | |
1011 | ||
4448aaf0 | 1012 | static inline pte_t pte_mkyoung(pte_t pte) |
1da177e4 | 1013 | { |
0944fe3f MS |
1014 | pte_val(pte) |= _PAGE_YOUNG; |
1015 | if (pte_val(pte) & _PAGE_READ) | |
1016 | pte_val(pte) &= ~_PAGE_INVALID; | |
1da177e4 LT |
1017 | return pte; |
1018 | } | |
1019 | ||
7e675137 NP |
1020 | static inline pte_t pte_mkspecial(pte_t pte) |
1021 | { | |
a08cb629 | 1022 | pte_val(pte) |= _PAGE_SPECIAL; |
7e675137 NP |
1023 | return pte; |
1024 | } | |
1025 | ||
84afdcee HC |
1026 | #ifdef CONFIG_HUGETLB_PAGE |
1027 | static inline pte_t pte_mkhuge(pte_t pte) | |
1028 | { | |
e5098611 | 1029 | pte_val(pte) |= _PAGE_LARGE; |
84afdcee HC |
1030 | return pte; |
1031 | } | |
1032 | #endif | |
1033 | ||
9282ed92 | 1034 | static inline void __ptep_ipte(unsigned long address, pte_t *ptep) |
1da177e4 | 1035 | { |
53e857f3 MS |
1036 | unsigned long pto = (unsigned long) ptep; |
1037 | ||
f4815ac6 | 1038 | #ifndef CONFIG_64BIT |
53e857f3 MS |
1039 | /* pto in ESA mode must point to the start of the segment table */ |
1040 | pto &= 0x7ffffc00; | |
9282ed92 | 1041 | #endif |
53e857f3 MS |
1042 | /* Invalidation + global TLB flush for the pte */ |
1043 | asm volatile( | |
1044 | " ipte %2,%3" | |
1045 | : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address)); | |
1046 | } | |
1047 | ||
1b948d6c MS |
1048 | static inline void __ptep_ipte_local(unsigned long address, pte_t *ptep) |
1049 | { | |
1050 | unsigned long pto = (unsigned long) ptep; | |
1051 | ||
1052 | #ifndef CONFIG_64BIT | |
1053 | /* pto in ESA mode must point to the start of the segment table */ | |
1054 | pto &= 0x7ffffc00; | |
1055 | #endif | |
1056 | /* Invalidation + local TLB flush for the pte */ | |
1057 | asm volatile( | |
1058 | " .insn rrf,0xb2210000,%2,%3,0,1" | |
1059 | : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address)); | |
1060 | } | |
1061 | ||
53e857f3 MS |
1062 | static inline void ptep_flush_direct(struct mm_struct *mm, |
1063 | unsigned long address, pte_t *ptep) | |
1064 | { | |
1b948d6c MS |
1065 | int active, count; |
1066 | ||
53e857f3 MS |
1067 | if (pte_val(*ptep) & _PAGE_INVALID) |
1068 | return; | |
1b948d6c MS |
1069 | active = (mm == current->active_mm) ? 1 : 0; |
1070 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
1071 | if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active && | |
1072 | cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) | |
1073 | __ptep_ipte_local(address, ptep); | |
1074 | else | |
1075 | __ptep_ipte(address, ptep); | |
1076 | atomic_sub(0x10000, &mm->context.attach_count); | |
9282ed92 GS |
1077 | } |
1078 | ||
5c474a1e MS |
1079 | static inline void ptep_flush_lazy(struct mm_struct *mm, |
1080 | unsigned long address, pte_t *ptep) | |
1081 | { | |
53e857f3 | 1082 | int active, count; |
5c474a1e | 1083 | |
53e857f3 MS |
1084 | if (pte_val(*ptep) & _PAGE_INVALID) |
1085 | return; | |
1086 | active = (mm == current->active_mm) ? 1 : 0; | |
1087 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
1088 | if ((count & 0xffff) <= active) { | |
1089 | pte_val(*ptep) |= _PAGE_INVALID; | |
5c474a1e | 1090 | mm->context.flush_mm = 1; |
53e857f3 MS |
1091 | } else |
1092 | __ptep_ipte(address, ptep); | |
1093 | atomic_sub(0x10000, &mm->context.attach_count); | |
5c474a1e MS |
1094 | } |
1095 | ||
0a61b222 MS |
1096 | /* |
1097 | * Get (and clear) the user dirty bit for a pte. | |
1098 | */ | |
1099 | static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, | |
1100 | unsigned long addr, | |
1101 | pte_t *ptep) | |
1102 | { | |
1103 | pgste_t pgste; | |
1104 | pte_t pte; | |
1105 | int dirty; | |
1106 | ||
1107 | if (!mm_has_pgste(mm)) | |
1108 | return 0; | |
1109 | pgste = pgste_get_lock(ptep); | |
1110 | dirty = !!(pgste_val(pgste) & PGSTE_UC_BIT); | |
1111 | pgste_val(pgste) &= ~PGSTE_UC_BIT; | |
1112 | pte = *ptep; | |
1113 | if (dirty && (pte_val(pte) & _PAGE_PRESENT)) { | |
55dbbdd9 | 1114 | pgste = pgste_ipte_notify(mm, addr, ptep, pgste); |
0a61b222 MS |
1115 | __ptep_ipte(addr, ptep); |
1116 | if (MACHINE_HAS_ESOP || !(pte_val(pte) & _PAGE_WRITE)) | |
1117 | pte_val(pte) |= _PAGE_PROTECT; | |
1118 | else | |
1119 | pte_val(pte) |= _PAGE_INVALID; | |
1120 | *ptep = pte; | |
1121 | } | |
1122 | pgste_set_unlock(ptep, pgste); | |
1123 | return dirty; | |
1124 | } | |
1125 | ||
0944fe3f MS |
1126 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
1127 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, | |
1128 | unsigned long addr, pte_t *ptep) | |
1129 | { | |
1130 | pgste_t pgste; | |
1131 | pte_t pte; | |
1132 | int young; | |
1133 | ||
1134 | if (mm_has_pgste(vma->vm_mm)) { | |
1135 | pgste = pgste_get_lock(ptep); | |
55dbbdd9 | 1136 | pgste = pgste_ipte_notify(vma->vm_mm, addr, ptep, pgste); |
0944fe3f MS |
1137 | } |
1138 | ||
1139 | pte = *ptep; | |
53e857f3 | 1140 | ptep_flush_direct(vma->vm_mm, addr, ptep); |
0944fe3f MS |
1141 | young = pte_young(pte); |
1142 | pte = pte_mkold(pte); | |
1143 | ||
1144 | if (mm_has_pgste(vma->vm_mm)) { | |
0a61b222 | 1145 | pgste = pgste_set_pte(ptep, pgste, pte); |
0944fe3f MS |
1146 | pgste_set_unlock(ptep, pgste); |
1147 | } else | |
1148 | *ptep = pte; | |
1149 | ||
1150 | return young; | |
1151 | } | |
1152 | ||
1153 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
1154 | static inline int ptep_clear_flush_young(struct vm_area_struct *vma, | |
1155 | unsigned long address, pte_t *ptep) | |
1156 | { | |
1157 | return ptep_test_and_clear_young(vma, address, ptep); | |
1158 | } | |
1159 | ||
ba8a9229 MS |
1160 | /* |
1161 | * This is hard to understand. ptep_get_and_clear and ptep_clear_flush | |
1162 | * both clear the TLB for the unmapped pte. The reason is that | |
1163 | * ptep_get_and_clear is used in common code (e.g. change_pte_range) | |
1164 | * to modify an active pte. The sequence is | |
1165 | * 1) ptep_get_and_clear | |
1166 | * 2) set_pte_at | |
1167 | * 3) flush_tlb_range | |
1168 | * On s390 the tlb needs to get flushed with the modification of the pte | |
1169 | * if the pte is active. The only way how this can be implemented is to | |
1170 | * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range | |
1171 | * is a nop. | |
1172 | */ | |
1173 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
b2fa47e6 MS |
1174 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, |
1175 | unsigned long address, pte_t *ptep) | |
1176 | { | |
1177 | pgste_t pgste; | |
1178 | pte_t pte; | |
1179 | ||
d3383632 | 1180 | if (mm_has_pgste(mm)) { |
b2fa47e6 | 1181 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1182 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1183 | } |
b2fa47e6 MS |
1184 | |
1185 | pte = *ptep; | |
5c474a1e | 1186 | ptep_flush_lazy(mm, address, ptep); |
e5098611 | 1187 | pte_val(*ptep) = _PAGE_INVALID; |
b2fa47e6 MS |
1188 | |
1189 | if (mm_has_pgste(mm)) { | |
65eef335 | 1190 | pgste = pgste_update_all(&pte, pgste, mm); |
b2fa47e6 MS |
1191 | pgste_set_unlock(ptep, pgste); |
1192 | } | |
1193 | return pte; | |
1194 | } | |
1195 | ||
1196 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION | |
1197 | static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, | |
1198 | unsigned long address, | |
1199 | pte_t *ptep) | |
1200 | { | |
d3383632 | 1201 | pgste_t pgste; |
b2fa47e6 MS |
1202 | pte_t pte; |
1203 | ||
d3383632 MS |
1204 | if (mm_has_pgste(mm)) { |
1205 | pgste = pgste_get_lock(ptep); | |
55dbbdd9 | 1206 | pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1207 | } |
b2fa47e6 MS |
1208 | |
1209 | pte = *ptep; | |
5c474a1e | 1210 | ptep_flush_lazy(mm, address, ptep); |
b56433cb | 1211 | |
3a82603b | 1212 | if (mm_has_pgste(mm)) { |
65eef335 | 1213 | pgste = pgste_update_all(&pte, pgste, mm); |
3a82603b CB |
1214 | pgste_set(ptep, pgste); |
1215 | } | |
b2fa47e6 MS |
1216 | return pte; |
1217 | } | |
1218 | ||
1219 | static inline void ptep_modify_prot_commit(struct mm_struct *mm, | |
1220 | unsigned long address, | |
1221 | pte_t *ptep, pte_t pte) | |
1222 | { | |
b56433cb CB |
1223 | pgste_t pgste; |
1224 | ||
abf09bed | 1225 | if (mm_has_pgste(mm)) { |
d56c893d | 1226 | pgste = pgste_get(ptep); |
65eef335 | 1227 | pgste_set_key(ptep, pgste, pte, mm); |
0a61b222 | 1228 | pgste = pgste_set_pte(ptep, pgste, pte); |
b56433cb | 1229 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1230 | } else |
1231 | *ptep = pte; | |
b2fa47e6 | 1232 | } |
ba8a9229 MS |
1233 | |
1234 | #define __HAVE_ARCH_PTEP_CLEAR_FLUSH | |
f0e47c22 MS |
1235 | static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, |
1236 | unsigned long address, pte_t *ptep) | |
1237 | { | |
b2fa47e6 MS |
1238 | pgste_t pgste; |
1239 | pte_t pte; | |
1240 | ||
d3383632 | 1241 | if (mm_has_pgste(vma->vm_mm)) { |
b2fa47e6 | 1242 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1243 | pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); |
d3383632 | 1244 | } |
b2fa47e6 MS |
1245 | |
1246 | pte = *ptep; | |
53e857f3 | 1247 | ptep_flush_direct(vma->vm_mm, address, ptep); |
e5098611 | 1248 | pte_val(*ptep) = _PAGE_INVALID; |
b2fa47e6 MS |
1249 | |
1250 | if (mm_has_pgste(vma->vm_mm)) { | |
b31288fa KW |
1251 | if ((pgste_val(pgste) & _PGSTE_GPS_USAGE_MASK) == |
1252 | _PGSTE_GPS_USAGE_UNUSED) | |
1253 | pte_val(pte) |= _PAGE_UNUSED; | |
65eef335 | 1254 | pgste = pgste_update_all(&pte, pgste, vma->vm_mm); |
b2fa47e6 MS |
1255 | pgste_set_unlock(ptep, pgste); |
1256 | } | |
1da177e4 LT |
1257 | return pte; |
1258 | } | |
1259 | ||
ba8a9229 MS |
1260 | /* |
1261 | * The batched pte unmap code uses ptep_get_and_clear_full to clear the | |
1262 | * ptes. Here an optimization is possible. tlb_gather_mmu flushes all | |
1263 | * tlbs of an mm if it can guarantee that the ptes of the mm_struct | |
1264 | * cannot be accessed while the batched unmap is running. In this case | |
1265 | * full==1 and a simple pte_clear is enough. See tlb.h. | |
1266 | */ | |
1267 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL | |
1268 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
b2fa47e6 | 1269 | unsigned long address, |
ba8a9229 | 1270 | pte_t *ptep, int full) |
1da177e4 | 1271 | { |
b2fa47e6 MS |
1272 | pgste_t pgste; |
1273 | pte_t pte; | |
1274 | ||
a055f66a | 1275 | if (!full && mm_has_pgste(mm)) { |
b2fa47e6 | 1276 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1277 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1278 | } |
ba8a9229 | 1279 | |
b2fa47e6 MS |
1280 | pte = *ptep; |
1281 | if (!full) | |
5c474a1e | 1282 | ptep_flush_lazy(mm, address, ptep); |
e5098611 | 1283 | pte_val(*ptep) = _PAGE_INVALID; |
b2fa47e6 | 1284 | |
a055f66a | 1285 | if (!full && mm_has_pgste(mm)) { |
65eef335 | 1286 | pgste = pgste_update_all(&pte, pgste, mm); |
b2fa47e6 MS |
1287 | pgste_set_unlock(ptep, pgste); |
1288 | } | |
ba8a9229 | 1289 | return pte; |
1da177e4 LT |
1290 | } |
1291 | ||
ba8a9229 | 1292 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
b2fa47e6 MS |
1293 | static inline pte_t ptep_set_wrprotect(struct mm_struct *mm, |
1294 | unsigned long address, pte_t *ptep) | |
1295 | { | |
1296 | pgste_t pgste; | |
1297 | pte_t pte = *ptep; | |
1298 | ||
1299 | if (pte_write(pte)) { | |
d3383632 | 1300 | if (mm_has_pgste(mm)) { |
b2fa47e6 | 1301 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1302 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1303 | } |
b2fa47e6 | 1304 | |
5c474a1e | 1305 | ptep_flush_lazy(mm, address, ptep); |
abf09bed | 1306 | pte = pte_wrprotect(pte); |
b2fa47e6 | 1307 | |
abf09bed | 1308 | if (mm_has_pgste(mm)) { |
0a61b222 | 1309 | pgste = pgste_set_pte(ptep, pgste, pte); |
b2fa47e6 | 1310 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1311 | } else |
1312 | *ptep = pte; | |
b2fa47e6 MS |
1313 | } |
1314 | return pte; | |
1315 | } | |
ba8a9229 MS |
1316 | |
1317 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
b2fa47e6 MS |
1318 | static inline int ptep_set_access_flags(struct vm_area_struct *vma, |
1319 | unsigned long address, pte_t *ptep, | |
1320 | pte_t entry, int dirty) | |
1321 | { | |
1322 | pgste_t pgste; | |
1323 | ||
1324 | if (pte_same(*ptep, entry)) | |
1325 | return 0; | |
d3383632 | 1326 | if (mm_has_pgste(vma->vm_mm)) { |
b2fa47e6 | 1327 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1328 | pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); |
d3383632 | 1329 | } |
b2fa47e6 | 1330 | |
53e857f3 | 1331 | ptep_flush_direct(vma->vm_mm, address, ptep); |
b2fa47e6 | 1332 | |
abf09bed | 1333 | if (mm_has_pgste(vma->vm_mm)) { |
0a61b222 | 1334 | pgste = pgste_set_pte(ptep, pgste, entry); |
b2fa47e6 | 1335 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1336 | } else |
1337 | *ptep = entry; | |
b2fa47e6 MS |
1338 | return 1; |
1339 | } | |
1da177e4 | 1340 | |
1da177e4 LT |
1341 | /* |
1342 | * Conversion functions: convert a page and protection to a page entry, | |
1343 | * and a page entry and page directory to the page they refer to. | |
1344 | */ | |
1345 | static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) | |
1346 | { | |
1347 | pte_t __pte; | |
1348 | pte_val(__pte) = physpage + pgprot_val(pgprot); | |
0944fe3f | 1349 | return pte_mkyoung(__pte); |
1da177e4 LT |
1350 | } |
1351 | ||
2dcea57a HC |
1352 | static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) |
1353 | { | |
0b2b6e1d | 1354 | unsigned long physpage = page_to_phys(page); |
abf09bed | 1355 | pte_t __pte = mk_pte_phys(physpage, pgprot); |
1da177e4 | 1356 | |
e5098611 MS |
1357 | if (pte_write(__pte) && PageDirty(page)) |
1358 | __pte = pte_mkdirty(__pte); | |
abf09bed | 1359 | return __pte; |
2dcea57a HC |
1360 | } |
1361 | ||
190a1d72 MS |
1362 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
1363 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) | |
1364 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
1365 | #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) | |
1da177e4 | 1366 | |
190a1d72 MS |
1367 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) |
1368 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
1da177e4 | 1369 | |
f4815ac6 | 1370 | #ifndef CONFIG_64BIT |
1da177e4 | 1371 | |
190a1d72 MS |
1372 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
1373 | #define pud_deref(pmd) ({ BUG(); 0UL; }) | |
1374 | #define pgd_deref(pmd) ({ BUG(); 0UL; }) | |
46a82b2d | 1375 | |
190a1d72 MS |
1376 | #define pud_offset(pgd, address) ((pud_t *) pgd) |
1377 | #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address)) | |
1da177e4 | 1378 | |
f4815ac6 | 1379 | #else /* CONFIG_64BIT */ |
1da177e4 | 1380 | |
190a1d72 MS |
1381 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
1382 | #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) | |
5a216a20 | 1383 | #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) |
1da177e4 | 1384 | |
5a216a20 MS |
1385 | static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) |
1386 | { | |
6252d702 MS |
1387 | pud_t *pud = (pud_t *) pgd; |
1388 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) | |
1389 | pud = (pud_t *) pgd_deref(*pgd); | |
5a216a20 MS |
1390 | return pud + pud_index(address); |
1391 | } | |
1da177e4 | 1392 | |
190a1d72 | 1393 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) |
1da177e4 | 1394 | { |
6252d702 MS |
1395 | pmd_t *pmd = (pmd_t *) pud; |
1396 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) | |
1397 | pmd = (pmd_t *) pud_deref(*pud); | |
190a1d72 | 1398 | return pmd + pmd_index(address); |
1da177e4 LT |
1399 | } |
1400 | ||
f4815ac6 | 1401 | #endif /* CONFIG_64BIT */ |
1da177e4 | 1402 | |
190a1d72 MS |
1403 | #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) |
1404 | #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) | |
1405 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
1da177e4 | 1406 | |
152125b7 | 1407 | #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) |
1da177e4 | 1408 | |
190a1d72 MS |
1409 | /* Find an entry in the lowest level page table.. */ |
1410 | #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) | |
1411 | #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) | |
1da177e4 | 1412 | #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) |
1da177e4 | 1413 | #define pte_unmap(pte) do { } while (0) |
1da177e4 | 1414 | |
106c992a | 1415 | #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) |
1ae1c1d0 GS |
1416 | static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) |
1417 | { | |
d8e7a33d | 1418 | /* |
e5098611 | 1419 | * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx) |
d8e7a33d GS |
1420 | * Convert to segment table entry format. |
1421 | */ | |
1422 | if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) | |
1423 | return pgprot_val(SEGMENT_NONE); | |
e5098611 MS |
1424 | if (pgprot_val(pgprot) == pgprot_val(PAGE_READ)) |
1425 | return pgprot_val(SEGMENT_READ); | |
1426 | return pgprot_val(SEGMENT_WRITE); | |
1ae1c1d0 GS |
1427 | } |
1428 | ||
152125b7 | 1429 | static inline pmd_t pmd_wrprotect(pmd_t pmd) |
0944fe3f | 1430 | { |
152125b7 MS |
1431 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_WRITE; |
1432 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1433 | return pmd; | |
1434 | } | |
1435 | ||
1436 | static inline pmd_t pmd_mkwrite(pmd_t pmd) | |
1437 | { | |
1438 | pmd_val(pmd) |= _SEGMENT_ENTRY_WRITE; | |
1439 | if (pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) | |
1440 | return pmd; | |
1441 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; | |
1442 | return pmd; | |
1443 | } | |
1444 | ||
1445 | static inline pmd_t pmd_mkclean(pmd_t pmd) | |
1446 | { | |
1447 | if (pmd_large(pmd)) { | |
1448 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_DIRTY; | |
0944fe3f | 1449 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; |
152125b7 MS |
1450 | } |
1451 | return pmd; | |
1452 | } | |
1453 | ||
1454 | static inline pmd_t pmd_mkdirty(pmd_t pmd) | |
1455 | { | |
1456 | if (pmd_large(pmd)) { | |
1457 | pmd_val(pmd) |= _SEGMENT_ENTRY_DIRTY; | |
1458 | if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) | |
1459 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; | |
1460 | } | |
1461 | return pmd; | |
1462 | } | |
1463 | ||
1464 | static inline pmd_t pmd_mkyoung(pmd_t pmd) | |
1465 | { | |
1466 | if (pmd_large(pmd)) { | |
0944fe3f | 1467 | pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; |
152125b7 MS |
1468 | if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) |
1469 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID; | |
0944fe3f | 1470 | } |
0944fe3f MS |
1471 | return pmd; |
1472 | } | |
1473 | ||
1474 | static inline pmd_t pmd_mkold(pmd_t pmd) | |
1475 | { | |
152125b7 | 1476 | if (pmd_large(pmd)) { |
0944fe3f MS |
1477 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG; |
1478 | pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; | |
1479 | } | |
0944fe3f MS |
1480 | return pmd; |
1481 | } | |
1482 | ||
1ae1c1d0 GS |
1483 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) |
1484 | { | |
152125b7 MS |
1485 | if (pmd_large(pmd)) { |
1486 | pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN_LARGE | | |
1487 | _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_YOUNG | | |
1488 | _SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_SPLIT; | |
1489 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); | |
1490 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) | |
1491 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1492 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) | |
1493 | pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; | |
1494 | return pmd; | |
1495 | } | |
1496 | pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN; | |
1ae1c1d0 GS |
1497 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); |
1498 | return pmd; | |
1499 | } | |
1500 | ||
106c992a | 1501 | static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) |
1ae1c1d0 | 1502 | { |
106c992a GS |
1503 | pmd_t __pmd; |
1504 | pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); | |
152125b7 | 1505 | return __pmd; |
1ae1c1d0 GS |
1506 | } |
1507 | ||
106c992a GS |
1508 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ |
1509 | ||
1b948d6c MS |
1510 | static inline void __pmdp_csp(pmd_t *pmdp) |
1511 | { | |
1512 | register unsigned long reg2 asm("2") = pmd_val(*pmdp); | |
1513 | register unsigned long reg3 asm("3") = pmd_val(*pmdp) | | |
1514 | _SEGMENT_ENTRY_INVALID; | |
1515 | register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5; | |
1516 | ||
1517 | asm volatile( | |
1518 | " csp %1,%3" | |
1519 | : "=m" (*pmdp) | |
1520 | : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc"); | |
1521 | } | |
1522 | ||
1523 | static inline void __pmdp_idte(unsigned long address, pmd_t *pmdp) | |
1524 | { | |
1525 | unsigned long sto; | |
1526 | ||
1527 | sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t); | |
1528 | asm volatile( | |
1529 | " .insn rrf,0xb98e0000,%2,%3,0,0" | |
1530 | : "=m" (*pmdp) | |
1531 | : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK)) | |
1532 | : "cc" ); | |
1533 | } | |
1534 | ||
1535 | static inline void __pmdp_idte_local(unsigned long address, pmd_t *pmdp) | |
1536 | { | |
1537 | unsigned long sto; | |
1538 | ||
1539 | sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t); | |
1540 | asm volatile( | |
1541 | " .insn rrf,0xb98e0000,%2,%3,0,1" | |
1542 | : "=m" (*pmdp) | |
1543 | : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK)) | |
1544 | : "cc" ); | |
1545 | } | |
1546 | ||
1547 | static inline void pmdp_flush_direct(struct mm_struct *mm, | |
1548 | unsigned long address, pmd_t *pmdp) | |
1549 | { | |
1550 | int active, count; | |
1551 | ||
1552 | if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID) | |
1553 | return; | |
1554 | if (!MACHINE_HAS_IDTE) { | |
1555 | __pmdp_csp(pmdp); | |
1556 | return; | |
1557 | } | |
1558 | active = (mm == current->active_mm) ? 1 : 0; | |
1559 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
1560 | if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active && | |
1561 | cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) | |
1562 | __pmdp_idte_local(address, pmdp); | |
1563 | else | |
1564 | __pmdp_idte(address, pmdp); | |
1565 | atomic_sub(0x10000, &mm->context.attach_count); | |
1566 | } | |
1567 | ||
3eabaee9 MS |
1568 | static inline void pmdp_flush_lazy(struct mm_struct *mm, |
1569 | unsigned long address, pmd_t *pmdp) | |
1570 | { | |
53e857f3 | 1571 | int active, count; |
3eabaee9 | 1572 | |
1b948d6c MS |
1573 | if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID) |
1574 | return; | |
53e857f3 MS |
1575 | active = (mm == current->active_mm) ? 1 : 0; |
1576 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
1577 | if ((count & 0xffff) <= active) { | |
1578 | pmd_val(*pmdp) |= _SEGMENT_ENTRY_INVALID; | |
3eabaee9 | 1579 | mm->context.flush_mm = 1; |
1b948d6c MS |
1580 | } else if (MACHINE_HAS_IDTE) |
1581 | __pmdp_idte(address, pmdp); | |
1582 | else | |
1583 | __pmdp_csp(pmdp); | |
53e857f3 | 1584 | atomic_sub(0x10000, &mm->context.attach_count); |
3eabaee9 MS |
1585 | } |
1586 | ||
106c992a GS |
1587 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1588 | ||
1589 | #define __HAVE_ARCH_PGTABLE_DEPOSIT | |
6b0b50b0 AK |
1590 | extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, |
1591 | pgtable_t pgtable); | |
106c992a GS |
1592 | |
1593 | #define __HAVE_ARCH_PGTABLE_WITHDRAW | |
6b0b50b0 | 1594 | extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); |
106c992a GS |
1595 | |
1596 | static inline int pmd_trans_splitting(pmd_t pmd) | |
1597 | { | |
152125b7 MS |
1598 | return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) && |
1599 | (pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT); | |
106c992a GS |
1600 | } |
1601 | ||
1602 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, | |
1603 | pmd_t *pmdp, pmd_t entry) | |
1604 | { | |
106c992a GS |
1605 | *pmdp = entry; |
1606 | } | |
1607 | ||
1608 | static inline pmd_t pmd_mkhuge(pmd_t pmd) | |
1609 | { | |
1610 | pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; | |
152125b7 MS |
1611 | pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; |
1612 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1ae1c1d0 GS |
1613 | return pmd; |
1614 | } | |
1615 | ||
1ae1c1d0 GS |
1616 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
1617 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
1618 | unsigned long address, pmd_t *pmdp) | |
1619 | { | |
0944fe3f | 1620 | pmd_t pmd; |
1ae1c1d0 | 1621 | |
0944fe3f | 1622 | pmd = *pmdp; |
1b948d6c | 1623 | pmdp_flush_direct(vma->vm_mm, address, pmdp); |
0944fe3f MS |
1624 | *pmdp = pmd_mkold(pmd); |
1625 | return pmd_young(pmd); | |
1ae1c1d0 GS |
1626 | } |
1627 | ||
1628 | #define __HAVE_ARCH_PMDP_GET_AND_CLEAR | |
1629 | static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, | |
1630 | unsigned long address, pmd_t *pmdp) | |
1631 | { | |
1632 | pmd_t pmd = *pmdp; | |
1633 | ||
1b948d6c | 1634 | pmdp_flush_direct(mm, address, pmdp); |
1ae1c1d0 GS |
1635 | pmd_clear(pmdp); |
1636 | return pmd; | |
1637 | } | |
1638 | ||
1639 | #define __HAVE_ARCH_PMDP_CLEAR_FLUSH | |
1640 | static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma, | |
1641 | unsigned long address, pmd_t *pmdp) | |
1642 | { | |
1643 | return pmdp_get_and_clear(vma->vm_mm, address, pmdp); | |
1644 | } | |
1645 | ||
1646 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
1647 | static inline void pmdp_invalidate(struct vm_area_struct *vma, | |
1648 | unsigned long address, pmd_t *pmdp) | |
1649 | { | |
1b948d6c | 1650 | pmdp_flush_direct(vma->vm_mm, address, pmdp); |
1ae1c1d0 GS |
1651 | } |
1652 | ||
be328650 GS |
1653 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT |
1654 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
1655 | unsigned long address, pmd_t *pmdp) | |
1656 | { | |
1657 | pmd_t pmd = *pmdp; | |
1658 | ||
1659 | if (pmd_write(pmd)) { | |
1b948d6c | 1660 | pmdp_flush_direct(mm, address, pmdp); |
be328650 GS |
1661 | set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd)); |
1662 | } | |
1663 | } | |
1664 | ||
1ae1c1d0 GS |
1665 | #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) |
1666 | #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) | |
1667 | ||
1668 | static inline int pmd_trans_huge(pmd_t pmd) | |
1669 | { | |
1670 | return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; | |
1671 | } | |
1672 | ||
1673 | static inline int has_transparent_hugepage(void) | |
1674 | { | |
1675 | return MACHINE_HAS_HPAGE ? 1 : 0; | |
1676 | } | |
75077afb GS |
1677 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
1678 | ||
1da177e4 LT |
1679 | /* |
1680 | * 31 bit swap entry format: | |
1681 | * A page-table entry has some bits we have to treat in a special way. | |
1682 | * Bits 0, 20 and bit 23 have to be zero, otherwise an specification | |
1683 | * exception will occur instead of a page translation exception. The | |
1684 | * specifiation exception has the bad habit not to store necessary | |
1685 | * information in the lowcore. | |
e5098611 MS |
1686 | * Bits 21, 22, 30 and 31 are used to indicate the page type. |
1687 | * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402 | |
1da177e4 LT |
1688 | * This leaves the bits 1-19 and bits 24-29 to store type and offset. |
1689 | * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19 | |
1690 | * plus 24 for the offset. | |
1691 | * 0| offset |0110|o|type |00| | |
1692 | * 0 0000000001111111111 2222 2 22222 33 | |
1693 | * 0 1234567890123456789 0123 4 56789 01 | |
1694 | * | |
1695 | * 64 bit swap entry format: | |
1696 | * A page-table entry has some bits we have to treat in a special way. | |
1697 | * Bits 52 and bit 55 have to be zero, otherwise an specification | |
1698 | * exception will occur instead of a page translation exception. The | |
1699 | * specifiation exception has the bad habit not to store necessary | |
1700 | * information in the lowcore. | |
e5098611 MS |
1701 | * Bits 53, 54, 62 and 63 are used to indicate the page type. |
1702 | * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402 | |
1da177e4 LT |
1703 | * This leaves the bits 0-51 and bits 56-61 to store type and offset. |
1704 | * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51 | |
1705 | * plus 56 for the offset. | |
1706 | * | offset |0110|o|type |00| | |
1707 | * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66 | |
1708 | * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23 | |
1709 | */ | |
f4815ac6 | 1710 | #ifndef CONFIG_64BIT |
1da177e4 LT |
1711 | #define __SWP_OFFSET_MASK (~0UL >> 12) |
1712 | #else | |
1713 | #define __SWP_OFFSET_MASK (~0UL >> 11) | |
1714 | #endif | |
4448aaf0 | 1715 | static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) |
1da177e4 LT |
1716 | { |
1717 | pte_t pte; | |
1718 | offset &= __SWP_OFFSET_MASK; | |
e5098611 | 1719 | pte_val(pte) = _PAGE_INVALID | _PAGE_TYPE | ((type & 0x1f) << 2) | |
1da177e4 LT |
1720 | ((offset & 1UL) << 7) | ((offset & ~1UL) << 11); |
1721 | return pte; | |
1722 | } | |
1723 | ||
1724 | #define __swp_type(entry) (((entry).val >> 2) & 0x1f) | |
1725 | #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1)) | |
1726 | #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) | |
1727 | ||
1728 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
1729 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
1730 | ||
f4815ac6 | 1731 | #ifndef CONFIG_64BIT |
1da177e4 | 1732 | # define PTE_FILE_MAX_BITS 26 |
f4815ac6 | 1733 | #else /* CONFIG_64BIT */ |
1da177e4 | 1734 | # define PTE_FILE_MAX_BITS 59 |
f4815ac6 | 1735 | #endif /* CONFIG_64BIT */ |
1da177e4 LT |
1736 | |
1737 | #define pte_to_pgoff(__pte) \ | |
1738 | ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f)) | |
1739 | ||
1740 | #define pgoff_to_pte(__off) \ | |
1741 | ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \ | |
e5098611 | 1742 | | _PAGE_INVALID | _PAGE_PROTECT }) |
1da177e4 LT |
1743 | |
1744 | #endif /* !__ASSEMBLY__ */ | |
1745 | ||
1746 | #define kern_addr_valid(addr) (1) | |
1747 | ||
17f34580 HC |
1748 | extern int vmem_add_mapping(unsigned long start, unsigned long size); |
1749 | extern int vmem_remove_mapping(unsigned long start, unsigned long size); | |
402b0862 | 1750 | extern int s390_enable_sie(void); |
934bc131 | 1751 | extern void s390_enable_skey(void); |
f4eb07c1 | 1752 | |
1da177e4 LT |
1753 | /* |
1754 | * No page table caches to initialise | |
1755 | */ | |
765a0cac HC |
1756 | static inline void pgtable_cache_init(void) { } |
1757 | static inline void check_pgt_cache(void) { } | |
1da177e4 | 1758 | |
1da177e4 LT |
1759 | #include <asm-generic/pgtable.h> |
1760 | ||
1761 | #endif /* _S390_PAGE_H */ |