Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * S390 version |
a53c8fab | 3 | * Copyright IBM Corp. 1999, 2000 |
1da177e4 LT |
4 | * Author(s): Hartmut Penner (hp@de.ibm.com) |
5 | * Ulrich Weigand (weigand@de.ibm.com) | |
6 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
7 | * | |
8 | * Derived from "include/asm-i386/pgtable.h" | |
9 | */ | |
10 | ||
11 | #ifndef _ASM_S390_PGTABLE_H | |
12 | #define _ASM_S390_PGTABLE_H | |
13 | ||
1da177e4 LT |
14 | /* |
15 | * The Linux memory management assumes a three-level page table setup. For | |
16 | * s390 31 bit we "fold" the mid level into the top-level page table, so | |
17 | * that we physically have the same two-level page table as the s390 mmu | |
18 | * expects in 31 bit mode. For s390 64 bit we use three of the five levels | |
19 | * the hardware provides (region first and region second tables are not | |
20 | * used). | |
21 | * | |
22 | * The "pgd_xxx()" functions are trivial for a folded two-level | |
23 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | |
24 | * into the pgd entry) | |
25 | * | |
26 | * This file contains the functions and defines necessary to modify and use | |
27 | * the S390 page table tree. | |
28 | */ | |
29 | #ifndef __ASSEMBLY__ | |
9789db08 | 30 | #include <linux/sched.h> |
2dcea57a | 31 | #include <linux/mm_types.h> |
abf09bed | 32 | #include <linux/page-flags.h> |
1da177e4 | 33 | #include <asm/bug.h> |
b2fa47e6 | 34 | #include <asm/page.h> |
1da177e4 | 35 | |
1da177e4 LT |
36 | extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); |
37 | extern void paging_init(void); | |
2b67fc46 | 38 | extern void vmem_map_init(void); |
1da177e4 LT |
39 | |
40 | /* | |
41 | * The S390 doesn't have any external MMU info: the kernel page | |
42 | * tables contain all the necessary information. | |
43 | */ | |
4b3073e1 | 44 | #define update_mmu_cache(vma, address, ptep) do { } while (0) |
b113da65 | 45 | #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) |
1da177e4 LT |
46 | |
47 | /* | |
238ec4ef | 48 | * ZERO_PAGE is a global shared page that is always zero; used |
1da177e4 LT |
49 | * for zero-mapped memory areas etc.. |
50 | */ | |
238ec4ef MS |
51 | |
52 | extern unsigned long empty_zero_page; | |
53 | extern unsigned long zero_page_mask; | |
54 | ||
55 | #define ZERO_PAGE(vaddr) \ | |
56 | (virt_to_page((void *)(empty_zero_page + \ | |
57 | (((unsigned long)(vaddr)) &zero_page_mask)))) | |
816422ad | 58 | #define __HAVE_COLOR_ZERO_PAGE |
238ec4ef | 59 | |
4f2e2903 | 60 | /* TODO: s390 cannot support io_remap_pfn_range... */ |
1da177e4 LT |
61 | #endif /* !__ASSEMBLY__ */ |
62 | ||
63 | /* | |
64 | * PMD_SHIFT determines the size of the area a second-level page | |
65 | * table can map | |
66 | * PGDIR_SHIFT determines what a third-level page table entry can map | |
67 | */ | |
f4815ac6 | 68 | #ifndef CONFIG_64BIT |
146e4b3c MS |
69 | # define PMD_SHIFT 20 |
70 | # define PUD_SHIFT 20 | |
71 | # define PGDIR_SHIFT 20 | |
f4815ac6 | 72 | #else /* CONFIG_64BIT */ |
146e4b3c | 73 | # define PMD_SHIFT 20 |
190a1d72 | 74 | # define PUD_SHIFT 31 |
5a216a20 | 75 | # define PGDIR_SHIFT 42 |
f4815ac6 | 76 | #endif /* CONFIG_64BIT */ |
1da177e4 LT |
77 | |
78 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
79 | #define PMD_MASK (~(PMD_SIZE-1)) | |
190a1d72 MS |
80 | #define PUD_SIZE (1UL << PUD_SHIFT) |
81 | #define PUD_MASK (~(PUD_SIZE-1)) | |
5a216a20 MS |
82 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
83 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
1da177e4 LT |
84 | |
85 | /* | |
86 | * entries per page directory level: the S390 is two-level, so | |
87 | * we don't really have any PMD directory physically. | |
88 | * for S390 segment-table entries are combined to one PGD | |
89 | * that leads to 1024 pte per pgd | |
90 | */ | |
146e4b3c | 91 | #define PTRS_PER_PTE 256 |
f4815ac6 | 92 | #ifndef CONFIG_64BIT |
146e4b3c | 93 | #define PTRS_PER_PMD 1 |
5a216a20 | 94 | #define PTRS_PER_PUD 1 |
f4815ac6 | 95 | #else /* CONFIG_64BIT */ |
146e4b3c | 96 | #define PTRS_PER_PMD 2048 |
5a216a20 | 97 | #define PTRS_PER_PUD 2048 |
f4815ac6 | 98 | #endif /* CONFIG_64BIT */ |
146e4b3c | 99 | #define PTRS_PER_PGD 2048 |
1da177e4 | 100 | |
d455a369 HD |
101 | #define FIRST_USER_ADDRESS 0 |
102 | ||
1da177e4 LT |
103 | #define pte_ERROR(e) \ |
104 | printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) | |
105 | #define pmd_ERROR(e) \ | |
106 | printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) | |
190a1d72 MS |
107 | #define pud_ERROR(e) \ |
108 | printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) | |
1da177e4 LT |
109 | #define pgd_ERROR(e) \ |
110 | printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) | |
111 | ||
112 | #ifndef __ASSEMBLY__ | |
113 | /* | |
c972cc60 HC |
114 | * The vmalloc and module area will always be on the topmost area of the kernel |
115 | * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules. | |
116 | * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where | |
117 | * modules will reside. That makes sure that inter module branches always | |
118 | * happen without trampolines and in addition the placement within a 2GB frame | |
119 | * is branch prediction unit friendly. | |
8b62bc96 | 120 | */ |
239a6425 | 121 | extern unsigned long VMALLOC_START; |
14045ebf MS |
122 | extern unsigned long VMALLOC_END; |
123 | extern struct page *vmemmap; | |
239a6425 | 124 | |
14045ebf | 125 | #define VMEM_MAX_PHYS ((unsigned long) vmemmap) |
5fd9c6e2 | 126 | |
c972cc60 HC |
127 | #ifdef CONFIG_64BIT |
128 | extern unsigned long MODULES_VADDR; | |
129 | extern unsigned long MODULES_END; | |
130 | #define MODULES_VADDR MODULES_VADDR | |
131 | #define MODULES_END MODULES_END | |
132 | #define MODULES_LEN (1UL << 31) | |
133 | #endif | |
134 | ||
1da177e4 LT |
135 | /* |
136 | * A 31 bit pagetable entry of S390 has following format: | |
137 | * | PFRA | | OS | | |
138 | * 0 0IP0 | |
139 | * 00000000001111111111222222222233 | |
140 | * 01234567890123456789012345678901 | |
141 | * | |
142 | * I Page-Invalid Bit: Page is not available for address-translation | |
143 | * P Page-Protection Bit: Store access not possible for page | |
144 | * | |
145 | * A 31 bit segmenttable entry of S390 has following format: | |
146 | * | P-table origin | |PTL | |
147 | * 0 IC | |
148 | * 00000000001111111111222222222233 | |
149 | * 01234567890123456789012345678901 | |
150 | * | |
151 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
152 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
153 | * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256) | |
154 | * | |
155 | * The 31 bit segmenttable origin of S390 has following format: | |
156 | * | |
157 | * |S-table origin | | STL | | |
158 | * X **GPS | |
159 | * 00000000001111111111222222222233 | |
160 | * 01234567890123456789012345678901 | |
161 | * | |
162 | * X Space-Switch event: | |
163 | * G Segment-Invalid Bit: * | |
164 | * P Private-Space Bit: Segment is not private (PoP 3-30) | |
165 | * S Storage-Alteration: | |
166 | * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048) | |
167 | * | |
168 | * A 64 bit pagetable entry of S390 has following format: | |
6a985c61 | 169 | * | PFRA |0IPC| OS | |
1da177e4 LT |
170 | * 0000000000111111111122222222223333333333444444444455555555556666 |
171 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
172 | * | |
173 | * I Page-Invalid Bit: Page is not available for address-translation | |
174 | * P Page-Protection Bit: Store access not possible for page | |
6a985c61 | 175 | * C Change-bit override: HW is not required to set change bit |
1da177e4 LT |
176 | * |
177 | * A 64 bit segmenttable entry of S390 has following format: | |
178 | * | P-table origin | TT | |
179 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
180 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
181 | * | |
182 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
183 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
184 | * P Page-Protection Bit: Store access not possible for page | |
185 | * TT Type 00 | |
186 | * | |
187 | * A 64 bit region table entry of S390 has following format: | |
188 | * | S-table origin | TF TTTL | |
189 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
190 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
191 | * | |
192 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
193 | * TT Type 01 | |
194 | * TF | |
190a1d72 | 195 | * TL Table length |
1da177e4 LT |
196 | * |
197 | * The 64 bit regiontable origin of S390 has following format: | |
198 | * | region table origon | DTTL | |
199 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
200 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
201 | * | |
202 | * X Space-Switch event: | |
203 | * G Segment-Invalid Bit: | |
204 | * P Private-Space Bit: | |
205 | * S Storage-Alteration: | |
206 | * R Real space | |
207 | * TL Table-Length: | |
208 | * | |
209 | * A storage key has the following format: | |
210 | * | ACC |F|R|C|0| | |
211 | * 0 3 4 5 6 7 | |
212 | * ACC: access key | |
213 | * F : fetch protection bit | |
214 | * R : referenced bit | |
215 | * C : changed bit | |
216 | */ | |
217 | ||
218 | /* Hardware bits in the page table entry */ | |
6a985c61 | 219 | #define _PAGE_CO 0x100 /* HW Change-bit override */ |
83377484 MS |
220 | #define _PAGE_RO 0x200 /* HW read-only bit */ |
221 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ | |
3610cce8 MS |
222 | |
223 | /* Software bits in the page table entry */ | |
83377484 MS |
224 | #define _PAGE_SWT 0x001 /* SW pte type bit t */ |
225 | #define _PAGE_SWX 0x002 /* SW pte type bit x */ | |
abf09bed MS |
226 | #define _PAGE_SWC 0x004 /* SW pte changed bit */ |
227 | #define _PAGE_SWR 0x008 /* SW pte referenced bit */ | |
228 | #define _PAGE_SWW 0x010 /* SW pte write bit */ | |
229 | #define _PAGE_SPECIAL 0x020 /* SW associated with special page */ | |
a08cb629 | 230 | #define __HAVE_ARCH_PTE_SPECIAL |
1da177e4 | 231 | |
138c9021 | 232 | /* Set of bits not changed in pte_modify */ |
abf09bed MS |
233 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_CO | \ |
234 | _PAGE_SWC | _PAGE_SWR) | |
138c9021 | 235 | |
83377484 | 236 | /* Six different types of pages. */ |
9282ed92 GS |
237 | #define _PAGE_TYPE_EMPTY 0x400 |
238 | #define _PAGE_TYPE_NONE 0x401 | |
83377484 MS |
239 | #define _PAGE_TYPE_SWAP 0x403 |
240 | #define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */ | |
9282ed92 GS |
241 | #define _PAGE_TYPE_RO 0x200 |
242 | #define _PAGE_TYPE_RW 0x000 | |
1da177e4 | 243 | |
53492b1d GS |
244 | /* |
245 | * Only four types for huge pages, using the invalid bit and protection bit | |
246 | * of a segment table entry. | |
247 | */ | |
248 | #define _HPAGE_TYPE_EMPTY 0x020 /* _SEGMENT_ENTRY_INV */ | |
249 | #define _HPAGE_TYPE_NONE 0x220 | |
250 | #define _HPAGE_TYPE_RO 0x200 /* _SEGMENT_ENTRY_RO */ | |
251 | #define _HPAGE_TYPE_RW 0x000 | |
252 | ||
83377484 MS |
253 | /* |
254 | * PTE type bits are rather complicated. handle_pte_fault uses pte_present, | |
255 | * pte_none and pte_file to find out the pte type WITHOUT holding the page | |
256 | * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to | |
257 | * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs | |
258 | * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards. | |
259 | * This change is done while holding the lock, but the intermediate step | |
260 | * of a previously valid pte with the hw invalid bit set can be observed by | |
261 | * handle_pte_fault. That makes it necessary that all valid pte types with | |
262 | * the hw invalid bit set must be distinguishable from the four pte types | |
263 | * empty, none, swap and file. | |
264 | * | |
265 | * irxt ipte irxt | |
266 | * _PAGE_TYPE_EMPTY 1000 -> 1000 | |
267 | * _PAGE_TYPE_NONE 1001 -> 1001 | |
268 | * _PAGE_TYPE_SWAP 1011 -> 1011 | |
269 | * _PAGE_TYPE_FILE 11?1 -> 11?1 | |
270 | * _PAGE_TYPE_RO 0100 -> 1100 | |
271 | * _PAGE_TYPE_RW 0000 -> 1000 | |
272 | * | |
c1821c2e | 273 | * pte_none is true for bits combinations 1000, 1010, 1100, 1110 |
83377484 MS |
274 | * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001 |
275 | * pte_file is true for bits combinations 1101, 1111 | |
c1821c2e | 276 | * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid. |
83377484 MS |
277 | */ |
278 | ||
f4815ac6 | 279 | #ifndef CONFIG_64BIT |
1da177e4 | 280 | |
3610cce8 MS |
281 | /* Bits in the segment table address-space-control-element */ |
282 | #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */ | |
283 | #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */ | |
284 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
285 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
286 | #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */ | |
1da177e4 | 287 | |
3610cce8 MS |
288 | /* Bits in the segment table entry */ |
289 | #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */ | |
80217147 | 290 | #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ |
3610cce8 MS |
291 | #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ |
292 | #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */ | |
293 | #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */ | |
1da177e4 | 294 | |
3610cce8 MS |
295 | #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL) |
296 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) | |
1da177e4 | 297 | |
6c61cfe9 | 298 | /* Page status table bits for virtualization */ |
0d0dafc1 MS |
299 | #define PGSTE_ACC_BITS 0xf0000000UL |
300 | #define PGSTE_FP_BIT 0x08000000UL | |
301 | #define PGSTE_PCL_BIT 0x00800000UL | |
302 | #define PGSTE_HR_BIT 0x00400000UL | |
303 | #define PGSTE_HC_BIT 0x00200000UL | |
304 | #define PGSTE_GR_BIT 0x00040000UL | |
305 | #define PGSTE_GC_BIT 0x00020000UL | |
306 | #define PGSTE_UR_BIT 0x00008000UL | |
307 | #define PGSTE_UC_BIT 0x00004000UL /* user dirty (migration) */ | |
308 | #define PGSTE_IN_BIT 0x00002000UL /* IPTE notify bit */ | |
6c61cfe9 | 309 | |
f4815ac6 | 310 | #else /* CONFIG_64BIT */ |
1da177e4 | 311 | |
3610cce8 MS |
312 | /* Bits in the segment/region table address-space-control-element */ |
313 | #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ | |
314 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
315 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
316 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
317 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
318 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
319 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
320 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
321 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
322 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
323 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
324 | ||
325 | /* Bits in the region table entry */ | |
326 | #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ | |
abf09bed | 327 | #define _REGION_ENTRY_RO 0x200 /* region protection bit */ |
3610cce8 MS |
328 | #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ |
329 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ | |
330 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
331 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
332 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
333 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
334 | ||
335 | #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) | |
336 | #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV) | |
337 | #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) | |
338 | #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV) | |
339 | #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) | |
340 | #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV) | |
341 | ||
18da2369 | 342 | #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */ |
1819ed1f HC |
343 | #define _REGION3_ENTRY_RO 0x200 /* page protection bit */ |
344 | #define _REGION3_ENTRY_CO 0x100 /* change-recording override */ | |
18da2369 | 345 | |
1da177e4 | 346 | /* Bits in the segment table entry */ |
ea81531d | 347 | #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ |
3610cce8 MS |
348 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ |
349 | #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ | |
350 | #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ | |
1da177e4 | 351 | |
3610cce8 MS |
352 | #define _SEGMENT_ENTRY (0) |
353 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) | |
354 | ||
53492b1d GS |
355 | #define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */ |
356 | #define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */ | |
75077afb GS |
357 | #define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */ |
358 | #define _SEGMENT_ENTRY_SPLIT (1UL << _SEGMENT_ENTRY_SPLIT_BIT) | |
53492b1d | 359 | |
1ae1c1d0 GS |
360 | /* Set of bits not changed in pmd_modify */ |
361 | #define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \ | |
362 | | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO) | |
363 | ||
6c61cfe9 | 364 | /* Page status table bits for virtualization */ |
0d0dafc1 MS |
365 | #define PGSTE_ACC_BITS 0xf000000000000000UL |
366 | #define PGSTE_FP_BIT 0x0800000000000000UL | |
367 | #define PGSTE_PCL_BIT 0x0080000000000000UL | |
368 | #define PGSTE_HR_BIT 0x0040000000000000UL | |
369 | #define PGSTE_HC_BIT 0x0020000000000000UL | |
370 | #define PGSTE_GR_BIT 0x0004000000000000UL | |
371 | #define PGSTE_GC_BIT 0x0002000000000000UL | |
372 | #define PGSTE_UR_BIT 0x0000800000000000UL | |
373 | #define PGSTE_UC_BIT 0x0000400000000000UL /* user dirty (migration) */ | |
374 | #define PGSTE_IN_BIT 0x0000200000000000UL /* IPTE notify bit */ | |
6c61cfe9 | 375 | |
f4815ac6 | 376 | #endif /* CONFIG_64BIT */ |
1da177e4 LT |
377 | |
378 | /* | |
3610cce8 MS |
379 | * A user page table pointer has the space-switch-event bit, the |
380 | * private-space-control bit and the storage-alteration-event-control | |
381 | * bit set. A kernel page table pointer doesn't need them. | |
1da177e4 | 382 | */ |
3610cce8 MS |
383 | #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ |
384 | _ASCE_ALT_EVENT) | |
1da177e4 | 385 | |
1da177e4 | 386 | /* |
9282ed92 | 387 | * Page protection definitions. |
1da177e4 | 388 | */ |
9282ed92 GS |
389 | #define PAGE_NONE __pgprot(_PAGE_TYPE_NONE) |
390 | #define PAGE_RO __pgprot(_PAGE_TYPE_RO) | |
abf09bed MS |
391 | #define PAGE_RW __pgprot(_PAGE_TYPE_RO | _PAGE_SWW) |
392 | #define PAGE_RWC __pgprot(_PAGE_TYPE_RW | _PAGE_SWW | _PAGE_SWC) | |
9282ed92 | 393 | |
abf09bed | 394 | #define PAGE_KERNEL PAGE_RWC |
bddb7ae2 | 395 | #define PAGE_SHARED PAGE_KERNEL |
9282ed92 | 396 | #define PAGE_COPY PAGE_RO |
1da177e4 LT |
397 | |
398 | /* | |
043d0708 MS |
399 | * On s390 the page table entry has an invalid bit and a read-only bit. |
400 | * Read permission implies execute permission and write permission | |
401 | * implies read permission. | |
1da177e4 LT |
402 | */ |
403 | /*xwr*/ | |
9282ed92 GS |
404 | #define __P000 PAGE_NONE |
405 | #define __P001 PAGE_RO | |
406 | #define __P010 PAGE_RO | |
407 | #define __P011 PAGE_RO | |
043d0708 MS |
408 | #define __P100 PAGE_RO |
409 | #define __P101 PAGE_RO | |
410 | #define __P110 PAGE_RO | |
411 | #define __P111 PAGE_RO | |
9282ed92 GS |
412 | |
413 | #define __S000 PAGE_NONE | |
414 | #define __S001 PAGE_RO | |
415 | #define __S010 PAGE_RW | |
416 | #define __S011 PAGE_RW | |
043d0708 MS |
417 | #define __S100 PAGE_RO |
418 | #define __S101 PAGE_RO | |
419 | #define __S110 PAGE_RW | |
420 | #define __S111 PAGE_RW | |
1da177e4 | 421 | |
106c992a GS |
422 | /* |
423 | * Segment entry (large page) protection definitions. | |
424 | */ | |
425 | #define SEGMENT_NONE __pgprot(_HPAGE_TYPE_NONE) | |
426 | #define SEGMENT_RO __pgprot(_HPAGE_TYPE_RO) | |
427 | #define SEGMENT_RW __pgprot(_HPAGE_TYPE_RW) | |
428 | ||
b2fa47e6 | 429 | static inline int mm_exclusive(struct mm_struct *mm) |
1da177e4 | 430 | { |
b2fa47e6 MS |
431 | return likely(mm == current->active_mm && |
432 | atomic_read(&mm->context.attach_count) <= 1); | |
1da177e4 | 433 | } |
1da177e4 | 434 | |
b2fa47e6 MS |
435 | static inline int mm_has_pgste(struct mm_struct *mm) |
436 | { | |
437 | #ifdef CONFIG_PGSTE | |
438 | if (unlikely(mm->context.has_pgste)) | |
439 | return 1; | |
440 | #endif | |
441 | return 0; | |
442 | } | |
1da177e4 LT |
443 | /* |
444 | * pgd/pmd/pte query functions | |
445 | */ | |
f4815ac6 | 446 | #ifndef CONFIG_64BIT |
1da177e4 | 447 | |
4448aaf0 AB |
448 | static inline int pgd_present(pgd_t pgd) { return 1; } |
449 | static inline int pgd_none(pgd_t pgd) { return 0; } | |
450 | static inline int pgd_bad(pgd_t pgd) { return 0; } | |
1da177e4 | 451 | |
190a1d72 MS |
452 | static inline int pud_present(pud_t pud) { return 1; } |
453 | static inline int pud_none(pud_t pud) { return 0; } | |
18da2369 | 454 | static inline int pud_large(pud_t pud) { return 0; } |
190a1d72 MS |
455 | static inline int pud_bad(pud_t pud) { return 0; } |
456 | ||
f4815ac6 | 457 | #else /* CONFIG_64BIT */ |
1da177e4 | 458 | |
5a216a20 MS |
459 | static inline int pgd_present(pgd_t pgd) |
460 | { | |
6252d702 MS |
461 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
462 | return 1; | |
5a216a20 MS |
463 | return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; |
464 | } | |
465 | ||
466 | static inline int pgd_none(pgd_t pgd) | |
467 | { | |
6252d702 MS |
468 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
469 | return 0; | |
5a216a20 MS |
470 | return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL; |
471 | } | |
472 | ||
473 | static inline int pgd_bad(pgd_t pgd) | |
474 | { | |
6252d702 MS |
475 | /* |
476 | * With dynamic page table levels the pgd can be a region table | |
477 | * entry or a segment table entry. Check for the bit that are | |
478 | * invalid for either table entry. | |
479 | */ | |
5a216a20 | 480 | unsigned long mask = |
6252d702 | 481 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & |
5a216a20 MS |
482 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
483 | return (pgd_val(pgd) & mask) != 0; | |
484 | } | |
190a1d72 MS |
485 | |
486 | static inline int pud_present(pud_t pud) | |
1da177e4 | 487 | { |
6252d702 MS |
488 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
489 | return 1; | |
0d017923 | 490 | return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
491 | } |
492 | ||
190a1d72 | 493 | static inline int pud_none(pud_t pud) |
1da177e4 | 494 | { |
6252d702 MS |
495 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
496 | return 0; | |
0d017923 | 497 | return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL; |
1da177e4 LT |
498 | } |
499 | ||
18da2369 HC |
500 | static inline int pud_large(pud_t pud) |
501 | { | |
502 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) | |
503 | return 0; | |
504 | return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); | |
505 | } | |
506 | ||
190a1d72 | 507 | static inline int pud_bad(pud_t pud) |
1da177e4 | 508 | { |
6252d702 MS |
509 | /* |
510 | * With dynamic page table levels the pud can be a region table | |
511 | * entry or a segment table entry. Check for the bit that are | |
512 | * invalid for either table entry. | |
513 | */ | |
5a216a20 | 514 | unsigned long mask = |
6252d702 | 515 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & |
5a216a20 MS |
516 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
517 | return (pud_val(pud) & mask) != 0; | |
1da177e4 LT |
518 | } |
519 | ||
f4815ac6 | 520 | #endif /* CONFIG_64BIT */ |
3610cce8 | 521 | |
4448aaf0 | 522 | static inline int pmd_present(pmd_t pmd) |
1da177e4 | 523 | { |
d8e7a33d GS |
524 | unsigned long mask = _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO; |
525 | return (pmd_val(pmd) & mask) == _HPAGE_TYPE_NONE || | |
526 | !(pmd_val(pmd) & _SEGMENT_ENTRY_INV); | |
1da177e4 LT |
527 | } |
528 | ||
4448aaf0 | 529 | static inline int pmd_none(pmd_t pmd) |
1da177e4 | 530 | { |
d8e7a33d GS |
531 | return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) && |
532 | !(pmd_val(pmd) & _SEGMENT_ENTRY_RO); | |
1da177e4 LT |
533 | } |
534 | ||
378b1e7a HC |
535 | static inline int pmd_large(pmd_t pmd) |
536 | { | |
537 | #ifdef CONFIG_64BIT | |
538 | return !!(pmd_val(pmd) & _SEGMENT_ENTRY_LARGE); | |
539 | #else | |
540 | return 0; | |
541 | #endif | |
542 | } | |
543 | ||
4448aaf0 | 544 | static inline int pmd_bad(pmd_t pmd) |
1da177e4 | 545 | { |
3610cce8 MS |
546 | unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV; |
547 | return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY; | |
1da177e4 LT |
548 | } |
549 | ||
75077afb GS |
550 | #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH |
551 | extern void pmdp_splitting_flush(struct vm_area_struct *vma, | |
552 | unsigned long addr, pmd_t *pmdp); | |
553 | ||
1ae1c1d0 GS |
554 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
555 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, | |
556 | unsigned long address, pmd_t *pmdp, | |
557 | pmd_t entry, int dirty); | |
558 | ||
559 | #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH | |
560 | extern int pmdp_clear_flush_young(struct vm_area_struct *vma, | |
561 | unsigned long address, pmd_t *pmdp); | |
562 | ||
563 | #define __HAVE_ARCH_PMD_WRITE | |
564 | static inline int pmd_write(pmd_t pmd) | |
565 | { | |
566 | return (pmd_val(pmd) & _SEGMENT_ENTRY_RO) == 0; | |
567 | } | |
568 | ||
569 | static inline int pmd_young(pmd_t pmd) | |
570 | { | |
571 | return 0; | |
572 | } | |
573 | ||
4448aaf0 | 574 | static inline int pte_none(pte_t pte) |
1da177e4 | 575 | { |
83377484 | 576 | return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT); |
1da177e4 LT |
577 | } |
578 | ||
4448aaf0 | 579 | static inline int pte_present(pte_t pte) |
1da177e4 | 580 | { |
83377484 MS |
581 | unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX; |
582 | return (pte_val(pte) & mask) == _PAGE_TYPE_NONE || | |
583 | (!(pte_val(pte) & _PAGE_INVALID) && | |
584 | !(pte_val(pte) & _PAGE_SWT)); | |
1da177e4 LT |
585 | } |
586 | ||
4448aaf0 | 587 | static inline int pte_file(pte_t pte) |
1da177e4 | 588 | { |
83377484 MS |
589 | unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT; |
590 | return (pte_val(pte) & mask) == _PAGE_TYPE_FILE; | |
1da177e4 LT |
591 | } |
592 | ||
7e675137 NP |
593 | static inline int pte_special(pte_t pte) |
594 | { | |
a08cb629 | 595 | return (pte_val(pte) & _PAGE_SPECIAL); |
7e675137 NP |
596 | } |
597 | ||
ba8a9229 | 598 | #define __HAVE_ARCH_PTE_SAME |
b2fa47e6 MS |
599 | static inline int pte_same(pte_t a, pte_t b) |
600 | { | |
601 | return pte_val(a) == pte_val(b); | |
602 | } | |
1da177e4 | 603 | |
b2fa47e6 | 604 | static inline pgste_t pgste_get_lock(pte_t *ptep) |
5b7baf05 | 605 | { |
b2fa47e6 | 606 | unsigned long new = 0; |
5b7baf05 | 607 | #ifdef CONFIG_PGSTE |
b2fa47e6 MS |
608 | unsigned long old; |
609 | ||
5b7baf05 | 610 | preempt_disable(); |
b2fa47e6 MS |
611 | asm( |
612 | " lg %0,%2\n" | |
613 | "0: lgr %1,%0\n" | |
0d0dafc1 MS |
614 | " nihh %0,0xff7f\n" /* clear PCL bit in old */ |
615 | " oihh %1,0x0080\n" /* set PCL bit in new */ | |
b2fa47e6 MS |
616 | " csg %0,%1,%2\n" |
617 | " jl 0b\n" | |
618 | : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) | |
a8f6e7f7 | 619 | : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory"); |
5b7baf05 | 620 | #endif |
b2fa47e6 | 621 | return __pgste(new); |
5b7baf05 CB |
622 | } |
623 | ||
b2fa47e6 | 624 | static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste) |
5b7baf05 CB |
625 | { |
626 | #ifdef CONFIG_PGSTE | |
b2fa47e6 | 627 | asm( |
0d0dafc1 | 628 | " nihh %1,0xff7f\n" /* clear PCL bit */ |
b2fa47e6 MS |
629 | " stg %1,%0\n" |
630 | : "=Q" (ptep[PTRS_PER_PTE]) | |
a8f6e7f7 CB |
631 | : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) |
632 | : "cc", "memory"); | |
5b7baf05 CB |
633 | preempt_enable(); |
634 | #endif | |
635 | } | |
636 | ||
3a82603b CB |
637 | static inline void pgste_set(pte_t *ptep, pgste_t pgste) |
638 | { | |
639 | #ifdef CONFIG_PGSTE | |
640 | *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste; | |
641 | #endif | |
642 | } | |
643 | ||
b2fa47e6 | 644 | static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste) |
5b7baf05 CB |
645 | { |
646 | #ifdef CONFIG_PGSTE | |
a43a9d93 | 647 | unsigned long address, bits; |
b2fa47e6 MS |
648 | unsigned char skey; |
649 | ||
b56433cb | 650 | if (pte_val(*ptep) & _PAGE_INVALID) |
09b53883 | 651 | return pgste; |
a43a9d93 HC |
652 | address = pte_val(*ptep) & PAGE_MASK; |
653 | skey = page_get_storage_key(address); | |
b2fa47e6 MS |
654 | bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED); |
655 | /* Clear page changed & referenced bit in the storage key */ | |
7c81878b | 656 | if (bits & _PAGE_CHANGED) |
abf09bed | 657 | page_set_storage_key(address, skey ^ bits, 0); |
7c81878b CO |
658 | else if (bits) |
659 | page_reset_referenced(address); | |
b2fa47e6 | 660 | /* Transfer page changed & referenced bit to guest bits in pgste */ |
0d0dafc1 | 661 | pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */ |
b2fa47e6 | 662 | /* Get host changed & referenced bits from pgste */ |
0d0dafc1 | 663 | bits |= (pgste_val(pgste) & (PGSTE_HR_BIT | PGSTE_HC_BIT)) >> 52; |
abf09bed | 664 | /* Transfer page changed & referenced bit to kvm user bits */ |
0d0dafc1 | 665 | pgste_val(pgste) |= bits << 45; /* PGSTE_UR_BIT & PGSTE_UC_BIT */ |
abf09bed | 666 | /* Clear relevant host bits in pgste. */ |
0d0dafc1 MS |
667 | pgste_val(pgste) &= ~(PGSTE_HR_BIT | PGSTE_HC_BIT); |
668 | pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT); | |
b2fa47e6 MS |
669 | /* Copy page access key and fetch protection bit to pgste */ |
670 | pgste_val(pgste) |= | |
671 | (unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56; | |
abf09bed MS |
672 | /* Transfer referenced bit to pte */ |
673 | pte_val(*ptep) |= (bits & _PAGE_REFERENCED) << 1; | |
b2fa47e6 MS |
674 | #endif |
675 | return pgste; | |
676 | ||
677 | } | |
678 | ||
679 | static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste) | |
680 | { | |
681 | #ifdef CONFIG_PGSTE | |
682 | int young; | |
683 | ||
b56433cb | 684 | if (pte_val(*ptep) & _PAGE_INVALID) |
09b53883 | 685 | return pgste; |
abf09bed | 686 | /* Get referenced bit from storage key */ |
b2fa47e6 | 687 | young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK); |
abf09bed | 688 | if (young) |
0d0dafc1 | 689 | pgste_val(pgste) |= PGSTE_GR_BIT; |
abf09bed | 690 | /* Get host referenced bit from pgste */ |
0d0dafc1 MS |
691 | if (pgste_val(pgste) & PGSTE_HR_BIT) { |
692 | pgste_val(pgste) &= ~PGSTE_HR_BIT; | |
abf09bed MS |
693 | young = 1; |
694 | } | |
695 | /* Transfer referenced bit to kvm user bits and pte */ | |
696 | if (young) { | |
0d0dafc1 | 697 | pgste_val(pgste) |= PGSTE_UR_BIT; |
b2fa47e6 | 698 | pte_val(*ptep) |= _PAGE_SWR; |
abf09bed | 699 | } |
b2fa47e6 MS |
700 | #endif |
701 | return pgste; | |
b2fa47e6 MS |
702 | } |
703 | ||
abf09bed | 704 | static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry) |
b2fa47e6 MS |
705 | { |
706 | #ifdef CONFIG_PGSTE | |
a43a9d93 | 707 | unsigned long address; |
338679f7 | 708 | unsigned long nkey; |
b2fa47e6 | 709 | |
b56433cb | 710 | if (pte_val(entry) & _PAGE_INVALID) |
09b53883 | 711 | return; |
338679f7 | 712 | VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID)); |
09b53883 | 713 | address = pte_val(entry) & PAGE_MASK; |
338679f7 CB |
714 | /* |
715 | * Set page access key and fetch protection bit from pgste. | |
716 | * The guest C/R information is still in the PGSTE, set real | |
717 | * key C/R to 0. | |
718 | */ | |
fe489bf4 | 719 | nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56; |
338679f7 | 720 | page_set_storage_key(address, nkey, 0); |
5b7baf05 CB |
721 | #endif |
722 | } | |
723 | ||
abf09bed MS |
724 | static inline void pgste_set_pte(pte_t *ptep, pte_t entry) |
725 | { | |
726 | if (!MACHINE_HAS_ESOP && (pte_val(entry) & _PAGE_SWW)) { | |
727 | /* | |
728 | * Without enhanced suppression-on-protection force | |
729 | * the dirty bit on for all writable ptes. | |
730 | */ | |
731 | pte_val(entry) |= _PAGE_SWC; | |
732 | pte_val(entry) &= ~_PAGE_RO; | |
733 | } | |
734 | *ptep = entry; | |
735 | } | |
736 | ||
e5992f2e MS |
737 | /** |
738 | * struct gmap_struct - guest address space | |
739 | * @mm: pointer to the parent mm_struct | |
740 | * @table: pointer to the page directory | |
480e5926 | 741 | * @asce: address space control element for gmap page table |
e5992f2e MS |
742 | * @crst_list: list of all crst tables used in the guest address space |
743 | */ | |
744 | struct gmap { | |
745 | struct list_head list; | |
746 | struct mm_struct *mm; | |
747 | unsigned long *table; | |
480e5926 | 748 | unsigned long asce; |
2c70fe44 | 749 | void *private; |
e5992f2e MS |
750 | struct list_head crst_list; |
751 | }; | |
752 | ||
753 | /** | |
754 | * struct gmap_rmap - reverse mapping for segment table entries | |
d3383632 | 755 | * @gmap: pointer to the gmap_struct |
e5992f2e | 756 | * @entry: pointer to a segment table entry |
d3383632 | 757 | * @vmaddr: virtual address in the guest address space |
e5992f2e MS |
758 | */ |
759 | struct gmap_rmap { | |
760 | struct list_head list; | |
d3383632 | 761 | struct gmap *gmap; |
e5992f2e | 762 | unsigned long *entry; |
d3383632 | 763 | unsigned long vmaddr; |
e5992f2e MS |
764 | }; |
765 | ||
766 | /** | |
767 | * struct gmap_pgtable - gmap information attached to a page table | |
768 | * @vmaddr: address of the 1MB segment in the process virtual memory | |
d3383632 | 769 | * @mapper: list of segment table entries mapping a page table |
e5992f2e MS |
770 | */ |
771 | struct gmap_pgtable { | |
772 | unsigned long vmaddr; | |
773 | struct list_head mapper; | |
774 | }; | |
775 | ||
d3383632 MS |
776 | /** |
777 | * struct gmap_notifier - notify function block for page invalidation | |
778 | * @notifier_call: address of callback function | |
779 | */ | |
780 | struct gmap_notifier { | |
781 | struct list_head list; | |
782 | void (*notifier_call)(struct gmap *gmap, unsigned long address); | |
783 | }; | |
784 | ||
e5992f2e MS |
785 | struct gmap *gmap_alloc(struct mm_struct *mm); |
786 | void gmap_free(struct gmap *gmap); | |
787 | void gmap_enable(struct gmap *gmap); | |
788 | void gmap_disable(struct gmap *gmap); | |
789 | int gmap_map_segment(struct gmap *gmap, unsigned long from, | |
d3383632 | 790 | unsigned long to, unsigned long len); |
e5992f2e | 791 | int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len); |
c5034945 HC |
792 | unsigned long __gmap_translate(unsigned long address, struct gmap *); |
793 | unsigned long gmap_translate(unsigned long address, struct gmap *); | |
499069e1 | 794 | unsigned long __gmap_fault(unsigned long address, struct gmap *); |
e5992f2e | 795 | unsigned long gmap_fault(unsigned long address, struct gmap *); |
388186bc | 796 | void gmap_discard(unsigned long from, unsigned long to, struct gmap *); |
e5992f2e | 797 | |
d3383632 MS |
798 | void gmap_register_ipte_notifier(struct gmap_notifier *); |
799 | void gmap_unregister_ipte_notifier(struct gmap_notifier *); | |
800 | int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len); | |
801 | void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *); | |
802 | ||
803 | static inline pgste_t pgste_ipte_notify(struct mm_struct *mm, | |
804 | unsigned long addr, | |
805 | pte_t *ptep, pgste_t pgste) | |
806 | { | |
807 | #ifdef CONFIG_PGSTE | |
0d0dafc1 MS |
808 | if (pgste_val(pgste) & PGSTE_IN_BIT) { |
809 | pgste_val(pgste) &= ~PGSTE_IN_BIT; | |
d3383632 MS |
810 | gmap_do_ipte_notify(mm, addr, ptep); |
811 | } | |
812 | #endif | |
813 | return pgste; | |
814 | } | |
815 | ||
b2fa47e6 MS |
816 | /* |
817 | * Certain architectures need to do special things when PTEs | |
818 | * within a page table are directly modified. Thus, the following | |
819 | * hook is made available. | |
820 | */ | |
821 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
822 | pte_t *ptep, pte_t entry) | |
823 | { | |
824 | pgste_t pgste; | |
825 | ||
826 | if (mm_has_pgste(mm)) { | |
827 | pgste = pgste_get_lock(ptep); | |
abf09bed MS |
828 | pgste_set_key(ptep, pgste, entry); |
829 | pgste_set_pte(ptep, entry); | |
b2fa47e6 | 830 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
831 | } else { |
832 | if (!(pte_val(entry) & _PAGE_INVALID) && MACHINE_HAS_EDAT1) | |
833 | pte_val(entry) |= _PAGE_CO; | |
b2fa47e6 | 834 | *ptep = entry; |
abf09bed | 835 | } |
b2fa47e6 MS |
836 | } |
837 | ||
1da177e4 LT |
838 | /* |
839 | * query functions pte_write/pte_dirty/pte_young only work if | |
840 | * pte_present() is true. Undefined behaviour if not.. | |
841 | */ | |
4448aaf0 | 842 | static inline int pte_write(pte_t pte) |
1da177e4 | 843 | { |
abf09bed | 844 | return (pte_val(pte) & _PAGE_SWW) != 0; |
1da177e4 LT |
845 | } |
846 | ||
4448aaf0 | 847 | static inline int pte_dirty(pte_t pte) |
1da177e4 | 848 | { |
abf09bed | 849 | return (pte_val(pte) & _PAGE_SWC) != 0; |
1da177e4 LT |
850 | } |
851 | ||
4448aaf0 | 852 | static inline int pte_young(pte_t pte) |
1da177e4 | 853 | { |
b2fa47e6 MS |
854 | #ifdef CONFIG_PGSTE |
855 | if (pte_val(pte) & _PAGE_SWR) | |
856 | return 1; | |
857 | #endif | |
1da177e4 LT |
858 | return 0; |
859 | } | |
860 | ||
1da177e4 LT |
861 | /* |
862 | * pgd/pmd/pte modification functions | |
863 | */ | |
864 | ||
b2fa47e6 | 865 | static inline void pgd_clear(pgd_t *pgd) |
5a216a20 | 866 | { |
f4815ac6 | 867 | #ifdef CONFIG_64BIT |
6252d702 MS |
868 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) |
869 | pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; | |
b2fa47e6 | 870 | #endif |
5a216a20 MS |
871 | } |
872 | ||
b2fa47e6 | 873 | static inline void pud_clear(pud_t *pud) |
1da177e4 | 874 | { |
f4815ac6 | 875 | #ifdef CONFIG_64BIT |
6252d702 MS |
876 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) |
877 | pud_val(*pud) = _REGION3_ENTRY_EMPTY; | |
b2fa47e6 | 878 | #endif |
1da177e4 LT |
879 | } |
880 | ||
b2fa47e6 | 881 | static inline void pmd_clear(pmd_t *pmdp) |
1da177e4 | 882 | { |
3610cce8 | 883 | pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY; |
1da177e4 LT |
884 | } |
885 | ||
4448aaf0 | 886 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
1da177e4 | 887 | { |
9282ed92 | 888 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; |
1da177e4 LT |
889 | } |
890 | ||
891 | /* | |
892 | * The following pte modification functions only work if | |
893 | * pte_present() is true. Undefined behaviour if not.. | |
894 | */ | |
4448aaf0 | 895 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
1da177e4 | 896 | { |
138c9021 | 897 | pte_val(pte) &= _PAGE_CHG_MASK; |
1da177e4 | 898 | pte_val(pte) |= pgprot_val(newprot); |
abf09bed MS |
899 | if ((pte_val(pte) & _PAGE_SWC) && (pte_val(pte) & _PAGE_SWW)) |
900 | pte_val(pte) &= ~_PAGE_RO; | |
1da177e4 LT |
901 | return pte; |
902 | } | |
903 | ||
4448aaf0 | 904 | static inline pte_t pte_wrprotect(pte_t pte) |
1da177e4 | 905 | { |
abf09bed | 906 | pte_val(pte) &= ~_PAGE_SWW; |
9282ed92 | 907 | /* Do not clobber _PAGE_TYPE_NONE pages! */ |
1da177e4 LT |
908 | if (!(pte_val(pte) & _PAGE_INVALID)) |
909 | pte_val(pte) |= _PAGE_RO; | |
910 | return pte; | |
911 | } | |
912 | ||
4448aaf0 | 913 | static inline pte_t pte_mkwrite(pte_t pte) |
1da177e4 | 914 | { |
abf09bed MS |
915 | pte_val(pte) |= _PAGE_SWW; |
916 | if (pte_val(pte) & _PAGE_SWC) | |
917 | pte_val(pte) &= ~_PAGE_RO; | |
1da177e4 LT |
918 | return pte; |
919 | } | |
920 | ||
4448aaf0 | 921 | static inline pte_t pte_mkclean(pte_t pte) |
1da177e4 | 922 | { |
b2fa47e6 | 923 | pte_val(pte) &= ~_PAGE_SWC; |
abf09bed MS |
924 | /* Do not clobber _PAGE_TYPE_NONE pages! */ |
925 | if (!(pte_val(pte) & _PAGE_INVALID)) | |
926 | pte_val(pte) |= _PAGE_RO; | |
1da177e4 LT |
927 | return pte; |
928 | } | |
929 | ||
4448aaf0 | 930 | static inline pte_t pte_mkdirty(pte_t pte) |
1da177e4 | 931 | { |
abf09bed MS |
932 | pte_val(pte) |= _PAGE_SWC; |
933 | if (pte_val(pte) & _PAGE_SWW) | |
934 | pte_val(pte) &= ~_PAGE_RO; | |
1da177e4 LT |
935 | return pte; |
936 | } | |
937 | ||
4448aaf0 | 938 | static inline pte_t pte_mkold(pte_t pte) |
1da177e4 | 939 | { |
b2fa47e6 MS |
940 | #ifdef CONFIG_PGSTE |
941 | pte_val(pte) &= ~_PAGE_SWR; | |
942 | #endif | |
1da177e4 LT |
943 | return pte; |
944 | } | |
945 | ||
4448aaf0 | 946 | static inline pte_t pte_mkyoung(pte_t pte) |
1da177e4 | 947 | { |
1da177e4 LT |
948 | return pte; |
949 | } | |
950 | ||
7e675137 NP |
951 | static inline pte_t pte_mkspecial(pte_t pte) |
952 | { | |
a08cb629 | 953 | pte_val(pte) |= _PAGE_SPECIAL; |
7e675137 NP |
954 | return pte; |
955 | } | |
956 | ||
84afdcee HC |
957 | #ifdef CONFIG_HUGETLB_PAGE |
958 | static inline pte_t pte_mkhuge(pte_t pte) | |
959 | { | |
84afdcee HC |
960 | pte_val(pte) |= (_SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_CO); |
961 | return pte; | |
962 | } | |
963 | #endif | |
964 | ||
15e86b0c | 965 | /* |
b2fa47e6 | 966 | * Get (and clear) the user dirty bit for a pte. |
15e86b0c | 967 | */ |
b2fa47e6 MS |
968 | static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, |
969 | pte_t *ptep) | |
15e86b0c | 970 | { |
b2fa47e6 MS |
971 | pgste_t pgste; |
972 | int dirty = 0; | |
973 | ||
974 | if (mm_has_pgste(mm)) { | |
975 | pgste = pgste_get_lock(ptep); | |
976 | pgste = pgste_update_all(ptep, pgste); | |
0d0dafc1 MS |
977 | dirty = !!(pgste_val(pgste) & PGSTE_UC_BIT); |
978 | pgste_val(pgste) &= ~PGSTE_UC_BIT; | |
b2fa47e6 MS |
979 | pgste_set_unlock(ptep, pgste); |
980 | return dirty; | |
15e86b0c | 981 | } |
15e86b0c FF |
982 | return dirty; |
983 | } | |
b2fa47e6 MS |
984 | |
985 | /* | |
986 | * Get (and clear) the user referenced bit for a pte. | |
987 | */ | |
988 | static inline int ptep_test_and_clear_user_young(struct mm_struct *mm, | |
989 | pte_t *ptep) | |
990 | { | |
991 | pgste_t pgste; | |
992 | int young = 0; | |
993 | ||
994 | if (mm_has_pgste(mm)) { | |
995 | pgste = pgste_get_lock(ptep); | |
996 | pgste = pgste_update_young(ptep, pgste); | |
0d0dafc1 MS |
997 | young = !!(pgste_val(pgste) & PGSTE_UR_BIT); |
998 | pgste_val(pgste) &= ~PGSTE_UR_BIT; | |
b2fa47e6 MS |
999 | pgste_set_unlock(ptep, pgste); |
1000 | } | |
1001 | return young; | |
1002 | } | |
15e86b0c | 1003 | |
ba8a9229 MS |
1004 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
1005 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, | |
1006 | unsigned long addr, pte_t *ptep) | |
1da177e4 | 1007 | { |
b2fa47e6 MS |
1008 | pgste_t pgste; |
1009 | pte_t pte; | |
1010 | ||
1011 | if (mm_has_pgste(vma->vm_mm)) { | |
1012 | pgste = pgste_get_lock(ptep); | |
1013 | pgste = pgste_update_young(ptep, pgste); | |
1014 | pte = *ptep; | |
1015 | *ptep = pte_mkold(pte); | |
1016 | pgste_set_unlock(ptep, pgste); | |
1017 | return pte_young(pte); | |
1018 | } | |
1da177e4 LT |
1019 | return 0; |
1020 | } | |
1021 | ||
ba8a9229 MS |
1022 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH |
1023 | static inline int ptep_clear_flush_young(struct vm_area_struct *vma, | |
1024 | unsigned long address, pte_t *ptep) | |
1da177e4 | 1025 | { |
5b7baf05 CB |
1026 | /* No need to flush TLB |
1027 | * On s390 reference bits are in storage key and never in TLB | |
1028 | * With virtualization we handle the reference bit, without we | |
1029 | * we can simply return */ | |
5b7baf05 | 1030 | return ptep_test_and_clear_young(vma, address, ptep); |
1da177e4 LT |
1031 | } |
1032 | ||
9282ed92 | 1033 | static inline void __ptep_ipte(unsigned long address, pte_t *ptep) |
1da177e4 | 1034 | { |
9282ed92 | 1035 | if (!(pte_val(*ptep) & _PAGE_INVALID)) { |
f4815ac6 | 1036 | #ifndef CONFIG_64BIT |
146e4b3c | 1037 | /* pto must point to the start of the segment table */ |
1da177e4 | 1038 | pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00); |
9282ed92 GS |
1039 | #else |
1040 | /* ipte in zarch mode can do the math */ | |
1041 | pte_t *pto = ptep; | |
1042 | #endif | |
94c12cc7 MS |
1043 | asm volatile( |
1044 | " ipte %2,%3" | |
1045 | : "=m" (*ptep) : "m" (*ptep), | |
1046 | "a" (pto), "a" (address)); | |
1da177e4 | 1047 | } |
9282ed92 GS |
1048 | } |
1049 | ||
ba8a9229 MS |
1050 | /* |
1051 | * This is hard to understand. ptep_get_and_clear and ptep_clear_flush | |
1052 | * both clear the TLB for the unmapped pte. The reason is that | |
1053 | * ptep_get_and_clear is used in common code (e.g. change_pte_range) | |
1054 | * to modify an active pte. The sequence is | |
1055 | * 1) ptep_get_and_clear | |
1056 | * 2) set_pte_at | |
1057 | * 3) flush_tlb_range | |
1058 | * On s390 the tlb needs to get flushed with the modification of the pte | |
1059 | * if the pte is active. The only way how this can be implemented is to | |
1060 | * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range | |
1061 | * is a nop. | |
1062 | */ | |
1063 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
b2fa47e6 MS |
1064 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, |
1065 | unsigned long address, pte_t *ptep) | |
1066 | { | |
1067 | pgste_t pgste; | |
1068 | pte_t pte; | |
1069 | ||
1070 | mm->context.flush_mm = 1; | |
d3383632 | 1071 | if (mm_has_pgste(mm)) { |
b2fa47e6 | 1072 | pgste = pgste_get_lock(ptep); |
d3383632 MS |
1073 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); |
1074 | } | |
b2fa47e6 MS |
1075 | |
1076 | pte = *ptep; | |
1077 | if (!mm_exclusive(mm)) | |
1078 | __ptep_ipte(address, ptep); | |
1079 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; | |
1080 | ||
1081 | if (mm_has_pgste(mm)) { | |
1082 | pgste = pgste_update_all(&pte, pgste); | |
1083 | pgste_set_unlock(ptep, pgste); | |
1084 | } | |
1085 | return pte; | |
1086 | } | |
1087 | ||
1088 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION | |
1089 | static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, | |
1090 | unsigned long address, | |
1091 | pte_t *ptep) | |
1092 | { | |
d3383632 | 1093 | pgste_t pgste; |
b2fa47e6 MS |
1094 | pte_t pte; |
1095 | ||
1096 | mm->context.flush_mm = 1; | |
d3383632 MS |
1097 | if (mm_has_pgste(mm)) { |
1098 | pgste = pgste_get_lock(ptep); | |
1099 | pgste_ipte_notify(mm, address, ptep, pgste); | |
1100 | } | |
b2fa47e6 MS |
1101 | |
1102 | pte = *ptep; | |
1103 | if (!mm_exclusive(mm)) | |
1104 | __ptep_ipte(address, ptep); | |
b56433cb | 1105 | |
3a82603b | 1106 | if (mm_has_pgste(mm)) { |
b56433cb | 1107 | pgste = pgste_update_all(&pte, pgste); |
3a82603b CB |
1108 | pgste_set(ptep, pgste); |
1109 | } | |
b2fa47e6 MS |
1110 | return pte; |
1111 | } | |
1112 | ||
1113 | static inline void ptep_modify_prot_commit(struct mm_struct *mm, | |
1114 | unsigned long address, | |
1115 | pte_t *ptep, pte_t pte) | |
1116 | { | |
b56433cb CB |
1117 | pgste_t pgste; |
1118 | ||
abf09bed | 1119 | if (mm_has_pgste(mm)) { |
b56433cb CB |
1120 | pgste = *(pgste_t *)(ptep + PTRS_PER_PTE); |
1121 | pgste_set_key(ptep, pgste, pte); | |
abf09bed | 1122 | pgste_set_pte(ptep, pte); |
b56433cb | 1123 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1124 | } else |
1125 | *ptep = pte; | |
b2fa47e6 | 1126 | } |
ba8a9229 MS |
1127 | |
1128 | #define __HAVE_ARCH_PTEP_CLEAR_FLUSH | |
f0e47c22 MS |
1129 | static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, |
1130 | unsigned long address, pte_t *ptep) | |
1131 | { | |
b2fa47e6 MS |
1132 | pgste_t pgste; |
1133 | pte_t pte; | |
1134 | ||
d3383632 | 1135 | if (mm_has_pgste(vma->vm_mm)) { |
b2fa47e6 | 1136 | pgste = pgste_get_lock(ptep); |
d3383632 MS |
1137 | pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); |
1138 | } | |
b2fa47e6 MS |
1139 | |
1140 | pte = *ptep; | |
1141 | __ptep_ipte(address, ptep); | |
1142 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; | |
1143 | ||
1144 | if (mm_has_pgste(vma->vm_mm)) { | |
1145 | pgste = pgste_update_all(&pte, pgste); | |
1146 | pgste_set_unlock(ptep, pgste); | |
1147 | } | |
1da177e4 LT |
1148 | return pte; |
1149 | } | |
1150 | ||
ba8a9229 MS |
1151 | /* |
1152 | * The batched pte unmap code uses ptep_get_and_clear_full to clear the | |
1153 | * ptes. Here an optimization is possible. tlb_gather_mmu flushes all | |
1154 | * tlbs of an mm if it can guarantee that the ptes of the mm_struct | |
1155 | * cannot be accessed while the batched unmap is running. In this case | |
1156 | * full==1 and a simple pte_clear is enough. See tlb.h. | |
1157 | */ | |
1158 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL | |
1159 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
b2fa47e6 | 1160 | unsigned long address, |
ba8a9229 | 1161 | pte_t *ptep, int full) |
1da177e4 | 1162 | { |
b2fa47e6 MS |
1163 | pgste_t pgste; |
1164 | pte_t pte; | |
1165 | ||
d3383632 | 1166 | if (mm_has_pgste(mm)) { |
b2fa47e6 | 1167 | pgste = pgste_get_lock(ptep); |
d3383632 MS |
1168 | if (!full) |
1169 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); | |
1170 | } | |
ba8a9229 | 1171 | |
b2fa47e6 MS |
1172 | pte = *ptep; |
1173 | if (!full) | |
1174 | __ptep_ipte(address, ptep); | |
1175 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; | |
1176 | ||
1177 | if (mm_has_pgste(mm)) { | |
1178 | pgste = pgste_update_all(&pte, pgste); | |
1179 | pgste_set_unlock(ptep, pgste); | |
1180 | } | |
ba8a9229 | 1181 | return pte; |
1da177e4 LT |
1182 | } |
1183 | ||
ba8a9229 | 1184 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
b2fa47e6 MS |
1185 | static inline pte_t ptep_set_wrprotect(struct mm_struct *mm, |
1186 | unsigned long address, pte_t *ptep) | |
1187 | { | |
1188 | pgste_t pgste; | |
1189 | pte_t pte = *ptep; | |
1190 | ||
1191 | if (pte_write(pte)) { | |
1192 | mm->context.flush_mm = 1; | |
d3383632 | 1193 | if (mm_has_pgste(mm)) { |
b2fa47e6 | 1194 | pgste = pgste_get_lock(ptep); |
d3383632 MS |
1195 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); |
1196 | } | |
b2fa47e6 MS |
1197 | |
1198 | if (!mm_exclusive(mm)) | |
1199 | __ptep_ipte(address, ptep); | |
abf09bed | 1200 | pte = pte_wrprotect(pte); |
b2fa47e6 | 1201 | |
abf09bed MS |
1202 | if (mm_has_pgste(mm)) { |
1203 | pgste_set_pte(ptep, pte); | |
b2fa47e6 | 1204 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1205 | } else |
1206 | *ptep = pte; | |
b2fa47e6 MS |
1207 | } |
1208 | return pte; | |
1209 | } | |
ba8a9229 MS |
1210 | |
1211 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
b2fa47e6 MS |
1212 | static inline int ptep_set_access_flags(struct vm_area_struct *vma, |
1213 | unsigned long address, pte_t *ptep, | |
1214 | pte_t entry, int dirty) | |
1215 | { | |
1216 | pgste_t pgste; | |
1217 | ||
1218 | if (pte_same(*ptep, entry)) | |
1219 | return 0; | |
d3383632 | 1220 | if (mm_has_pgste(vma->vm_mm)) { |
b2fa47e6 | 1221 | pgste = pgste_get_lock(ptep); |
d3383632 MS |
1222 | pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); |
1223 | } | |
b2fa47e6 MS |
1224 | |
1225 | __ptep_ipte(address, ptep); | |
b2fa47e6 | 1226 | |
abf09bed MS |
1227 | if (mm_has_pgste(vma->vm_mm)) { |
1228 | pgste_set_pte(ptep, entry); | |
b2fa47e6 | 1229 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1230 | } else |
1231 | *ptep = entry; | |
b2fa47e6 MS |
1232 | return 1; |
1233 | } | |
1da177e4 | 1234 | |
1da177e4 LT |
1235 | /* |
1236 | * Conversion functions: convert a page and protection to a page entry, | |
1237 | * and a page entry and page directory to the page they refer to. | |
1238 | */ | |
1239 | static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) | |
1240 | { | |
1241 | pte_t __pte; | |
1242 | pte_val(__pte) = physpage + pgprot_val(pgprot); | |
1243 | return __pte; | |
1244 | } | |
1245 | ||
2dcea57a HC |
1246 | static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) |
1247 | { | |
0b2b6e1d | 1248 | unsigned long physpage = page_to_phys(page); |
abf09bed | 1249 | pte_t __pte = mk_pte_phys(physpage, pgprot); |
1da177e4 | 1250 | |
abf09bed MS |
1251 | if ((pte_val(__pte) & _PAGE_SWW) && PageDirty(page)) { |
1252 | pte_val(__pte) |= _PAGE_SWC; | |
1253 | pte_val(__pte) &= ~_PAGE_RO; | |
1254 | } | |
1255 | return __pte; | |
2dcea57a HC |
1256 | } |
1257 | ||
190a1d72 MS |
1258 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
1259 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) | |
1260 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
1261 | #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) | |
1da177e4 | 1262 | |
190a1d72 MS |
1263 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) |
1264 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
1da177e4 | 1265 | |
f4815ac6 | 1266 | #ifndef CONFIG_64BIT |
1da177e4 | 1267 | |
190a1d72 MS |
1268 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
1269 | #define pud_deref(pmd) ({ BUG(); 0UL; }) | |
1270 | #define pgd_deref(pmd) ({ BUG(); 0UL; }) | |
46a82b2d | 1271 | |
190a1d72 MS |
1272 | #define pud_offset(pgd, address) ((pud_t *) pgd) |
1273 | #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address)) | |
1da177e4 | 1274 | |
f4815ac6 | 1275 | #else /* CONFIG_64BIT */ |
1da177e4 | 1276 | |
190a1d72 MS |
1277 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
1278 | #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) | |
5a216a20 | 1279 | #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) |
1da177e4 | 1280 | |
5a216a20 MS |
1281 | static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) |
1282 | { | |
6252d702 MS |
1283 | pud_t *pud = (pud_t *) pgd; |
1284 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) | |
1285 | pud = (pud_t *) pgd_deref(*pgd); | |
5a216a20 MS |
1286 | return pud + pud_index(address); |
1287 | } | |
1da177e4 | 1288 | |
190a1d72 | 1289 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) |
1da177e4 | 1290 | { |
6252d702 MS |
1291 | pmd_t *pmd = (pmd_t *) pud; |
1292 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) | |
1293 | pmd = (pmd_t *) pud_deref(*pud); | |
190a1d72 | 1294 | return pmd + pmd_index(address); |
1da177e4 LT |
1295 | } |
1296 | ||
f4815ac6 | 1297 | #endif /* CONFIG_64BIT */ |
1da177e4 | 1298 | |
190a1d72 MS |
1299 | #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) |
1300 | #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) | |
1301 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
1da177e4 | 1302 | |
190a1d72 | 1303 | #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) |
1da177e4 | 1304 | |
190a1d72 MS |
1305 | /* Find an entry in the lowest level page table.. */ |
1306 | #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) | |
1307 | #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) | |
1da177e4 | 1308 | #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) |
1da177e4 | 1309 | #define pte_unmap(pte) do { } while (0) |
1da177e4 | 1310 | |
1ae1c1d0 GS |
1311 | static inline void __pmd_idte(unsigned long address, pmd_t *pmdp) |
1312 | { | |
1313 | unsigned long sto = (unsigned long) pmdp - | |
1314 | pmd_index(address) * sizeof(pmd_t); | |
1315 | ||
1316 | if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INV)) { | |
1317 | asm volatile( | |
1318 | " .insn rrf,0xb98e0000,%2,%3,0,0" | |
1319 | : "=m" (*pmdp) | |
1320 | : "m" (*pmdp), "a" (sto), | |
1321 | "a" ((address & HPAGE_MASK)) | |
1322 | : "cc" | |
1323 | ); | |
1324 | } | |
1325 | } | |
1326 | ||
106c992a | 1327 | #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) |
1ae1c1d0 GS |
1328 | static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) |
1329 | { | |
d8e7a33d GS |
1330 | /* |
1331 | * pgprot is PAGE_NONE, PAGE_RO, or PAGE_RW (see __Pxxx / __Sxxx) | |
1332 | * Convert to segment table entry format. | |
1333 | */ | |
1334 | if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) | |
1335 | return pgprot_val(SEGMENT_NONE); | |
1336 | if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) | |
1337 | return pgprot_val(SEGMENT_RO); | |
1338 | return pgprot_val(SEGMENT_RW); | |
1ae1c1d0 GS |
1339 | } |
1340 | ||
1341 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) | |
1342 | { | |
1343 | pmd_val(pmd) &= _SEGMENT_CHG_MASK; | |
1344 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); | |
1345 | return pmd; | |
1346 | } | |
1347 | ||
106c992a | 1348 | static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) |
1ae1c1d0 | 1349 | { |
106c992a GS |
1350 | pmd_t __pmd; |
1351 | pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); | |
1352 | return __pmd; | |
1ae1c1d0 GS |
1353 | } |
1354 | ||
1355 | static inline pmd_t pmd_mkwrite(pmd_t pmd) | |
1356 | { | |
d8e7a33d GS |
1357 | /* Do not clobber _HPAGE_TYPE_NONE pages! */ |
1358 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_INV)) | |
1359 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_RO; | |
1ae1c1d0 GS |
1360 | return pmd; |
1361 | } | |
106c992a GS |
1362 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ |
1363 | ||
1364 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
1365 | ||
1366 | #define __HAVE_ARCH_PGTABLE_DEPOSIT | |
6b0b50b0 AK |
1367 | extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, |
1368 | pgtable_t pgtable); | |
106c992a GS |
1369 | |
1370 | #define __HAVE_ARCH_PGTABLE_WITHDRAW | |
6b0b50b0 | 1371 | extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); |
106c992a GS |
1372 | |
1373 | static inline int pmd_trans_splitting(pmd_t pmd) | |
1374 | { | |
1375 | return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT; | |
1376 | } | |
1377 | ||
1378 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, | |
1379 | pmd_t *pmdp, pmd_t entry) | |
1380 | { | |
1381 | if (!(pmd_val(entry) & _SEGMENT_ENTRY_INV) && MACHINE_HAS_EDAT1) | |
1382 | pmd_val(entry) |= _SEGMENT_ENTRY_CO; | |
1383 | *pmdp = entry; | |
1384 | } | |
1385 | ||
1386 | static inline pmd_t pmd_mkhuge(pmd_t pmd) | |
1387 | { | |
1388 | pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; | |
1389 | return pmd; | |
1390 | } | |
1ae1c1d0 GS |
1391 | |
1392 | static inline pmd_t pmd_wrprotect(pmd_t pmd) | |
1393 | { | |
1394 | pmd_val(pmd) |= _SEGMENT_ENTRY_RO; | |
1395 | return pmd; | |
1396 | } | |
1397 | ||
1398 | static inline pmd_t pmd_mkdirty(pmd_t pmd) | |
1399 | { | |
1400 | /* No dirty bit in the segment table entry. */ | |
1401 | return pmd; | |
1402 | } | |
1403 | ||
1404 | static inline pmd_t pmd_mkold(pmd_t pmd) | |
1405 | { | |
1406 | /* No referenced bit in the segment table entry. */ | |
1407 | return pmd; | |
1408 | } | |
1409 | ||
1410 | static inline pmd_t pmd_mkyoung(pmd_t pmd) | |
1411 | { | |
1412 | /* No referenced bit in the segment table entry. */ | |
1413 | return pmd; | |
1414 | } | |
1415 | ||
1416 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG | |
1417 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
1418 | unsigned long address, pmd_t *pmdp) | |
1419 | { | |
1420 | unsigned long pmd_addr = pmd_val(*pmdp) & HPAGE_MASK; | |
1421 | long tmp, rc; | |
1422 | int counter; | |
1423 | ||
1424 | rc = 0; | |
1425 | if (MACHINE_HAS_RRBM) { | |
1426 | counter = PTRS_PER_PTE >> 6; | |
1427 | asm volatile( | |
1428 | "0: .insn rre,0xb9ae0000,%0,%3\n" /* rrbm */ | |
1429 | " ogr %1,%0\n" | |
1430 | " la %3,0(%4,%3)\n" | |
1431 | " brct %2,0b\n" | |
1432 | : "=&d" (tmp), "+&d" (rc), "+d" (counter), | |
1433 | "+a" (pmd_addr) | |
1434 | : "a" (64 * 4096UL) : "cc"); | |
1435 | rc = !!rc; | |
1436 | } else { | |
1437 | counter = PTRS_PER_PTE; | |
1438 | asm volatile( | |
1439 | "0: rrbe 0,%2\n" | |
1440 | " la %2,0(%3,%2)\n" | |
1441 | " brc 12,1f\n" | |
1442 | " lhi %0,1\n" | |
1443 | "1: brct %1,0b\n" | |
1444 | : "+d" (rc), "+d" (counter), "+a" (pmd_addr) | |
1445 | : "a" (4096UL) : "cc"); | |
1446 | } | |
1447 | return rc; | |
1448 | } | |
1449 | ||
1450 | #define __HAVE_ARCH_PMDP_GET_AND_CLEAR | |
1451 | static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, | |
1452 | unsigned long address, pmd_t *pmdp) | |
1453 | { | |
1454 | pmd_t pmd = *pmdp; | |
1455 | ||
1456 | __pmd_idte(address, pmdp); | |
1457 | pmd_clear(pmdp); | |
1458 | return pmd; | |
1459 | } | |
1460 | ||
1461 | #define __HAVE_ARCH_PMDP_CLEAR_FLUSH | |
1462 | static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma, | |
1463 | unsigned long address, pmd_t *pmdp) | |
1464 | { | |
1465 | return pmdp_get_and_clear(vma->vm_mm, address, pmdp); | |
1466 | } | |
1467 | ||
1468 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
1469 | static inline void pmdp_invalidate(struct vm_area_struct *vma, | |
1470 | unsigned long address, pmd_t *pmdp) | |
1471 | { | |
1472 | __pmd_idte(address, pmdp); | |
1473 | } | |
1474 | ||
be328650 GS |
1475 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT |
1476 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
1477 | unsigned long address, pmd_t *pmdp) | |
1478 | { | |
1479 | pmd_t pmd = *pmdp; | |
1480 | ||
1481 | if (pmd_write(pmd)) { | |
1482 | __pmd_idte(address, pmdp); | |
1483 | set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd)); | |
1484 | } | |
1485 | } | |
1486 | ||
1ae1c1d0 GS |
1487 | #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) |
1488 | #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) | |
1489 | ||
1490 | static inline int pmd_trans_huge(pmd_t pmd) | |
1491 | { | |
1492 | return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; | |
1493 | } | |
1494 | ||
1495 | static inline int has_transparent_hugepage(void) | |
1496 | { | |
1497 | return MACHINE_HAS_HPAGE ? 1 : 0; | |
1498 | } | |
1499 | ||
1500 | static inline unsigned long pmd_pfn(pmd_t pmd) | |
1501 | { | |
171c4006 | 1502 | return pmd_val(pmd) >> PAGE_SHIFT; |
1ae1c1d0 | 1503 | } |
75077afb GS |
1504 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
1505 | ||
1da177e4 LT |
1506 | /* |
1507 | * 31 bit swap entry format: | |
1508 | * A page-table entry has some bits we have to treat in a special way. | |
1509 | * Bits 0, 20 and bit 23 have to be zero, otherwise an specification | |
1510 | * exception will occur instead of a page translation exception. The | |
1511 | * specifiation exception has the bad habit not to store necessary | |
1512 | * information in the lowcore. | |
1513 | * Bit 21 and bit 22 are the page invalid bit and the page protection | |
1514 | * bit. We set both to indicate a swapped page. | |
1515 | * Bit 30 and 31 are used to distinguish the different page types. For | |
1516 | * a swapped page these bits need to be zero. | |
1517 | * This leaves the bits 1-19 and bits 24-29 to store type and offset. | |
1518 | * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19 | |
1519 | * plus 24 for the offset. | |
1520 | * 0| offset |0110|o|type |00| | |
1521 | * 0 0000000001111111111 2222 2 22222 33 | |
1522 | * 0 1234567890123456789 0123 4 56789 01 | |
1523 | * | |
1524 | * 64 bit swap entry format: | |
1525 | * A page-table entry has some bits we have to treat in a special way. | |
1526 | * Bits 52 and bit 55 have to be zero, otherwise an specification | |
1527 | * exception will occur instead of a page translation exception. The | |
1528 | * specifiation exception has the bad habit not to store necessary | |
1529 | * information in the lowcore. | |
1530 | * Bit 53 and bit 54 are the page invalid bit and the page protection | |
1531 | * bit. We set both to indicate a swapped page. | |
1532 | * Bit 62 and 63 are used to distinguish the different page types. For | |
1533 | * a swapped page these bits need to be zero. | |
1534 | * This leaves the bits 0-51 and bits 56-61 to store type and offset. | |
1535 | * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51 | |
1536 | * plus 56 for the offset. | |
1537 | * | offset |0110|o|type |00| | |
1538 | * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66 | |
1539 | * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23 | |
1540 | */ | |
f4815ac6 | 1541 | #ifndef CONFIG_64BIT |
1da177e4 LT |
1542 | #define __SWP_OFFSET_MASK (~0UL >> 12) |
1543 | #else | |
1544 | #define __SWP_OFFSET_MASK (~0UL >> 11) | |
1545 | #endif | |
4448aaf0 | 1546 | static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) |
1da177e4 LT |
1547 | { |
1548 | pte_t pte; | |
1549 | offset &= __SWP_OFFSET_MASK; | |
9282ed92 | 1550 | pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) | |
1da177e4 LT |
1551 | ((offset & 1UL) << 7) | ((offset & ~1UL) << 11); |
1552 | return pte; | |
1553 | } | |
1554 | ||
1555 | #define __swp_type(entry) (((entry).val >> 2) & 0x1f) | |
1556 | #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1)) | |
1557 | #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) | |
1558 | ||
1559 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
1560 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
1561 | ||
f4815ac6 | 1562 | #ifndef CONFIG_64BIT |
1da177e4 | 1563 | # define PTE_FILE_MAX_BITS 26 |
f4815ac6 | 1564 | #else /* CONFIG_64BIT */ |
1da177e4 | 1565 | # define PTE_FILE_MAX_BITS 59 |
f4815ac6 | 1566 | #endif /* CONFIG_64BIT */ |
1da177e4 LT |
1567 | |
1568 | #define pte_to_pgoff(__pte) \ | |
1569 | ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f)) | |
1570 | ||
1571 | #define pgoff_to_pte(__off) \ | |
1572 | ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \ | |
9282ed92 | 1573 | | _PAGE_TYPE_FILE }) |
1da177e4 LT |
1574 | |
1575 | #endif /* !__ASSEMBLY__ */ | |
1576 | ||
1577 | #define kern_addr_valid(addr) (1) | |
1578 | ||
17f34580 HC |
1579 | extern int vmem_add_mapping(unsigned long start, unsigned long size); |
1580 | extern int vmem_remove_mapping(unsigned long start, unsigned long size); | |
402b0862 | 1581 | extern int s390_enable_sie(void); |
f4eb07c1 | 1582 | |
1da177e4 LT |
1583 | /* |
1584 | * No page table caches to initialise | |
1585 | */ | |
765a0cac HC |
1586 | static inline void pgtable_cache_init(void) { } |
1587 | static inline void check_pgt_cache(void) { } | |
1da177e4 | 1588 | |
1da177e4 LT |
1589 | #include <asm-generic/pgtable.h> |
1590 | ||
1591 | #endif /* _S390_PAGE_H */ |