projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
s390/zcrypt: remove duplicated include from zcrypt_pcixcc.c
[linux-2.6-block.git] / arch / s390 / include / asm / pgtable.h
CommitLineData
1da177e4 1/*
1da177e4 2 * S390 version
a53c8fab 3 * Copyright IBM Corp. 1999, 2000
1da177e4
LT		 4 * Author(s): Hartmut Penner (hp@de.ibm.com)
5 * Ulrich Weigand (weigand@de.ibm.com)
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/pgtable.h"
9 */
10
11#ifndef _ASM_S390_PGTABLE_H
12#define _ASM_S390_PGTABLE_H
13
1da177e4
LT		 14/*
15 * The Linux memory management assumes a three-level page table setup. For
16 * s390 31 bit we "fold" the mid level into the top-level page table, so
17 * that we physically have the same two-level page table as the s390 mmu
18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
19 * the hardware provides (region first and region second tables are not
20 * used).
21 *
22 * The "pgd_xxx()" functions are trivial for a folded two-level
23 * setup: the pgd is never bad, and a pmd always exists (as it's folded
24 * into the pgd entry)
25 *
26 * This file contains the functions and defines necessary to modify and use
27 * the S390 page table tree.
28 */
29#ifndef __ASSEMBLY__
9789db08 30#include <linux/sched.h>
2dcea57a 31#include <linux/mm_types.h>
1da177e4 32#include <asm/bug.h>
b2fa47e6 33#include <asm/page.h>
1da177e4 34
1da177e4
LT		 35extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
36extern void paging_init(void);
2b67fc46 37extern void vmem_map_init(void);
92f842ea 38extern void fault_init(void);
1da177e4
LT		 39
40/*
41 * The S390 doesn't have any external MMU info: the kernel page
42 * tables contain all the necessary information.
43 */
4b3073e1 44#define update_mmu_cache(vma, address, ptep) do { } while (0)
b113da65 45#define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
1da177e4
LT		 46
47/*
238ec4ef 48 * ZERO_PAGE is a global shared page that is always zero; used
1da177e4
LT		 49 * for zero-mapped memory areas etc..
50 */
238ec4ef
MS		 51
52extern unsigned long empty_zero_page;
53extern unsigned long zero_page_mask;
54
55#define ZERO_PAGE(vaddr) \
56 (virt_to_page((void *)(empty_zero_page + \
57 (((unsigned long)(vaddr)) &zero_page_mask))))
58
59#define is_zero_pfn is_zero_pfn
60static inline int is_zero_pfn(unsigned long pfn)
61{
62 extern unsigned long zero_pfn;
63 unsigned long offset_from_zero_pfn = pfn - zero_pfn;
64 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
65}
66
67#define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr))
68
1da177e4
LT		 69#endif /* !__ASSEMBLY__ */
70
71/*
72 * PMD_SHIFT determines the size of the area a second-level page
73 * table can map
74 * PGDIR_SHIFT determines what a third-level page table entry can map
75 */
f4815ac6 76#ifndef CONFIG_64BIT
146e4b3c
MS		 77# define PMD_SHIFT 20
78# define PUD_SHIFT 20
79# define PGDIR_SHIFT 20
f4815ac6 80#else /* CONFIG_64BIT */
146e4b3c 81# define PMD_SHIFT 20
190a1d72 82# define PUD_SHIFT 31
5a216a20 83# define PGDIR_SHIFT 42
f4815ac6 84#endif /* CONFIG_64BIT */
1da177e4
LT		 85
86#define PMD_SIZE (1UL << PMD_SHIFT)
87#define PMD_MASK (~(PMD_SIZE-1))
190a1d72
MS		 88#define PUD_SIZE (1UL << PUD_SHIFT)
89#define PUD_MASK (~(PUD_SIZE-1))
5a216a20
MS		 90#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
91#define PGDIR_MASK (~(PGDIR_SIZE-1))
1da177e4
LT		 92
93/*
94 * entries per page directory level: the S390 is two-level, so
95 * we don't really have any PMD directory physically.
96 * for S390 segment-table entries are combined to one PGD
97 * that leads to 1024 pte per pgd
98 */
146e4b3c 99#define PTRS_PER_PTE 256
f4815ac6 100#ifndef CONFIG_64BIT
146e4b3c 101#define PTRS_PER_PMD 1
5a216a20 102#define PTRS_PER_PUD 1
f4815ac6 103#else /* CONFIG_64BIT */
146e4b3c 104#define PTRS_PER_PMD 2048
5a216a20 105#define PTRS_PER_PUD 2048
f4815ac6 106#endif /* CONFIG_64BIT */
146e4b3c 107#define PTRS_PER_PGD 2048
1da177e4 108
d455a369
HD		 109#define FIRST_USER_ADDRESS 0
110
1da177e4
LT		 111#define pte_ERROR(e) \
112 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
113#define pmd_ERROR(e) \
114 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
190a1d72
MS		 115#define pud_ERROR(e) \
116 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
1da177e4
LT		 117#define pgd_ERROR(e) \
118 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
119
120#ifndef __ASSEMBLY__
121/*
5fd9c6e2 122 * The vmalloc area will always be on the topmost area of the kernel
7d3f661e 123 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc,
5fd9c6e2
CB		 124 * which should be enough for any sane case.
125 * By putting vmalloc at the top, we maximise the gap between physical
126 * memory and vmalloc to catch misplaced memory accesses. As a side
127 * effect, this also makes sure that 64 bit module code cannot be used
128 * as system call address.
8b62bc96 129 */
239a6425 130extern unsigned long VMALLOC_START;
14045ebf
MS		 131extern unsigned long VMALLOC_END;
132extern struct page *vmemmap;
239a6425 133
14045ebf 134#define VMEM_MAX_PHYS ((unsigned long) vmemmap)
5fd9c6e2 135
1da177e4
LT		 136/*
137 * A 31 bit pagetable entry of S390 has following format:
138 * | PFRA | | OS |
139 * 0 0IP0
140 * 00000000001111111111222222222233
141 * 01234567890123456789012345678901
142 *
143 * I Page-Invalid Bit: Page is not available for address-translation
144 * P Page-Protection Bit: Store access not possible for page
145 *
146 * A 31 bit segmenttable entry of S390 has following format:
147 * | P-table origin | |PTL
148 * 0 IC
149 * 00000000001111111111222222222233
150 * 01234567890123456789012345678901
151 *
152 * I Segment-Invalid Bit: Segment is not available for address-translation
153 * C Common-Segment Bit: Segment is not private (PoP 3-30)
154 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
155 *
156 * The 31 bit segmenttable origin of S390 has following format:
157 *
158 * |S-table origin | | STL |
159 * X **GPS
160 * 00000000001111111111222222222233
161 * 01234567890123456789012345678901
162 *
163 * X Space-Switch event:
164 * G Segment-Invalid Bit: *
165 * P Private-Space Bit: Segment is not private (PoP 3-30)
166 * S Storage-Alteration:
167 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
168 *
169 * A 64 bit pagetable entry of S390 has following format:
6a985c61 170 * | PFRA |0IPC| OS |
1da177e4
LT		 171 * 0000000000111111111122222222223333333333444444444455555555556666
172 * 0123456789012345678901234567890123456789012345678901234567890123
173 *
174 * I Page-Invalid Bit: Page is not available for address-translation
175 * P Page-Protection Bit: Store access not possible for page
6a985c61 176 * C Change-bit override: HW is not required to set change bit
1da177e4
LT		 177 *
178 * A 64 bit segmenttable entry of S390 has following format:
179 * | P-table origin | TT
180 * 0000000000111111111122222222223333333333444444444455555555556666
181 * 0123456789012345678901234567890123456789012345678901234567890123
182 *
183 * I Segment-Invalid Bit: Segment is not available for address-translation
184 * C Common-Segment Bit: Segment is not private (PoP 3-30)
185 * P Page-Protection Bit: Store access not possible for page
186 * TT Type 00
187 *
188 * A 64 bit region table entry of S390 has following format:
189 * | S-table origin | TF TTTL
190 * 0000000000111111111122222222223333333333444444444455555555556666
191 * 0123456789012345678901234567890123456789012345678901234567890123
192 *
193 * I Segment-Invalid Bit: Segment is not available for address-translation
194 * TT Type 01
195 * TF
190a1d72 196 * TL Table length
1da177e4
LT		 197 *
198 * The 64 bit regiontable origin of S390 has following format:
199 * | region table origon | DTTL
200 * 0000000000111111111122222222223333333333444444444455555555556666
201 * 0123456789012345678901234567890123456789012345678901234567890123
202 *
203 * X Space-Switch event:
204 * G Segment-Invalid Bit:
205 * P Private-Space Bit:
206 * S Storage-Alteration:
207 * R Real space
208 * TL Table-Length:
209 *
210 * A storage key has the following format:
211 * | ACC |F|R|C|0|
212 * 0 3 4 5 6 7
213 * ACC: access key
214 * F : fetch protection bit
215 * R : referenced bit
216 * C : changed bit
217 */
218
219/* Hardware bits in the page table entry */
6a985c61 220#define _PAGE_CO 0x100 /* HW Change-bit override */
83377484
MS		 221#define _PAGE_RO 0x200 /* HW read-only bit */
222#define _PAGE_INVALID 0x400 /* HW invalid bit */
3610cce8
MS		 223
224/* Software bits in the page table entry */
83377484
MS		 225#define _PAGE_SWT 0x001 /* SW pte type bit t */
226#define _PAGE_SWX 0x002 /* SW pte type bit x */
b2fa47e6
MS		 227#define _PAGE_SWC 0x004 /* SW pte changed bit (for KVM) */
228#define _PAGE_SWR 0x008 /* SW pte referenced bit (for KVM) */
229#define _PAGE_SPECIAL 0x010 /* SW associated with special page */
a08cb629 230#define __HAVE_ARCH_PTE_SPECIAL
1da177e4 231
138c9021 232/* Set of bits not changed in pte_modify */
b2fa47e6 233#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_SWC | _PAGE_SWR)
138c9021 234
83377484 235/* Six different types of pages. */
9282ed92
GS		 236#define _PAGE_TYPE_EMPTY 0x400
237#define _PAGE_TYPE_NONE 0x401
83377484
MS		 238#define _PAGE_TYPE_SWAP 0x403
239#define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */
9282ed92
GS		 240#define _PAGE_TYPE_RO 0x200
241#define _PAGE_TYPE_RW 0x000
1da177e4 242
53492b1d
GS		 243/*
244 * Only four types for huge pages, using the invalid bit and protection bit
245 * of a segment table entry.
246 */
247#define _HPAGE_TYPE_EMPTY 0x020 /* _SEGMENT_ENTRY_INV */
248#define _HPAGE_TYPE_NONE 0x220
249#define _HPAGE_TYPE_RO 0x200 /* _SEGMENT_ENTRY_RO */
250#define _HPAGE_TYPE_RW 0x000
251
83377484
MS		 252/*
253 * PTE type bits are rather complicated. handle_pte_fault uses pte_present,
254 * pte_none and pte_file to find out the pte type WITHOUT holding the page
255 * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to
256 * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs
257 * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards.
258 * This change is done while holding the lock, but the intermediate step
259 * of a previously valid pte with the hw invalid bit set can be observed by
260 * handle_pte_fault. That makes it necessary that all valid pte types with
261 * the hw invalid bit set must be distinguishable from the four pte types
262 * empty, none, swap and file.
263 *
264 * irxt ipte irxt
265 * _PAGE_TYPE_EMPTY 1000 -> 1000
266 * _PAGE_TYPE_NONE 1001 -> 1001
267 * _PAGE_TYPE_SWAP 1011 -> 1011
268 * _PAGE_TYPE_FILE 11?1 -> 11?1
269 * _PAGE_TYPE_RO 0100 -> 1100
270 * _PAGE_TYPE_RW 0000 -> 1000
271 *
c1821c2e 272 * pte_none is true for bits combinations 1000, 1010, 1100, 1110
83377484
MS		 273 * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
274 * pte_file is true for bits combinations 1101, 1111
c1821c2e 275 * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid.
83377484
MS		 276 */
277
f4815ac6 278#ifndef CONFIG_64BIT
1da177e4 279
3610cce8
MS		 280/* Bits in the segment table address-space-control-element */
281#define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */
282#define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */
283#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
284#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
285#define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */
1da177e4 286
3610cce8
MS		 287/* Bits in the segment table entry */
288#define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */
80217147 289#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
3610cce8
MS		 290#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
291#define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */
292#define _SEGMENT_ENTRY_PTL 0x0f /* page table length */
1da177e4 293
3610cce8
MS		 294#define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL)
295#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
1da177e4 296
6c61cfe9
MS		 297/* Page status table bits for virtualization */
298#define RCP_ACC_BITS 0xf0000000UL
299#define RCP_FP_BIT 0x08000000UL
300#define RCP_PCL_BIT 0x00800000UL
301#define RCP_HR_BIT 0x00400000UL
302#define RCP_HC_BIT 0x00200000UL
303#define RCP_GR_BIT 0x00040000UL
304#define RCP_GC_BIT 0x00020000UL
305
306/* User dirty / referenced bit for KVM's migration feature */
307#define KVM_UR_BIT 0x00008000UL
308#define KVM_UC_BIT 0x00004000UL
309
f4815ac6 310#else /* CONFIG_64BIT */
1da177e4 311
3610cce8
MS		 312/* Bits in the segment/region table address-space-control-element */
313#define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
314#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
315#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
316#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
317#define _ASCE_REAL_SPACE 0x20 /* real space control */
318#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
319#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
320#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
321#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
322#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
323#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
324
325/* Bits in the region table entry */
326#define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
327#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
328#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
329#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
330#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
331#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
332#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
333
334#define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
335#define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV)
336#define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
337#define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV)
338#define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
339#define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV)
340
1da177e4 341/* Bits in the segment table entry */
3610cce8
MS		 342#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
343#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
344#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
1da177e4 345
3610cce8
MS		 346#define _SEGMENT_ENTRY (0)
347#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
348
53492b1d
GS		 349#define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */
350#define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */
75077afb
GS		 351#define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */
352#define _SEGMENT_ENTRY_SPLIT (1UL << _SEGMENT_ENTRY_SPLIT_BIT)
53492b1d 353
1ae1c1d0
GS		 354/* Set of bits not changed in pmd_modify */
355#define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \
356 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO)
357
6c61cfe9
MS		 358/* Page status table bits for virtualization */
359#define RCP_ACC_BITS 0xf000000000000000UL
360#define RCP_FP_BIT 0x0800000000000000UL
361#define RCP_PCL_BIT 0x0080000000000000UL
362#define RCP_HR_BIT 0x0040000000000000UL
363#define RCP_HC_BIT 0x0020000000000000UL
364#define RCP_GR_BIT 0x0004000000000000UL
365#define RCP_GC_BIT 0x0002000000000000UL
366
367/* User dirty / referenced bit for KVM's migration feature */
368#define KVM_UR_BIT 0x0000800000000000UL
369#define KVM_UC_BIT 0x0000400000000000UL
370
f4815ac6 371#endif /* CONFIG_64BIT */
1da177e4
LT		 372
373/*
3610cce8
MS		 374 * A user page table pointer has the space-switch-event bit, the
375 * private-space-control bit and the storage-alteration-event-control
376 * bit set. A kernel page table pointer doesn't need them.
1da177e4 377 */
3610cce8
MS		 378#define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
379 _ASCE_ALT_EVENT)
1da177e4 380
1da177e4 381/*
9282ed92 382 * Page protection definitions.
1da177e4 383 */
9282ed92
GS		 384#define PAGE_NONE __pgprot(_PAGE_TYPE_NONE)
385#define PAGE_RO __pgprot(_PAGE_TYPE_RO)
386#define PAGE_RW __pgprot(_PAGE_TYPE_RW)
387
388#define PAGE_KERNEL PAGE_RW
389#define PAGE_COPY PAGE_RO
1da177e4
LT		 390
391/*
043d0708
MS		 392 * On s390 the page table entry has an invalid bit and a read-only bit.
393 * Read permission implies execute permission and write permission
394 * implies read permission.
1da177e4
LT		 395 */
396 /*xwr*/
9282ed92
GS		 397#define __P000 PAGE_NONE
398#define __P001 PAGE_RO
399#define __P010 PAGE_RO
400#define __P011 PAGE_RO
043d0708
MS		 401#define __P100 PAGE_RO
402#define __P101 PAGE_RO
403#define __P110 PAGE_RO
404#define __P111 PAGE_RO
9282ed92
GS		 405
406#define __S000 PAGE_NONE
407#define __S001 PAGE_RO
408#define __S010 PAGE_RW
409#define __S011 PAGE_RW
043d0708
MS		 410#define __S100 PAGE_RO
411#define __S101 PAGE_RO
412#define __S110 PAGE_RW
413#define __S111 PAGE_RW
1da177e4 414
b2fa47e6 415static inline int mm_exclusive(struct mm_struct *mm)
1da177e4 416{
b2fa47e6
MS		 417 return likely(mm == current->active_mm &&
418 atomic_read(&mm->context.attach_count) <= 1);
1da177e4 419}
1da177e4 420
b2fa47e6
MS		 421static inline int mm_has_pgste(struct mm_struct *mm)
422{
423#ifdef CONFIG_PGSTE
424 if (unlikely(mm->context.has_pgste))
425 return 1;
426#endif
427 return 0;
428}
1da177e4
LT		 429/*
430 * pgd/pmd/pte query functions
431 */
f4815ac6 432#ifndef CONFIG_64BIT
1da177e4 433
4448aaf0
AB		 434static inline int pgd_present(pgd_t pgd) { return 1; }
435static inline int pgd_none(pgd_t pgd) { return 0; }
436static inline int pgd_bad(pgd_t pgd) { return 0; }
1da177e4 437
190a1d72
MS		 438static inline int pud_present(pud_t pud) { return 1; }
439static inline int pud_none(pud_t pud) { return 0; }
440static inline int pud_bad(pud_t pud) { return 0; }
441
f4815ac6 442#else /* CONFIG_64BIT */
1da177e4 443
5a216a20
MS		 444static inline int pgd_present(pgd_t pgd)
445{
6252d702
MS		 446 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
447 return 1;
5a216a20
MS		 448 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
449}
450
451static inline int pgd_none(pgd_t pgd)
452{
6252d702
MS		 453 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
454 return 0;
5a216a20
MS		 455 return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL;
456}
457
458static inline int pgd_bad(pgd_t pgd)
459{
6252d702
MS		 460 /*
461 * With dynamic page table levels the pgd can be a region table
462 * entry or a segment table entry. Check for the bit that are
463 * invalid for either table entry.
464 */
5a216a20 465 unsigned long mask =
6252d702 466 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
5a216a20
MS		 467 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
468 return (pgd_val(pgd) & mask) != 0;
469}
190a1d72
MS		 470
471static inline int pud_present(pud_t pud)
1da177e4 472{
6252d702
MS		 473 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
474 return 1;
0d017923 475 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
1da177e4
LT		 476}
477
190a1d72 478static inline int pud_none(pud_t pud)
1da177e4 479{
6252d702
MS		 480 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
481 return 0;
0d017923 482 return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL;
1da177e4
LT		 483}
484
190a1d72 485static inline int pud_bad(pud_t pud)
1da177e4 486{
6252d702
MS		 487 /*
488 * With dynamic page table levels the pud can be a region table
489 * entry or a segment table entry. Check for the bit that are
490 * invalid for either table entry.
491 */
5a216a20 492 unsigned long mask =
6252d702 493 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
5a216a20
MS		 494 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
495 return (pud_val(pud) & mask) != 0;
1da177e4
LT		 496}
497
f4815ac6 498#endif /* CONFIG_64BIT */
3610cce8 499
4448aaf0 500static inline int pmd_present(pmd_t pmd)
1da177e4 501{
0d017923 502 return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL;
1da177e4
LT		 503}
504
4448aaf0 505static inline int pmd_none(pmd_t pmd)
1da177e4 506{
0d017923 507 return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL;
1da177e4
LT		 508}
509
378b1e7a
HC		 510static inline int pmd_large(pmd_t pmd)
511{
512#ifdef CONFIG_64BIT
513 return !!(pmd_val(pmd) & _SEGMENT_ENTRY_LARGE);
514#else
515 return 0;
516#endif
517}
518
4448aaf0 519static inline int pmd_bad(pmd_t pmd)
1da177e4 520{
3610cce8
MS		 521 unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV;
522 return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY;
1da177e4
LT		 523}
524
75077afb
GS		 525#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
526extern void pmdp_splitting_flush(struct vm_area_struct *vma,
527 unsigned long addr, pmd_t *pmdp);
528
1ae1c1d0
GS		 529#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
530extern int pmdp_set_access_flags(struct vm_area_struct *vma,
531 unsigned long address, pmd_t *pmdp,
532 pmd_t entry, int dirty);
533
534#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
535extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
536 unsigned long address, pmd_t *pmdp);
537
538#define __HAVE_ARCH_PMD_WRITE
539static inline int pmd_write(pmd_t pmd)
540{
541 return (pmd_val(pmd) & _SEGMENT_ENTRY_RO) == 0;
542}
543
544static inline int pmd_young(pmd_t pmd)
545{
546 return 0;
547}
548
4448aaf0 549static inline int pte_none(pte_t pte)
1da177e4 550{
83377484 551 return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT);
1da177e4
LT		 552}
553
4448aaf0 554static inline int pte_present(pte_t pte)
1da177e4 555{
83377484
MS		 556 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX;
557 return (pte_val(pte) & mask) == _PAGE_TYPE_NONE ||
558 (!(pte_val(pte) & _PAGE_INVALID) &&
559 !(pte_val(pte) & _PAGE_SWT));
1da177e4
LT		 560}
561
4448aaf0 562static inline int pte_file(pte_t pte)
1da177e4 563{
83377484
MS		 564 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT;
565 return (pte_val(pte) & mask) == _PAGE_TYPE_FILE;
1da177e4
LT		 566}
567
7e675137
NP		 568static inline int pte_special(pte_t pte)
569{
a08cb629 570 return (pte_val(pte) & _PAGE_SPECIAL);
7e675137
NP		 571}
572
ba8a9229 573#define __HAVE_ARCH_PTE_SAME
b2fa47e6
MS		 574static inline int pte_same(pte_t a, pte_t b)
575{
576 return pte_val(a) == pte_val(b);
577}
1da177e4 578
b2fa47e6 579static inline pgste_t pgste_get_lock(pte_t *ptep)
5b7baf05 580{
b2fa47e6 581 unsigned long new = 0;
5b7baf05 582#ifdef CONFIG_PGSTE
b2fa47e6
MS		 583 unsigned long old;
584
5b7baf05 585 preempt_disable();
b2fa47e6
MS		 586 asm(
587 " lg %0,%2\n"
588 "0: lgr %1,%0\n"
589 " nihh %0,0xff7f\n" /* clear RCP_PCL_BIT in old */
590 " oihh %1,0x0080\n" /* set RCP_PCL_BIT in new */
591 " csg %0,%1,%2\n"
592 " jl 0b\n"
593 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
594 : "Q" (ptep[PTRS_PER_PTE]) : "cc");
5b7baf05 595#endif
b2fa47e6 596 return __pgste(new);
5b7baf05
CB		 597}
598
b2fa47e6 599static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
5b7baf05
CB		 600{
601#ifdef CONFIG_PGSTE
b2fa47e6
MS		 602 asm(
603 " nihh %1,0xff7f\n" /* clear RCP_PCL_BIT */
604 " stg %1,%0\n"
605 : "=Q" (ptep[PTRS_PER_PTE])
606 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc");
5b7baf05
CB		 607 preempt_enable();
608#endif
609}
610
b2fa47e6 611static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
5b7baf05
CB		 612{
613#ifdef CONFIG_PGSTE
a43a9d93 614 unsigned long address, bits;
b2fa47e6
MS		 615 unsigned char skey;
616
09b53883
MS		 617 if (!pte_present(*ptep))
618 return pgste;
a43a9d93
HC		 619 address = pte_val(*ptep) & PAGE_MASK;
620 skey = page_get_storage_key(address);
b2fa47e6
MS		 621 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
622 /* Clear page changed & referenced bit in the storage key */
7c81878b
CO		 623 if (bits & _PAGE_CHANGED)
624 page_set_storage_key(address, skey ^ bits, 1);
625 else if (bits)
626 page_reset_referenced(address);
b2fa47e6
MS		 627 /* Transfer page changed & referenced bit to guest bits in pgste */
628 pgste_val(pgste) |= bits << 48; /* RCP_GR_BIT & RCP_GC_BIT */
629 /* Get host changed & referenced bits from pgste */
630 bits |= (pgste_val(pgste) & (RCP_HR_BIT | RCP_HC_BIT)) >> 52;
631 /* Clear host bits in pgste. */
632 pgste_val(pgste) &= ~(RCP_HR_BIT | RCP_HC_BIT);
633 pgste_val(pgste) &= ~(RCP_ACC_BITS | RCP_FP_BIT);
634 /* Copy page access key and fetch protection bit to pgste */
635 pgste_val(pgste) |=
636 (unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
637 /* Transfer changed and referenced to kvm user bits */
638 pgste_val(pgste) |= bits << 45; /* KVM_UR_BIT & KVM_UC_BIT */
639 /* Transfer changed & referenced to pte sofware bits */
640 pte_val(*ptep) |= bits << 1; /* _PAGE_SWR & _PAGE_SWC */
641#endif
642 return pgste;
643
644}
645
646static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste)
647{
648#ifdef CONFIG_PGSTE
649 int young;
650
09b53883
MS		 651 if (!pte_present(*ptep))
652 return pgste;
b2fa47e6
MS		 653 young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK);
654 /* Transfer page referenced bit to pte software bit (host view) */
655 if (young || (pgste_val(pgste) & RCP_HR_BIT))
656 pte_val(*ptep) |= _PAGE_SWR;
657 /* Clear host referenced bit in pgste. */
658 pgste_val(pgste) &= ~RCP_HR_BIT;
659 /* Transfer page referenced bit to guest bit in pgste */
660 pgste_val(pgste) |= (unsigned long) young << 50; /* set RCP_GR_BIT */
661#endif
662 return pgste;
663
664}
665
09b53883 666static inline void pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry)
b2fa47e6
MS		 667{
668#ifdef CONFIG_PGSTE
a43a9d93 669 unsigned long address;
b2fa47e6
MS		 670 unsigned long okey, nkey;
671
09b53883
MS		 672 if (!pte_present(entry))
673 return;
674 address = pte_val(entry) & PAGE_MASK;
a43a9d93 675 okey = nkey = page_get_storage_key(address);
b2fa47e6
MS		 676 nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT);
677 /* Set page access key and fetch protection bit from pgste */
678 nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56;
679 if (okey != nkey)
a43a9d93 680 page_set_storage_key(address, nkey, 1);
5b7baf05
CB		 681#endif
682}
683
e5992f2e
MS		 684/**
685 * struct gmap_struct - guest address space
686 * @mm: pointer to the parent mm_struct
687 * @table: pointer to the page directory
480e5926 688 * @asce: address space control element for gmap page table
e5992f2e
MS		 689 * @crst_list: list of all crst tables used in the guest address space
690 */
691struct gmap {
692 struct list_head list;
693 struct mm_struct *mm;
694 unsigned long *table;
480e5926 695 unsigned long asce;
e5992f2e
MS		 696 struct list_head crst_list;
697};
698
699/**
700 * struct gmap_rmap - reverse mapping for segment table entries
701 * @next: pointer to the next gmap_rmap structure in the list
702 * @entry: pointer to a segment table entry
703 */
704struct gmap_rmap {
705 struct list_head list;
706 unsigned long *entry;
707};
708
709/**
710 * struct gmap_pgtable - gmap information attached to a page table
711 * @vmaddr: address of the 1MB segment in the process virtual memory
712 * @mapper: list of segment table entries maping a page table
713 */
714struct gmap_pgtable {
715 unsigned long vmaddr;
716 struct list_head mapper;
717};
718
719struct gmap *gmap_alloc(struct mm_struct *mm);
720void gmap_free(struct gmap *gmap);
721void gmap_enable(struct gmap *gmap);
722void gmap_disable(struct gmap *gmap);
723int gmap_map_segment(struct gmap *gmap, unsigned long from,
724 unsigned long to, unsigned long length);
725int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len);
499069e1 726unsigned long __gmap_fault(unsigned long address, struct gmap *);
e5992f2e 727unsigned long gmap_fault(unsigned long address, struct gmap *);
388186bc 728void gmap_discard(unsigned long from, unsigned long to, struct gmap *);
e5992f2e 729
b2fa47e6
MS		 730/*
731 * Certain architectures need to do special things when PTEs
732 * within a page table are directly modified. Thus, the following
733 * hook is made available.
734 */
735static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
736 pte_t *ptep, pte_t entry)
737{
738 pgste_t pgste;
739
740 if (mm_has_pgste(mm)) {
741 pgste = pgste_get_lock(ptep);
09b53883 742 pgste_set_pte(ptep, pgste, entry);
b2fa47e6
MS		 743 *ptep = entry;
744 pgste_set_unlock(ptep, pgste);
745 } else
746 *ptep = entry;
747}
748
1da177e4
LT		 749/*
750 * query functions pte_write/pte_dirty/pte_young only work if
751 * pte_present() is true. Undefined behaviour if not..
752 */
4448aaf0 753static inline int pte_write(pte_t pte)
1da177e4
LT		 754{
755 return (pte_val(pte) & _PAGE_RO) == 0;
756}
757
4448aaf0 758static inline int pte_dirty(pte_t pte)
1da177e4 759{
b2fa47e6
MS		 760#ifdef CONFIG_PGSTE
761 if (pte_val(pte) & _PAGE_SWC)
762 return 1;
763#endif
1da177e4
LT		 764 return 0;
765}
766
4448aaf0 767static inline int pte_young(pte_t pte)
1da177e4 768{
b2fa47e6
MS		 769#ifdef CONFIG_PGSTE
770 if (pte_val(pte) & _PAGE_SWR)
771 return 1;
772#endif
1da177e4
LT		 773 return 0;
774}
775
1da177e4
LT		 776/*
777 * pgd/pmd/pte modification functions
778 */
779
b2fa47e6 780static inline void pgd_clear(pgd_t *pgd)
5a216a20 781{
f4815ac6 782#ifdef CONFIG_64BIT
6252d702
MS		 783 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
784 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
b2fa47e6 785#endif
5a216a20
MS		 786}
787
b2fa47e6 788static inline void pud_clear(pud_t *pud)
1da177e4 789{
f4815ac6 790#ifdef CONFIG_64BIT
6252d702
MS		 791 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
792 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
b2fa47e6 793#endif
1da177e4
LT		 794}
795
b2fa47e6 796static inline void pmd_clear(pmd_t *pmdp)
1da177e4 797{
3610cce8 798 pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY;
1da177e4
LT		 799}
800
4448aaf0 801static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
1da177e4 802{
9282ed92 803 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1da177e4
LT		 804}
805
806/*
807 * The following pte modification functions only work if
808 * pte_present() is true. Undefined behaviour if not..
809 */
4448aaf0 810static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4 811{
138c9021 812 pte_val(pte) &= _PAGE_CHG_MASK;
1da177e4
LT		 813 pte_val(pte) |= pgprot_val(newprot);
814 return pte;
815}
816
4448aaf0 817static inline pte_t pte_wrprotect(pte_t pte)
1da177e4 818{
9282ed92 819 /* Do not clobber _PAGE_TYPE_NONE pages! */
1da177e4
LT		 820 if (!(pte_val(pte) & _PAGE_INVALID))
821 pte_val(pte) |= _PAGE_RO;
822 return pte;
823}
824
4448aaf0 825static inline pte_t pte_mkwrite(pte_t pte)
1da177e4
LT		 826{
827 pte_val(pte) &= ~_PAGE_RO;
828 return pte;
829}
830
4448aaf0 831static inline pte_t pte_mkclean(pte_t pte)
1da177e4 832{
b2fa47e6
MS		 833#ifdef CONFIG_PGSTE
834 pte_val(pte) &= ~_PAGE_SWC;
835#endif
1da177e4
LT		 836 return pte;
837}
838
4448aaf0 839static inline pte_t pte_mkdirty(pte_t pte)
1da177e4 840{
1da177e4
LT		 841 return pte;
842}
843
4448aaf0 844static inline pte_t pte_mkold(pte_t pte)
1da177e4 845{
b2fa47e6
MS		 846#ifdef CONFIG_PGSTE
847 pte_val(pte) &= ~_PAGE_SWR;
848#endif
1da177e4
LT		 849 return pte;
850}
851
4448aaf0 852static inline pte_t pte_mkyoung(pte_t pte)
1da177e4 853{
1da177e4
LT		 854 return pte;
855}
856
7e675137
NP		 857static inline pte_t pte_mkspecial(pte_t pte)
858{
a08cb629 859 pte_val(pte) |= _PAGE_SPECIAL;
7e675137
NP		 860 return pte;
861}
862
84afdcee
HC		 863#ifdef CONFIG_HUGETLB_PAGE
864static inline pte_t pte_mkhuge(pte_t pte)
865{
866 /*
867 * PROT_NONE needs to be remapped from the pte type to the ste type.
868 * The HW invalid bit is also different for pte and ste. The pte
869 * invalid bit happens to be the same as the ste _SEGMENT_ENTRY_LARGE
870 * bit, so we don't have to clear it.
871 */
872 if (pte_val(pte) & _PAGE_INVALID) {
873 if (pte_val(pte) & _PAGE_SWT)
874 pte_val(pte) |= _HPAGE_TYPE_NONE;
875 pte_val(pte) |= _SEGMENT_ENTRY_INV;
876 }
877 /*
878 * Clear SW pte bits SWT and SWX, there are no SW bits in a segment
879 * table entry.
880 */
881 pte_val(pte) &= ~(_PAGE_SWT | _PAGE_SWX);
882 /*
883 * Also set the change-override bit because we don't need dirty bit
884 * tracking for hugetlbfs pages.
885 */
886 pte_val(pte) |= (_SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_CO);
887 return pte;
888}
889#endif
890
15e86b0c 891/*
b2fa47e6 892 * Get (and clear) the user dirty bit for a pte.
15e86b0c 893 */
b2fa47e6
MS		 894static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
895 pte_t *ptep)
15e86b0c 896{
b2fa47e6
MS		 897 pgste_t pgste;
898 int dirty = 0;
899
900 if (mm_has_pgste(mm)) {
901 pgste = pgste_get_lock(ptep);
902 pgste = pgste_update_all(ptep, pgste);
903 dirty = !!(pgste_val(pgste) & KVM_UC_BIT);
904 pgste_val(pgste) &= ~KVM_UC_BIT;
905 pgste_set_unlock(ptep, pgste);
906 return dirty;
15e86b0c 907 }
15e86b0c
FF		 908 return dirty;
909}
b2fa47e6
MS		 910
911/*
912 * Get (and clear) the user referenced bit for a pte.
913 */
914static inline int ptep_test_and_clear_user_young(struct mm_struct *mm,
915 pte_t *ptep)
916{
917 pgste_t pgste;
918 int young = 0;
919
920 if (mm_has_pgste(mm)) {
921 pgste = pgste_get_lock(ptep);
922 pgste = pgste_update_young(ptep, pgste);
923 young = !!(pgste_val(pgste) & KVM_UR_BIT);
924 pgste_val(pgste) &= ~KVM_UR_BIT;
925 pgste_set_unlock(ptep, pgste);
926 }
927 return young;
928}
15e86b0c 929
ba8a9229
MS		 930#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
931static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
932 unsigned long addr, pte_t *ptep)
1da177e4 933{
b2fa47e6
MS		 934 pgste_t pgste;
935 pte_t pte;
936
937 if (mm_has_pgste(vma->vm_mm)) {
938 pgste = pgste_get_lock(ptep);
939 pgste = pgste_update_young(ptep, pgste);
940 pte = *ptep;
941 *ptep = pte_mkold(pte);
942 pgste_set_unlock(ptep, pgste);
943 return pte_young(pte);
944 }
1da177e4
LT		 945 return 0;
946}
947
ba8a9229
MS		 948#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
949static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
950 unsigned long address, pte_t *ptep)
1da177e4 951{
5b7baf05
CB		 952 /* No need to flush TLB
953 * On s390 reference bits are in storage key and never in TLB
954 * With virtualization we handle the reference bit, without we
955 * we can simply return */
5b7baf05 956 return ptep_test_and_clear_young(vma, address, ptep);
1da177e4
LT		 957}
958
9282ed92 959static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
1da177e4 960{
9282ed92 961 if (!(pte_val(*ptep) & _PAGE_INVALID)) {
f4815ac6 962#ifndef CONFIG_64BIT
146e4b3c 963 /* pto must point to the start of the segment table */
1da177e4 964 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
9282ed92
GS		 965#else
966 /* ipte in zarch mode can do the math */
967 pte_t *pto = ptep;
968#endif
94c12cc7
MS		 969 asm volatile(
970 " ipte %2,%3"
971 : "=m" (*ptep) : "m" (*ptep),
972 "a" (pto), "a" (address));
1da177e4 973 }
9282ed92
GS		 974}
975
ba8a9229
MS		 976/*
977 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
978 * both clear the TLB for the unmapped pte. The reason is that
979 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
980 * to modify an active pte. The sequence is
981 * 1) ptep_get_and_clear
982 * 2) set_pte_at
983 * 3) flush_tlb_range
984 * On s390 the tlb needs to get flushed with the modification of the pte
985 * if the pte is active. The only way how this can be implemented is to
986 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
987 * is a nop.
988 */
989#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
b2fa47e6
MS		 990static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
991 unsigned long address, pte_t *ptep)
992{
993 pgste_t pgste;
994 pte_t pte;
995
996 mm->context.flush_mm = 1;
997 if (mm_has_pgste(mm))
998 pgste = pgste_get_lock(ptep);
999
1000 pte = *ptep;
1001 if (!mm_exclusive(mm))
1002 __ptep_ipte(address, ptep);
1003 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1004
1005 if (mm_has_pgste(mm)) {
1006 pgste = pgste_update_all(&pte, pgste);
1007 pgste_set_unlock(ptep, pgste);
1008 }
1009 return pte;
1010}
1011
1012#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1013static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
1014 unsigned long address,
1015 pte_t *ptep)
1016{
1017 pte_t pte;
1018
1019 mm->context.flush_mm = 1;
1020 if (mm_has_pgste(mm))
1021 pgste_get_lock(ptep);
1022
1023 pte = *ptep;
1024 if (!mm_exclusive(mm))
1025 __ptep_ipte(address, ptep);
1026 return pte;
1027}
1028
1029static inline void ptep_modify_prot_commit(struct mm_struct *mm,
1030 unsigned long address,
1031 pte_t *ptep, pte_t pte)
1032{
1033 *ptep = pte;
1034 if (mm_has_pgste(mm))
1035 pgste_set_unlock(ptep, *(pgste_t *)(ptep + PTRS_PER_PTE));
1036}
ba8a9229
MS		 1037
1038#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
f0e47c22
MS		 1039static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
1040 unsigned long address, pte_t *ptep)
1041{
b2fa47e6
MS		 1042 pgste_t pgste;
1043 pte_t pte;
1044
1045 if (mm_has_pgste(vma->vm_mm))
1046 pgste = pgste_get_lock(ptep);
1047
1048 pte = *ptep;
1049 __ptep_ipte(address, ptep);
1050 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1051
1052 if (mm_has_pgste(vma->vm_mm)) {
1053 pgste = pgste_update_all(&pte, pgste);
1054 pgste_set_unlock(ptep, pgste);
1055 }
1da177e4
LT		 1056 return pte;
1057}
1058
ba8a9229
MS		 1059/*
1060 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1061 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1062 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1063 * cannot be accessed while the batched unmap is running. In this case
1064 * full==1 and a simple pte_clear is enough. See tlb.h.
1065 */
1066#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1067static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
b2fa47e6 1068 unsigned long address,
ba8a9229 1069 pte_t *ptep, int full)
1da177e4 1070{
b2fa47e6
MS		 1071 pgste_t pgste;
1072 pte_t pte;
1073
1074 if (mm_has_pgste(mm))
1075 pgste = pgste_get_lock(ptep);
ba8a9229 1076
b2fa47e6
MS		 1077 pte = *ptep;
1078 if (!full)
1079 __ptep_ipte(address, ptep);
1080 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1081
1082 if (mm_has_pgste(mm)) {
1083 pgste = pgste_update_all(&pte, pgste);
1084 pgste_set_unlock(ptep, pgste);
1085 }
ba8a9229 1086 return pte;
1da177e4
LT		 1087}
1088
ba8a9229 1089#define __HAVE_ARCH_PTEP_SET_WRPROTECT
b2fa47e6
MS		 1090static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
1091 unsigned long address, pte_t *ptep)
1092{
1093 pgste_t pgste;
1094 pte_t pte = *ptep;
1095
1096 if (pte_write(pte)) {
1097 mm->context.flush_mm = 1;
1098 if (mm_has_pgste(mm))
1099 pgste = pgste_get_lock(ptep);
1100
1101 if (!mm_exclusive(mm))
1102 __ptep_ipte(address, ptep);
1103 *ptep = pte_wrprotect(pte);
1104
1105 if (mm_has_pgste(mm))
1106 pgste_set_unlock(ptep, pgste);
1107 }
1108 return pte;
1109}
ba8a9229
MS		 1110
1111#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
b2fa47e6
MS		 1112static inline int ptep_set_access_flags(struct vm_area_struct *vma,
1113 unsigned long address, pte_t *ptep,
1114 pte_t entry, int dirty)
1115{
1116 pgste_t pgste;
1117
1118 if (pte_same(*ptep, entry))
1119 return 0;
1120 if (mm_has_pgste(vma->vm_mm))
1121 pgste = pgste_get_lock(ptep);
1122
1123 __ptep_ipte(address, ptep);
1124 *ptep = entry;
1125
1126 if (mm_has_pgste(vma->vm_mm))
1127 pgste_set_unlock(ptep, pgste);
1128 return 1;
1129}
1da177e4 1130
1da177e4
LT		 1131/*
1132 * Conversion functions: convert a page and protection to a page entry,
1133 * and a page entry and page directory to the page they refer to.
1134 */
1135static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1136{
1137 pte_t __pte;
1138 pte_val(__pte) = physpage + pgprot_val(pgprot);
1139 return __pte;
1140}
1141
2dcea57a
HC		 1142static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
1143{
0b2b6e1d 1144 unsigned long physpage = page_to_phys(page);
1da177e4 1145
2dcea57a
HC		 1146 return mk_pte_phys(physpage, pgprot);
1147}
1148
190a1d72
MS		 1149#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1150#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1151#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1152#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
1da177e4 1153
190a1d72
MS		 1154#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
1155#define pgd_offset_k(address) pgd_offset(&init_mm, address)
1da177e4 1156
f4815ac6 1157#ifndef CONFIG_64BIT
1da177e4 1158
190a1d72
MS		 1159#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1160#define pud_deref(pmd) ({ BUG(); 0UL; })
1161#define pgd_deref(pmd) ({ BUG(); 0UL; })
46a82b2d 1162
190a1d72
MS		 1163#define pud_offset(pgd, address) ((pud_t *) pgd)
1164#define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
1da177e4 1165
f4815ac6 1166#else /* CONFIG_64BIT */
1da177e4 1167
190a1d72
MS		 1168#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1169#define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
5a216a20 1170#define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
1da177e4 1171
5a216a20
MS		 1172static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
1173{
6252d702
MS		 1174 pud_t *pud = (pud_t *) pgd;
1175 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
1176 pud = (pud_t *) pgd_deref(*pgd);
5a216a20
MS		 1177 return pud + pud_index(address);
1178}
1da177e4 1179
190a1d72 1180static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
1da177e4 1181{
6252d702
MS		 1182 pmd_t *pmd = (pmd_t *) pud;
1183 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
1184 pmd = (pmd_t *) pud_deref(*pud);
190a1d72 1185 return pmd + pmd_index(address);
1da177e4
LT		 1186}
1187
f4815ac6 1188#endif /* CONFIG_64BIT */
1da177e4 1189
190a1d72
MS		 1190#define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
1191#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1192#define pte_page(x) pfn_to_page(pte_pfn(x))
1da177e4 1193
190a1d72 1194#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
1da177e4 1195
190a1d72
MS		 1196/* Find an entry in the lowest level page table.. */
1197#define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
1198#define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1da177e4 1199#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1da177e4 1200#define pte_unmap(pte) do { } while (0)
1da177e4 1201
1ae1c1d0
GS		 1202static inline void __pmd_idte(unsigned long address, pmd_t *pmdp)
1203{
1204 unsigned long sto = (unsigned long) pmdp -
1205 pmd_index(address) * sizeof(pmd_t);
1206
1207 if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INV)) {
1208 asm volatile(
1209 " .insn rrf,0xb98e0000,%2,%3,0,0"
1210 : "=m" (*pmdp)
1211 : "m" (*pmdp), "a" (sto),
1212 "a" ((address & HPAGE_MASK))
1213 : "cc"
1214 );
1215 }
1216}
1217
75077afb 1218#ifdef CONFIG_TRANSPARENT_HUGEPAGE
9501d09f
GS		 1219#define __HAVE_ARCH_PGTABLE_DEPOSIT
1220extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable);
1221
1222#define __HAVE_ARCH_PGTABLE_WITHDRAW
1223extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm);
1224
75077afb
GS		 1225static inline int pmd_trans_splitting(pmd_t pmd)
1226{
1227 return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT;
1228}
1ae1c1d0
GS		 1229
1230static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1231 pmd_t *pmdp, pmd_t entry)
1232{
1233 *pmdp = entry;
1234}
1235
1236static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
1237{
1238 unsigned long pgprot_pmd = 0;
1239
1240 if (pgprot_val(pgprot) & _PAGE_INVALID) {
1241 if (pgprot_val(pgprot) & _PAGE_SWT)
1242 pgprot_pmd |= _HPAGE_TYPE_NONE;
1243 pgprot_pmd |= _SEGMENT_ENTRY_INV;
1244 }
1245 if (pgprot_val(pgprot) & _PAGE_RO)
1246 pgprot_pmd |= _SEGMENT_ENTRY_RO;
1247 return pgprot_pmd;
1248}
1249
1250static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
1251{
1252 pmd_val(pmd) &= _SEGMENT_CHG_MASK;
1253 pmd_val(pmd) |= massage_pgprot_pmd(newprot);
1254 return pmd;
1255}
1256
1257static inline pmd_t pmd_mkhuge(pmd_t pmd)
1258{
1259 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE;
1260 return pmd;
1261}
1262
1263static inline pmd_t pmd_mkwrite(pmd_t pmd)
1264{
1265 pmd_val(pmd) &= ~_SEGMENT_ENTRY_RO;
1266 return pmd;
1267}
1268
1269static inline pmd_t pmd_wrprotect(pmd_t pmd)
1270{
1271 pmd_val(pmd) |= _SEGMENT_ENTRY_RO;
1272 return pmd;
1273}
1274
1275static inline pmd_t pmd_mkdirty(pmd_t pmd)
1276{
1277 /* No dirty bit in the segment table entry. */
1278 return pmd;
1279}
1280
1281static inline pmd_t pmd_mkold(pmd_t pmd)
1282{
1283 /* No referenced bit in the segment table entry. */
1284 return pmd;
1285}
1286
1287static inline pmd_t pmd_mkyoung(pmd_t pmd)
1288{
1289 /* No referenced bit in the segment table entry. */
1290 return pmd;
1291}
1292
1293#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1294static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1295 unsigned long address, pmd_t *pmdp)
1296{
1297 unsigned long pmd_addr = pmd_val(*pmdp) & HPAGE_MASK;
1298 long tmp, rc;
1299 int counter;
1300
1301 rc = 0;
1302 if (MACHINE_HAS_RRBM) {
1303 counter = PTRS_PER_PTE >> 6;
1304 asm volatile(
1305 "0: .insn rre,0xb9ae0000,%0,%3\n" /* rrbm */
1306 " ogr %1,%0\n"
1307 " la %3,0(%4,%3)\n"
1308 " brct %2,0b\n"
1309 : "=&d" (tmp), "+&d" (rc), "+d" (counter),
1310 "+a" (pmd_addr)
1311 : "a" (64 * 4096UL) : "cc");
1312 rc = !!rc;
1313 } else {
1314 counter = PTRS_PER_PTE;
1315 asm volatile(
1316 "0: rrbe 0,%2\n"
1317 " la %2,0(%3,%2)\n"
1318 " brc 12,1f\n"
1319 " lhi %0,1\n"
1320 "1: brct %1,0b\n"
1321 : "+d" (rc), "+d" (counter), "+a" (pmd_addr)
1322 : "a" (4096UL) : "cc");
1323 }
1324 return rc;
1325}
1326
1327#define __HAVE_ARCH_PMDP_GET_AND_CLEAR
1328static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
1329 unsigned long address, pmd_t *pmdp)
1330{
1331 pmd_t pmd = *pmdp;
1332
1333 __pmd_idte(address, pmdp);
1334 pmd_clear(pmdp);
1335 return pmd;
1336}
1337
1338#define __HAVE_ARCH_PMDP_CLEAR_FLUSH
1339static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma,
1340 unsigned long address, pmd_t *pmdp)
1341{
1342 return pmdp_get_and_clear(vma->vm_mm, address, pmdp);
1343}
1344
1345#define __HAVE_ARCH_PMDP_INVALIDATE
1346static inline void pmdp_invalidate(struct vm_area_struct *vma,
1347 unsigned long address, pmd_t *pmdp)
1348{
1349 __pmd_idte(address, pmdp);
1350}
1351
1352static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
1353{
1354 pmd_t __pmd;
1355 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot);
1356 return __pmd;
1357}
1358
1359#define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot))
1360#define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
1361
1362static inline int pmd_trans_huge(pmd_t pmd)
1363{
1364 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE;
1365}
1366
1367static inline int has_transparent_hugepage(void)
1368{
1369 return MACHINE_HAS_HPAGE ? 1 : 0;
1370}
1371
1372static inline unsigned long pmd_pfn(pmd_t pmd)
1373{
1374 if (pmd_trans_huge(pmd))
1375 return pmd_val(pmd) >> HPAGE_SHIFT;
1376 else
1377 return pmd_val(pmd) >> PAGE_SHIFT;
1378}
75077afb
GS		 1379#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1380
1da177e4
LT		 1381/*
1382 * 31 bit swap entry format:
1383 * A page-table entry has some bits we have to treat in a special way.
1384 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
1385 * exception will occur instead of a page translation exception. The
1386 * specifiation exception has the bad habit not to store necessary
1387 * information in the lowcore.
1388 * Bit 21 and bit 22 are the page invalid bit and the page protection
1389 * bit. We set both to indicate a swapped page.
1390 * Bit 30 and 31 are used to distinguish the different page types. For
1391 * a swapped page these bits need to be zero.
1392 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
1393 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
1394 * plus 24 for the offset.
1395 * 0| offset |0110|o|type |00|
1396 * 0 0000000001111111111 2222 2 22222 33
1397 * 0 1234567890123456789 0123 4 56789 01
1398 *
1399 * 64 bit swap entry format:
1400 * A page-table entry has some bits we have to treat in a special way.
1401 * Bits 52 and bit 55 have to be zero, otherwise an specification
1402 * exception will occur instead of a page translation exception. The
1403 * specifiation exception has the bad habit not to store necessary
1404 * information in the lowcore.
1405 * Bit 53 and bit 54 are the page invalid bit and the page protection
1406 * bit. We set both to indicate a swapped page.
1407 * Bit 62 and 63 are used to distinguish the different page types. For
1408 * a swapped page these bits need to be zero.
1409 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
1410 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
1411 * plus 56 for the offset.
1412 * | offset |0110|o|type |00|
1413 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
1414 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
1415 */
f4815ac6 1416#ifndef CONFIG_64BIT
1da177e4
LT		 1417#define __SWP_OFFSET_MASK (~0UL >> 12)
1418#else
1419#define __SWP_OFFSET_MASK (~0UL >> 11)
1420#endif
4448aaf0 1421static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1da177e4
LT		 1422{
1423 pte_t pte;
1424 offset &= __SWP_OFFSET_MASK;
9282ed92 1425 pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) |
1da177e4
LT		 1426 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
1427 return pte;
1428}
1429
1430#define __swp_type(entry) (((entry).val >> 2) & 0x1f)
1431#define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
1432#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
1433
1434#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1435#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1436
f4815ac6 1437#ifndef CONFIG_64BIT
1da177e4 1438# define PTE_FILE_MAX_BITS 26
f4815ac6 1439#else /* CONFIG_64BIT */
1da177e4 1440# define PTE_FILE_MAX_BITS 59
f4815ac6 1441#endif /* CONFIG_64BIT */
1da177e4
LT		 1442
1443#define pte_to_pgoff(__pte) \
1444 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
1445
1446#define pgoff_to_pte(__off) \
1447 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
9282ed92 1448 | _PAGE_TYPE_FILE })
1da177e4
LT		 1449
1450#endif /* !__ASSEMBLY__ */
1451
1452#define kern_addr_valid(addr) (1)
1453
17f34580
HC		 1454extern int vmem_add_mapping(unsigned long start, unsigned long size);
1455extern int vmem_remove_mapping(unsigned long start, unsigned long size);
402b0862 1456extern int s390_enable_sie(void);
f4eb07c1 1457
1da177e4
LT		 1458/*
1459 * No page table caches to initialise
1460 */
1461#define pgtable_cache_init() do { } while (0)
1462
1da177e4
LT		 1463#include <asm-generic/pgtable.h>
1464
1465#endif /* _S390_PAGE_H */
Linux 6.x block layer and io_uring tree(s)