projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| a0616cde DH |
2 | /* |
| 3 | * Copyright IBM Corp. 1999, 2009 | |
| 4 | * | |
| 5 | * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> | |
| 6 | */ | |
| 7 | ||
| 8 | #ifndef __ASM_BARRIER_H | |
| 9 | #define __ASM_BARRIER_H | |
| 10 | ||
| 11 | /* | |
| 12 | * Force strict CPU ordering. | |
| 13 | * And yes, this is required on UP too when we're talking | |
| 14 | * to devices. | |
| a0616cde DH |
15 | */ |
| 16 | ||
| e5b8d755 | 17 | #ifdef CONFIG_HAVE_MARCH_Z196_FEATURES |
| e06ef372 | 18 | /* Fast-BCR without checkpoint synchronization */ |
| 44230282 | 19 | #define __ASM_BARRIER "bcr 14,0\n" |
| e5b8d755 | 20 | #else |
| 44230282 | 21 | #define __ASM_BARRIER "bcr 15,0\n" |
| e5b8d755 | 22 | #endif |
| c6f48b0b | 23 | |
| 44230282 HC |
24 | #define mb() do { asm volatile(__ASM_BARRIER : : : "memory"); } while (0) |
| 25 | ||
| 1afc82ae CB |
26 | #define rmb() barrier() |
| 27 | #define wmb() barrier() | |
| 28 | #define dma_rmb() mb() | |
| 29 | #define dma_wmb() mb() | |
| 82b44496 MT |
30 | #define __smp_mb() mb() |
| 31 | #define __smp_rmb() rmb() | |
| 32 | #define __smp_wmb() wmb() | |
| 82b44496 MT |
33 | |
| 34 | #define __smp_store_release(p, v) \ | |
| 47933ad4 PZ |
35 | do { \ |
| 36 | compiletime_assert_atomic_type(*p); \ | |
| 37 | barrier(); \ | |
| 76695af2 | 38 | WRITE_ONCE(*p, v); \ |
| 47933ad4 PZ |
39 | } while (0) |
| 40 | ||
| 82b44496 | 41 | #define __smp_load_acquire(p) \ |
| 47933ad4 | 42 | ({ \ |
| 76695af2 | 43 | typeof(*p) ___p1 = READ_ONCE(*p); \ |
| 47933ad4 PZ |
44 | compiletime_assert_atomic_type(*p); \ |
| 45 | barrier(); \ | |
| 46 | ___p1; \ | |
| 47 | }) | |
| 48 | ||
| 779a6a36 MT |
49 | #define __smp_mb__before_atomic() barrier() |
| 50 | #define __smp_mb__after_atomic() barrier() | |
| 51 | ||
| 21535aae MT |
52 | #include <asm-generic/barrier.h> |
| 53 | ||
| a0616cde | 54 | #endif /* __ASM_BARRIER_H */ |