[linux-block.git] / arch / ppc64 / kernel / cpu_setup_power4.S

/*
 * This file contains low level CPU setup functions.
 *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 */

#include <linux/config.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/ppc_asm.h>
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
#include <asm/offsets.h>
#include <asm/cache.h>

_GLOBAL(__970_cpu_preinit)
	/*
	 * Do nothing if not running in HV mode
	 */
	mfmsr	r0
	rldicl.	r0,r0,4,63
	beqlr

	/*
	 * Deal only with PPC970 and PPC970FX.
	 */
	mfspr	r0,SPRN_PVR
	srwi	r0,r0,16
	cmpwi	cr0,r0,0x39
	cmpwi	cr1,r0,0x3c
	cror	4*cr0+eq,4*cr0+eq,4*cr1+eq
	bnelr

	/* Make sure HID4:rm_ci is off before MMU is turned off, that large
	 * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
	 * HID5:DCBZ32_ill
	 */
	li	r0,0
	mfspr	r3,SPRN_HID4
	rldimi	r3,r0,40,23	/* clear bit 23 (rm_ci) */
	rldimi	r3,r0,2,61	/* clear bit 61 (lg_pg_en) */
	sync
	mtspr	SPRN_HID4,r3
	isync
	sync
	mfspr	r3,SPRN_HID5
	rldimi	r3,r0,6,56	/* clear bits 56 & 57 (DCBZ*) */
	sync
	mtspr	SPRN_HID5,r3
	isync
	sync

	/* Setup some basic HID1 features */
	mfspr	r0,SPRN_HID1
	li	r3,0x1200		/* enable i-fetch cacheability */
	sldi	r3,r3,44		/* and prefetch */
	or	r0,r0,r3
	mtspr	SPRN_HID1,r0
	mtspr	SPRN_HID1,r0
	isync

	/* Clear HIOR */
	li	r0,0
	sync
	mtspr	SPRN_HIOR,0		/* Clear interrupt prefix */
	isync
	blr

_GLOBAL(__setup_cpu_power4)
	blr

_GLOBAL(__setup_cpu_be)
        /* Set large page sizes LP=0: 16MB, LP=1: 64KB */
        addi    r3, 0,  0
        ori     r3, r3, HID6_LB
        sldi    r3, r3, 32
        nor     r3, r3, r3
        mfspr   r4, SPRN_HID6
        and     r4, r4, r3
        addi    r3, 0, 0x02000
        sldi    r3, r3, 32
        or      r4, r4, r3
        mtspr   SPRN_HID6, r4
	blr

_GLOBAL(__setup_cpu_ppc970)
	mfspr	r0,SPRN_HID0
	li	r11,5			/* clear DOZE and SLEEP */
	rldimi	r0,r11,52,8		/* set NAP and DPM */
	mtspr	SPRN_HID0,r0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	sync
	isync
	blr

/* Definitions for the table use to save CPU states */
#define CS_HID0		0
#define CS_HID1		8
#define	CS_HID4		16
#define CS_HID5		24
#define CS_SIZE		32

	.data
	.balign	L1_CACHE_BYTES,0
cpu_state_storage:	
	.space	CS_SIZE
	.balign	L1_CACHE_BYTES,0
	.text
	
/* Called in normal context to backup CPU 0 state. This
 * does not include cache settings. This function is also
 * called for machine sleep. This does not include the MMU
 * setup, BATs, etc... but rather the "special" registers
 * like HID0, HID1, HID4, etc...
 */
_GLOBAL(__save_cpu_setup)
	/* Some CR fields are volatile, we back it up all */
	mfcr	r7

	/* Get storage ptr */
	LOADADDR(r5,cpu_state_storage)

	/* We only deal with 970 for now */
	mfspr	r0,SPRN_PVR
	srwi	r0,r0,16
	cmpwi	cr0,r0,0x39
	cmpwi	cr1,r0,0x3c
	cror	4*cr0+eq,4*cr0+eq,4*cr1+eq
	bne	1f

	/* Save HID0,1,4 and 5 */
	mfspr	r3,SPRN_HID0
	std	r3,CS_HID0(r5)
	mfspr	r3,SPRN_HID1
	std	r3,CS_HID1(r5)
	mfspr	r3,SPRN_HID4
	std	r3,CS_HID4(r5)
	mfspr	r3,SPRN_HID5
	std	r3,CS_HID5(r5)
	
1:
	mtcr	r7
	blr

/* Called with no MMU context (typically MSR:IR/DR off) to
 * restore CPU state as backed up by the previous
 * function. This does not include cache setting
 */
_GLOBAL(__restore_cpu_setup)
	/* Get storage ptr (FIXME when using anton reloc as we
	 * are running with translation disabled here
	 */
	LOADADDR(r5,cpu_state_storage)

	/* We only deal with 970 for now */
	mfspr	r0,SPRN_PVR
	srwi	r0,r0,16
	cmpwi	cr0,r0,0x39
	cmpwi	cr1,r0,0x3c
	cror	4*cr0+eq,4*cr0+eq,4*cr1+eq
	bne	1f

	/* Before accessing memory, we make sure rm_ci is clear */
	li	r0,0
	mfspr	r3,SPRN_HID4
	rldimi	r3,r0,40,23	/* clear bit 23 (rm_ci) */
	sync
	mtspr	SPRN_HID4,r3
	isync
	sync

	/* Clear interrupt prefix */
	li	r0,0
	sync
	mtspr	SPRN_HIOR,0
	isync

	/* Restore HID0 */
	ld	r3,CS_HID0(r5)
	sync
	isync
	mtspr	SPRN_HID0,r3
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	sync
	isync

	/* Restore HID1 */
	ld	r3,CS_HID1(r5)
	sync
	isync
	mtspr	SPRN_HID1,r3
	mtspr	SPRN_HID1,r3
	sync
	isync
	
	/* Restore HID4 */
	ld	r3,CS_HID4(r5)
	sync
	isync
	mtspr	SPRN_HID4,r3
	sync
	isync

	/* Restore HID5 */
	ld	r3,CS_HID5(r5)
	sync
	isync
	mtspr	SPRN_HID5,r3
	sync
	isync
1:
	blr
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file contains low level CPU setup functions.
	3	* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*
	10	*/
	11
	12	#include <linux/config.h>
	13	#include <asm/processor.h>
	14	#include <asm/page.h>
	15	#include <asm/ppc_asm.h>
	16	#include <asm/cputable.h>
	17	#include <asm/ppc_asm.h>
	18	#include <asm/offsets.h>
	19	#include <asm/cache.h>
	20
	21	_GLOBAL(__970_cpu_preinit)
	22	/*
	23	* Do nothing if not running in HV mode
	24	*/
	25	mfmsr r0
	26	rldicl. r0,r0,4,63
	27	beqlr
	28
	29	/*
	30	* Deal only with PPC970 and PPC970FX.
	31	*/
	32	mfspr r0,SPRN_PVR
	33	srwi r0,r0,16
	34	cmpwi cr0,r0,0x39
	35	cmpwi cr1,r0,0x3c
	36	cror 4cr0+eq,4cr0+eq,4*cr1+eq
	37	bnelr
	38
	39	/* Make sure HID4:rm_ci is off before MMU is turned off, that large
	40	* pages are enabled with HID4:61 and clear HID5:DCBZ_size and
	41	* HID5:DCBZ32_ill
	42	*/
	43	li r0,0
	44	mfspr r3,SPRN_HID4
	45	rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
	46	rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
	47	sync
	48	mtspr SPRN_HID4,r3
	49	isync
	50	sync
	51	mfspr r3,SPRN_HID5
	52	rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ) /
	53	sync
	54	mtspr SPRN_HID5,r3
	55	isync
	56	sync
	57
	58	/* Setup some basic HID1 features */
	59	mfspr r0,SPRN_HID1
	60	li r3,0x1200 /* enable i-fetch cacheability */
	61	sldi r3,r3,44 /* and prefetch */
	62	or r0,r0,r3
	63	mtspr SPRN_HID1,r0
	64	mtspr SPRN_HID1,r0
65	isync
66
67	/* Clear HIOR */
68	li r0,0
69	sync
70	mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
71	isync
72	blr
73
74	_GLOBAL(__setup_cpu_power4)
75	blr
fef1c772 AB	76
	77	_GLOBAL(__setup_cpu_be)
	78	/* Set large page sizes LP=0: 16MB, LP=1: 64KB */
	79	addi r3, 0, 0
	80	ori r3, r3, HID6_LB
	81	sldi r3, r3, 32
	82	nor r3, r3, r3
	83	mfspr r4, SPRN_HID6
	84	and r4, r4, r3
	85	addi r3, 0, 0x02000
	86	sldi r3, r3, 32
	87	or r4, r4, r3
	88	mtspr SPRN_HID6, r4
	89	blr
	90
1da177e4 LT	91	_GLOBAL(__setup_cpu_ppc970)
	92	mfspr r0,SPRN_HID0
	93	li r11,5 /* clear DOZE and SLEEP */
	94	rldimi r0,r11,52,8 /* set NAP and DPM */
	95	mtspr SPRN_HID0,r0
	96	mfspr r0,SPRN_HID0
	97	mfspr r0,SPRN_HID0
	98	mfspr r0,SPRN_HID0
	99	mfspr r0,SPRN_HID0
	100	mfspr r0,SPRN_HID0
	101	mfspr r0,SPRN_HID0
	102	sync
	103	isync
	104	blr
	105
	106	/* Definitions for the table use to save CPU states */
	107	#define CS_HID0 0
	108	#define CS_HID1 8
	109	#define CS_HID4 16
	110	#define CS_HID5 24
	111	#define CS_SIZE 32
	112
	113	.data
	114	.balign L1_CACHE_BYTES,0
	115	cpu_state_storage:
	116	.space CS_SIZE
	117	.balign L1_CACHE_BYTES,0
	118	.text
	119
	120	/* Called in normal context to backup CPU 0 state. This
	121	* does not include cache settings. This function is also
	122	* called for machine sleep. This does not include the MMU
	123	* setup, BATs, etc... but rather the "special" registers
	124	* like HID0, HID1, HID4, etc...
	125	*/
	126	_GLOBAL(__save_cpu_setup)
	127	/* Some CR fields are volatile, we back it up all */
	128	mfcr r7
	129
	130	/* Get storage ptr */
	131	LOADADDR(r5,cpu_state_storage)
	132
	133	/* We only deal with 970 for now */
	134	mfspr r0,SPRN_PVR
	135	srwi r0,r0,16
	136	cmpwi cr0,r0,0x39
	137	cmpwi cr1,r0,0x3c
	138	cror 4cr0+eq,4cr0+eq,4*cr1+eq
	139	bne 1f
	140
	141	/* Save HID0,1,4 and 5 */
	142	mfspr r3,SPRN_HID0
	143	std r3,CS_HID0(r5)
	144	mfspr r3,SPRN_HID1
	145	std r3,CS_HID1(r5)
	146	mfspr r3,SPRN_HID4
	147	std r3,CS_HID4(r5)
	148	mfspr r3,SPRN_HID5
	149	std r3,CS_HID5(r5)
	150
	151	1:
	152	mtcr r7
	153	blr
	154
155	/* Called with no MMU context (typically MSR:IR/DR off) to
156	* restore CPU state as backed up by the previous
157	* function. This does not include cache setting
158	*/
159	_GLOBAL(__restore_cpu_setup)
160	/* Get storage ptr (FIXME when using anton reloc as we
161	* are running with translation disabled here
162	*/
163	LOADADDR(r5,cpu_state_storage)
164
165	/* We only deal with 970 for now */
166	mfspr r0,SPRN_PVR
167	srwi r0,r0,16
168	cmpwi cr0,r0,0x39
169	cmpwi cr1,r0,0x3c
170	cror 4cr0+eq,4cr0+eq,4*cr1+eq
171	bne 1f
172
173	/* Before accessing memory, we make sure rm_ci is clear */
174	li r0,0
175	mfspr r3,SPRN_HID4
176	rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
177	sync
178	mtspr SPRN_HID4,r3
179	isync
180	sync
181
182	/* Clear interrupt prefix */
183	li r0,0
184	sync
185	mtspr SPRN_HIOR,0
186	isync
187
188	/* Restore HID0 */
189	ld r3,CS_HID0(r5)
190	sync
191	isync
192	mtspr SPRN_HID0,r3
193	mfspr r3,SPRN_HID0
194	mfspr r3,SPRN_HID0
195	mfspr r3,SPRN_HID0
196	mfspr r3,SPRN_HID0
197	mfspr r3,SPRN_HID0
198	mfspr r3,SPRN_HID0
199	sync
200	isync
201
202	/* Restore HID1 */
203	ld r3,CS_HID1(r5)
204	sync
205	isync
206	mtspr SPRN_HID1,r3
207	mtspr SPRN_HID1,r3
208	sync
209	isync
210
211	/* Restore HID4 */
212	ld r3,CS_HID4(r5)
213	sync
214	isync
215	mtspr SPRN_HID4,r3
216	sync
217	isync
218
219	/* Restore HID5 */
220	ld r3,CS_HID5(r5)
221	sync
222	isync
223	mtspr SPRN_HID5,r3
224	sync
225	isync
226	1:
227	blr
228