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90eb2665 | 1 | /* |
90eb2665 RD |
2 | * Yucca board specific routines |
3 | * | |
4 | * Roland Dreier <rolandd@cisco.com> (based on luan.c by Matt Porter) | |
5 | * | |
6 | * Copyright 2004-2005 MontaVista Software Inc. | |
7 | * Copyright (c) 2005 Cisco Systems. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | */ | |
14 | ||
90eb2665 RD |
15 | #include <linux/stddef.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/reboot.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/kdev_t.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/major.h> | |
24 | #include <linux/blkdev.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/ide.h> | |
28 | #include <linux/initrd.h> | |
29 | #include <linux/seq_file.h> | |
30 | #include <linux/root_dev.h> | |
31 | #include <linux/tty.h> | |
32 | #include <linux/serial.h> | |
33 | #include <linux/serial_core.h> | |
b187f180 | 34 | #include <linux/serial_8250.h> |
90eb2665 RD |
35 | |
36 | #include <asm/system.h> | |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/page.h> | |
39 | #include <asm/dma.h> | |
40 | #include <asm/io.h> | |
41 | #include <asm/machdep.h> | |
42 | #include <asm/ocp.h> | |
43 | #include <asm/pci-bridge.h> | |
44 | #include <asm/time.h> | |
45 | #include <asm/todc.h> | |
46 | #include <asm/bootinfo.h> | |
47 | #include <asm/ppc4xx_pic.h> | |
48 | #include <asm/ppcboot.h> | |
49 | ||
50 | #include <syslib/ibm44x_common.h> | |
51 | #include <syslib/ibm440gx_common.h> | |
52 | #include <syslib/ibm440sp_common.h> | |
53 | #include <syslib/ppc440spe_pcie.h> | |
54 | ||
55 | extern bd_t __res; | |
56 | ||
57 | static struct ibm44x_clocks clocks __initdata; | |
58 | ||
59 | static void __init | |
60 | yucca_calibrate_decr(void) | |
61 | { | |
62 | unsigned int freq; | |
63 | ||
64 | if (mfspr(SPRN_CCR1) & CCR1_TCS) | |
65 | freq = YUCCA_TMR_CLK; | |
66 | else | |
67 | freq = clocks.cpu; | |
68 | ||
69 | ibm44x_calibrate_decr(freq); | |
70 | } | |
71 | ||
72 | static int | |
73 | yucca_show_cpuinfo(struct seq_file *m) | |
74 | { | |
75 | seq_printf(m, "vendor\t\t: AMCC\n"); | |
76 | seq_printf(m, "machine\t\t: PPC440SPe EVB (Yucca)\n"); | |
77 | ||
78 | return 0; | |
79 | } | |
80 | ||
81 | static enum { | |
82 | HOSE_UNKNOWN, | |
83 | HOSE_PCIX, | |
84 | HOSE_PCIE0, | |
85 | HOSE_PCIE1, | |
86 | HOSE_PCIE2 | |
87 | } hose_type[4]; | |
88 | ||
89 | static inline int | |
90 | yucca_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) | |
91 | { | |
92 | struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); | |
93 | ||
94 | if (hose_type[hose->index] == HOSE_PCIX) { | |
95 | static char pci_irq_table[][4] = | |
96 | /* | |
97 | * PCI IDSEL/INTPIN->INTLINE | |
98 | * A B C D | |
99 | */ | |
100 | { | |
101 | { 81, -1, -1, -1 }, /* IDSEL 1 - PCIX0 Slot 0 */ | |
102 | }; | |
103 | const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; | |
104 | return PCI_IRQ_TABLE_LOOKUP; | |
105 | } else if (hose_type[hose->index] == HOSE_PCIE0) { | |
106 | static char pci_irq_table[][4] = | |
107 | /* | |
108 | * PCI IDSEL/INTPIN->INTLINE | |
109 | * A B C D | |
110 | */ | |
111 | { | |
112 | { 96, 97, 98, 99 }, | |
113 | }; | |
114 | const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; | |
115 | return PCI_IRQ_TABLE_LOOKUP; | |
116 | } else if (hose_type[hose->index] == HOSE_PCIE1) { | |
117 | static char pci_irq_table[][4] = | |
118 | /* | |
119 | * PCI IDSEL/INTPIN->INTLINE | |
120 | * A B C D | |
121 | */ | |
122 | { | |
123 | { 100, 101, 102, 103 }, | |
124 | }; | |
125 | const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; | |
126 | return PCI_IRQ_TABLE_LOOKUP; | |
127 | } else if (hose_type[hose->index] == HOSE_PCIE2) { | |
128 | static char pci_irq_table[][4] = | |
129 | /* | |
130 | * PCI IDSEL/INTPIN->INTLINE | |
131 | * A B C D | |
132 | */ | |
133 | { | |
134 | { 104, 105, 106, 107 }, | |
135 | }; | |
136 | const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; | |
137 | return PCI_IRQ_TABLE_LOOKUP; | |
138 | } | |
139 | return -1; | |
140 | } | |
141 | ||
142 | static void __init yucca_set_emacdata(void) | |
143 | { | |
144 | struct ocp_def *def; | |
145 | struct ocp_func_emac_data *emacdata; | |
146 | ||
147 | /* Set phy_map, phy_mode, and mac_addr for the EMAC */ | |
148 | def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0); | |
149 | emacdata = def->additions; | |
150 | emacdata->phy_map = 0x00000001; /* Skip 0x00 */ | |
151 | emacdata->phy_mode = PHY_MODE_GMII; | |
152 | memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); | |
153 | } | |
154 | ||
155 | static int __init yucca_pcie_card_present(int port) | |
156 | { | |
157 | void __iomem *pcie_fpga_base; | |
158 | u16 reg; | |
159 | ||
160 | pcie_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE); | |
161 | reg = in_be16(pcie_fpga_base + FPGA_REG1C); | |
162 | iounmap(pcie_fpga_base); | |
163 | ||
164 | switch(port) { | |
165 | case 0: return !(reg & FPGA_REG1C_PE0_PRSNT); | |
166 | case 1: return !(reg & FPGA_REG1C_PE1_PRSNT); | |
167 | case 2: return !(reg & FPGA_REG1C_PE2_PRSNT); | |
168 | default: return 0; | |
169 | } | |
170 | } | |
171 | ||
172 | /* | |
173 | * For the given slot, set rootpoint mode, send power to the slot, | |
174 | * turn on the green LED and turn off the yellow LED, enable the clock | |
175 | * and turn off reset. | |
176 | */ | |
177 | static void __init yucca_setup_pcie_fpga_rootpoint(int port) | |
178 | { | |
179 | void __iomem *pcie_reg_fpga_base; | |
180 | u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint; | |
181 | ||
182 | pcie_reg_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE); | |
183 | ||
184 | switch(port) { | |
185 | case 0: | |
186 | rootpoint = FPGA_REG1C_PE0_ROOTPOINT; | |
187 | endpoint = 0; | |
188 | power = FPGA_REG1A_PE0_PWRON; | |
189 | green_led = FPGA_REG1A_PE0_GLED; | |
190 | clock = FPGA_REG1A_PE0_REFCLK_ENABLE; | |
191 | yellow_led = FPGA_REG1A_PE0_YLED; | |
192 | reset_off = FPGA_REG1C_PE0_PERST; | |
193 | break; | |
194 | case 1: | |
195 | rootpoint = 0; | |
196 | endpoint = FPGA_REG1C_PE1_ENDPOINT; | |
197 | power = FPGA_REG1A_PE1_PWRON; | |
198 | green_led = FPGA_REG1A_PE1_GLED; | |
199 | clock = FPGA_REG1A_PE1_REFCLK_ENABLE; | |
200 | yellow_led = FPGA_REG1A_PE1_YLED; | |
201 | reset_off = FPGA_REG1C_PE1_PERST; | |
202 | break; | |
203 | case 2: | |
204 | rootpoint = 0; | |
205 | endpoint = FPGA_REG1C_PE2_ENDPOINT; | |
206 | power = FPGA_REG1A_PE2_PWRON; | |
207 | green_led = FPGA_REG1A_PE2_GLED; | |
208 | clock = FPGA_REG1A_PE2_REFCLK_ENABLE; | |
209 | yellow_led = FPGA_REG1A_PE2_YLED; | |
210 | reset_off = FPGA_REG1C_PE2_PERST; | |
211 | break; | |
212 | ||
213 | default: | |
2ae24c52 | 214 | iounmap(pcie_reg_fpga_base); |
90eb2665 RD |
215 | return; |
216 | } | |
217 | ||
218 | out_be16(pcie_reg_fpga_base + FPGA_REG1A, | |
219 | ~(power | clock | green_led) & | |
220 | (yellow_led | in_be16(pcie_reg_fpga_base + FPGA_REG1A))); | |
221 | out_be16(pcie_reg_fpga_base + FPGA_REG1C, | |
222 | ~(endpoint | reset_off) & | |
223 | (rootpoint | in_be16(pcie_reg_fpga_base + FPGA_REG1C))); | |
224 | ||
225 | /* | |
226 | * Leave device in reset for a while after powering on the | |
227 | * slot to give it a chance to initialize. | |
228 | */ | |
229 | mdelay(250); | |
230 | ||
231 | out_be16(pcie_reg_fpga_base + FPGA_REG1C, | |
232 | reset_off | in_be16(pcie_reg_fpga_base + FPGA_REG1C)); | |
233 | ||
234 | iounmap(pcie_reg_fpga_base); | |
235 | } | |
236 | ||
237 | static void __init | |
238 | yucca_setup_hoses(void) | |
239 | { | |
240 | struct pci_controller *hose; | |
241 | char name[20]; | |
242 | int i; | |
243 | ||
244 | if (0 && ppc440spe_init_pcie()) { | |
245 | printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n"); | |
246 | return; | |
247 | } | |
248 | ||
249 | for (i = 0; i <= 2; ++i) { | |
250 | if (!yucca_pcie_card_present(i)) | |
251 | continue; | |
252 | ||
253 | printk(KERN_INFO "PCIE%d: card present\n", i); | |
254 | yucca_setup_pcie_fpga_rootpoint(i); | |
255 | if (ppc440spe_init_pcie_rootport(i)) { | |
256 | printk(KERN_WARNING "PCIE%d: initialization failed\n", i); | |
257 | continue; | |
258 | } | |
259 | ||
260 | hose = pcibios_alloc_controller(); | |
261 | if (!hose) | |
262 | return; | |
263 | ||
264 | sprintf(name, "PCIE%d host bridge", i); | |
265 | pci_init_resource(&hose->io_resource, | |
266 | YUCCA_PCIX_LOWER_IO, | |
267 | YUCCA_PCIX_UPPER_IO, | |
268 | IORESOURCE_IO, | |
269 | name); | |
270 | ||
271 | hose->mem_space.start = YUCCA_PCIE_LOWER_MEM + | |
272 | i * YUCCA_PCIE_MEM_SIZE; | |
273 | hose->mem_space.end = hose->mem_space.start + | |
274 | YUCCA_PCIE_MEM_SIZE - 1; | |
275 | ||
276 | pci_init_resource(&hose->mem_resources[0], | |
277 | hose->mem_space.start, | |
278 | hose->mem_space.end, | |
279 | IORESOURCE_MEM, | |
280 | name); | |
281 | ||
282 | hose->first_busno = 0; | |
283 | hose->last_busno = 15; | |
284 | hose_type[hose->index] = HOSE_PCIE0 + i; | |
285 | ||
286 | ppc440spe_setup_pcie(hose, i); | |
287 | hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); | |
288 | } | |
289 | ||
290 | ppc_md.pci_swizzle = common_swizzle; | |
291 | ppc_md.pci_map_irq = yucca_map_irq; | |
292 | } | |
293 | ||
294 | TODC_ALLOC(); | |
295 | ||
296 | static void __init | |
297 | yucca_early_serial_map(void) | |
298 | { | |
299 | struct uart_port port; | |
300 | ||
301 | /* Setup ioremapped serial port access */ | |
302 | memset(&port, 0, sizeof(port)); | |
303 | port.membase = ioremap64(PPC440SPE_UART0_ADDR, 8); | |
304 | port.irq = UART0_INT; | |
305 | port.uartclk = clocks.uart0; | |
306 | port.regshift = 0; | |
9b4a1617 | 307 | port.iotype = UPIO_MEM; |
59a675b2 | 308 | port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; |
90eb2665 RD |
309 | port.line = 0; |
310 | ||
311 | if (early_serial_setup(&port) != 0) { | |
312 | printk("Early serial init of port 0 failed\n"); | |
313 | } | |
314 | ||
315 | port.membase = ioremap64(PPC440SPE_UART1_ADDR, 8); | |
316 | port.irq = UART1_INT; | |
317 | port.uartclk = clocks.uart1; | |
318 | port.line = 1; | |
319 | ||
320 | if (early_serial_setup(&port) != 0) { | |
321 | printk("Early serial init of port 1 failed\n"); | |
322 | } | |
323 | ||
324 | port.membase = ioremap64(PPC440SPE_UART2_ADDR, 8); | |
325 | port.irq = UART2_INT; | |
326 | port.uartclk = BASE_BAUD; | |
327 | port.line = 2; | |
328 | ||
329 | if (early_serial_setup(&port) != 0) { | |
330 | printk("Early serial init of port 2 failed\n"); | |
331 | } | |
332 | } | |
333 | ||
334 | static void __init | |
335 | yucca_setup_arch(void) | |
336 | { | |
337 | yucca_set_emacdata(); | |
338 | ||
339 | #if !defined(CONFIG_BDI_SWITCH) | |
340 | /* | |
341 | * The Abatron BDI JTAG debugger does not tolerate others | |
342 | * mucking with the debug registers. | |
343 | */ | |
344 | mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM)); | |
345 | #endif | |
346 | ||
347 | /* | |
348 | * Determine various clocks. | |
349 | * To be completely correct we should get SysClk | |
350 | * from FPGA, because it can be changed by on-board switches | |
351 | * --ebs | |
352 | */ | |
353 | /* 440GX and 440SPe clocking is the same - rd */ | |
354 | ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200); | |
355 | ocp_sys_info.opb_bus_freq = clocks.opb; | |
356 | ||
357 | /* init to some ~sane value until calibrate_delay() runs */ | |
358 | loops_per_jiffy = 50000000/HZ; | |
359 | ||
360 | /* Setup PCIXn host bridges */ | |
361 | yucca_setup_hoses(); | |
362 | ||
363 | #ifdef CONFIG_BLK_DEV_INITRD | |
364 | if (initrd_start) | |
365 | ROOT_DEV = Root_RAM0; | |
366 | else | |
367 | #endif | |
368 | #ifdef CONFIG_ROOT_NFS | |
369 | ROOT_DEV = Root_NFS; | |
370 | #else | |
371 | ROOT_DEV = Root_HDA1; | |
372 | #endif | |
373 | ||
374 | yucca_early_serial_map(); | |
375 | ||
376 | /* Identify the system */ | |
377 | printk("Yucca port (Roland Dreier <rolandd@cisco.com>)\n"); | |
378 | } | |
379 | ||
380 | void __init platform_init(unsigned long r3, unsigned long r4, | |
381 | unsigned long r5, unsigned long r6, unsigned long r7) | |
382 | { | |
383 | ibm44x_platform_init(r3, r4, r5, r6, r7); | |
384 | ||
385 | ppc_md.setup_arch = yucca_setup_arch; | |
386 | ppc_md.show_cpuinfo = yucca_show_cpuinfo; | |
387 | ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory; | |
388 | ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ | |
389 | ||
390 | ppc_md.calibrate_decr = yucca_calibrate_decr; | |
391 | #ifdef CONFIG_KGDB | |
392 | ppc_md.early_serial_map = yucca_early_serial_map; | |
393 | #endif | |
394 | } |