Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
0b05ac6e BH |
2 | /* |
3 | * Copyright 2011 IBM Corporation. | |
0b05ac6e BH |
4 | */ |
5 | #include <linux/types.h> | |
6 | #include <linux/threads.h> | |
7 | #include <linux/kernel.h> | |
8 | #include <linux/irq.h> | |
e6f6390a | 9 | #include <linux/irqdomain.h> |
0b05ac6e BH |
10 | #include <linux/debugfs.h> |
11 | #include <linux/smp.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/seq_file.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/cpu.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/spinlock.h> | |
a69e2fb7 | 19 | #include <linux/delay.h> |
0b05ac6e | 20 | |
0b05ac6e BH |
21 | #include <asm/io.h> |
22 | #include <asm/smp.h> | |
23 | #include <asm/machdep.h> | |
24 | #include <asm/irq.h> | |
25 | #include <asm/errno.h> | |
26 | #include <asm/rtas.h> | |
27 | #include <asm/xics.h> | |
28 | #include <asm/firmware.h> | |
29 | ||
30 | /* Globals common to all ICP/ICS implementations */ | |
31 | const struct icp_ops *icp_ops; | |
32 | ||
33 | unsigned int xics_default_server = 0xff; | |
34 | unsigned int xics_default_distrib_server = 0; | |
35 | unsigned int xics_interrupt_server_size = 8; | |
36 | ||
37 | DEFINE_PER_CPU(struct xics_cppr, xics_cppr); | |
38 | ||
bae1d8f1 | 39 | struct irq_domain *xics_host; |
0b05ac6e | 40 | |
298f6f95 | 41 | static struct ics *xics_ics; |
0b05ac6e BH |
42 | |
43 | void xics_update_irq_servers(void) | |
44 | { | |
45 | int i, j; | |
46 | struct device_node *np; | |
47 | u32 ilen; | |
d213dd53 | 48 | const __be32 *ireg; |
0b05ac6e BH |
49 | u32 hcpuid; |
50 | ||
51 | /* Find the server numbers for the boot cpu. */ | |
52 | np = of_get_cpu_node(boot_cpuid, NULL); | |
53 | BUG_ON(!np); | |
54 | ||
55 | hcpuid = get_hard_smp_processor_id(boot_cpuid); | |
f6e17f9b BH |
56 | xics_default_server = xics_default_distrib_server = hcpuid; |
57 | ||
58 | pr_devel("xics: xics_default_server = 0x%x\n", xics_default_server); | |
0b05ac6e BH |
59 | |
60 | ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen); | |
61 | if (!ireg) { | |
62 | of_node_put(np); | |
63 | return; | |
64 | } | |
65 | ||
66 | i = ilen / sizeof(int); | |
67 | ||
68 | /* Global interrupt distribution server is specified in the last | |
69 | * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last | |
70 | * entry fom this property for current boot cpu id and use it as | |
71 | * default distribution server | |
72 | */ | |
73 | for (j = 0; j < i; j += 2) { | |
d213dd53 AB |
74 | if (be32_to_cpu(ireg[j]) == hcpuid) { |
75 | xics_default_distrib_server = be32_to_cpu(ireg[j+1]); | |
f6e17f9b | 76 | break; |
0b05ac6e BH |
77 | } |
78 | } | |
f6e17f9b BH |
79 | pr_devel("xics: xics_default_distrib_server = 0x%x\n", |
80 | xics_default_distrib_server); | |
0b05ac6e BH |
81 | of_node_put(np); |
82 | } | |
83 | ||
84 | /* GIQ stuff, currently only supported on RTAS setups, will have | |
85 | * to be sorted properly for bare metal | |
86 | */ | |
87 | void xics_set_cpu_giq(unsigned int gserver, unsigned int join) | |
88 | { | |
89 | #ifdef CONFIG_PPC_RTAS | |
90 | int index; | |
91 | int status; | |
92 | ||
93 | if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL)) | |
94 | return; | |
95 | ||
96 | index = (1UL << xics_interrupt_server_size) - 1 - gserver; | |
97 | ||
98 | status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join); | |
99 | ||
100 | WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n", | |
101 | GLOBAL_INTERRUPT_QUEUE, index, join, status); | |
102 | #endif | |
103 | } | |
104 | ||
105 | void xics_setup_cpu(void) | |
106 | { | |
107 | icp_ops->set_priority(LOWEST_PRIORITY); | |
108 | ||
109 | xics_set_cpu_giq(xics_default_distrib_server, 1); | |
110 | } | |
111 | ||
112 | void xics_mask_unknown_vec(unsigned int vec) | |
113 | { | |
f6e17f9b | 114 | pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec); |
0b05ac6e | 115 | |
298f6f95 CLG |
116 | if (WARN_ON(!xics_ics)) |
117 | return; | |
118 | xics_ics->mask_unknown(xics_ics, vec); | |
0b05ac6e BH |
119 | } |
120 | ||
121 | ||
122 | #ifdef CONFIG_SMP | |
123 | ||
6c552983 | 124 | static void __init xics_request_ipi(void) |
0b05ac6e BH |
125 | { |
126 | unsigned int ipi; | |
127 | ||
128 | ipi = irq_create_mapping(xics_host, XICS_IPI); | |
ef24ba70 | 129 | BUG_ON(!ipi); |
0b05ac6e BH |
130 | |
131 | /* | |
a3a9f3b4 | 132 | * IPIs are marked IRQF_PERCPU. The handler was set in map. |
0b05ac6e | 133 | */ |
0b05ac6e | 134 | BUG_ON(request_irq(ipi, icp_ops->ipi_action, |
17df41fe | 135 | IRQF_NO_DEBUG | IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL)); |
0b05ac6e BH |
136 | } |
137 | ||
a7f4ee1f | 138 | void __init xics_smp_probe(void) |
0b05ac6e | 139 | { |
0b05ac6e BH |
140 | /* Register all the IPIs */ |
141 | xics_request_ipi(); | |
45b21cfe ME |
142 | |
143 | /* Setup cause_ipi callback based on which ICP is used */ | |
144 | smp_ops->cause_ipi = icp_ops->cause_ipi; | |
0b05ac6e BH |
145 | } |
146 | ||
147 | #endif /* CONFIG_SMP */ | |
148 | ||
2ab2d579 | 149 | noinstr void xics_teardown_cpu(void) |
0b05ac6e | 150 | { |
69111bac | 151 | struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr); |
0b05ac6e BH |
152 | |
153 | /* | |
154 | * we have to reset the cppr index to 0 because we're | |
155 | * not going to return from the IPI | |
156 | */ | |
157 | os_cppr->index = 0; | |
158 | icp_ops->set_priority(0); | |
159 | icp_ops->teardown_cpu(); | |
160 | } | |
161 | ||
2ab2d579 | 162 | noinstr void xics_kexec_teardown_cpu(int secondary) |
0b05ac6e BH |
163 | { |
164 | xics_teardown_cpu(); | |
165 | ||
166 | icp_ops->flush_ipi(); | |
167 | ||
168 | /* | |
169 | * Some machines need to have at least one cpu in the GIQ, | |
170 | * so leave the master cpu in the group. | |
171 | */ | |
172 | if (secondary) | |
173 | xics_set_cpu_giq(xics_default_distrib_server, 0); | |
174 | } | |
175 | ||
176 | ||
177 | #ifdef CONFIG_HOTPLUG_CPU | |
178 | ||
179 | /* Interrupts are disabled. */ | |
180 | void xics_migrate_irqs_away(void) | |
181 | { | |
182 | int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id(); | |
183 | unsigned int irq, virq; | |
4013369f | 184 | struct irq_desc *desc; |
0b05ac6e | 185 | |
c80198a2 CLG |
186 | pr_debug("%s: CPU %u\n", __func__, cpu); |
187 | ||
0b05ac6e BH |
188 | /* If we used to be the default server, move to the new "boot_cpuid" */ |
189 | if (hw_cpu == xics_default_server) | |
190 | xics_update_irq_servers(); | |
191 | ||
192 | /* Reject any interrupt that was queued to us... */ | |
193 | icp_ops->set_priority(0); | |
194 | ||
195 | /* Remove ourselves from the global interrupt queue */ | |
196 | xics_set_cpu_giq(xics_default_distrib_server, 0); | |
197 | ||
4013369f | 198 | for_each_irq_desc(virq, desc) { |
0b05ac6e BH |
199 | struct irq_chip *chip; |
200 | long server; | |
201 | unsigned long flags; | |
c80198a2 | 202 | struct irq_data *irqd; |
0b05ac6e BH |
203 | |
204 | /* We can't set affinity on ISA interrupts */ | |
7c576f4d | 205 | if (virq < NR_IRQS_LEGACY) |
0b05ac6e | 206 | continue; |
0b05ac6e | 207 | /* We only need to migrate enabled IRQS */ |
4013369f | 208 | if (!desc->action) |
0b05ac6e | 209 | continue; |
c80198a2 CLG |
210 | /* We need a mapping in the XICS IRQ domain */ |
211 | irqd = irq_domain_get_irq_data(xics_host, virq); | |
212 | if (!irqd) | |
6d9285b0 | 213 | continue; |
c80198a2 | 214 | irq = irqd_to_hwirq(irqd); |
6d9285b0 GL |
215 | /* We need to get IPIs still. */ |
216 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
217 | continue; | |
0b05ac6e BH |
218 | chip = irq_desc_get_chip(desc); |
219 | if (!chip || !chip->irq_set_affinity) | |
220 | continue; | |
221 | ||
222 | raw_spin_lock_irqsave(&desc->lock, flags); | |
223 | ||
224 | /* Locate interrupt server */ | |
298f6f95 | 225 | server = xics_ics->get_server(xics_ics, irq); |
0b05ac6e | 226 | if (server < 0) { |
298f6f95 CLG |
227 | pr_err("%s: Can't find server for irq %d/%x\n", |
228 | __func__, virq, irq); | |
0b05ac6e BH |
229 | goto unlock; |
230 | } | |
231 | ||
232 | /* We only support delivery to all cpus or to one cpu. | |
233 | * The irq has to be migrated only in the single cpu | |
234 | * case. | |
235 | */ | |
236 | if (server != hw_cpu) | |
237 | goto unlock; | |
238 | ||
239 | /* This is expected during cpu offline. */ | |
240 | if (cpu_online(cpu)) | |
f2c2cbcc JP |
241 | pr_warn("IRQ %u affinity broken off cpu %u\n", |
242 | virq, cpu); | |
0b05ac6e BH |
243 | |
244 | /* Reset affinity to all cpus */ | |
245 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
246 | irq_set_affinity(virq, cpu_all_mask); | |
247 | continue; | |
248 | unlock: | |
249 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
250 | } | |
a69e2fb7 BS |
251 | |
252 | /* Allow "sufficient" time to drop any inflight IRQ's */ | |
253 | mdelay(5); | |
254 | ||
255 | /* | |
256 | * Allow IPIs again. This is done at the very end, after migrating all | |
257 | * interrupts, the expectation is that we'll only get woken up by an IPI | |
258 | * interrupt beyond this point, but leave externals masked just to be | |
259 | * safe. If we're using icp-opal this may actually allow all | |
260 | * interrupts anyway, but that should be OK. | |
261 | */ | |
262 | icp_ops->set_priority(DEFAULT_PRIORITY); | |
263 | ||
0b05ac6e BH |
264 | } |
265 | #endif /* CONFIG_HOTPLUG_CPU */ | |
266 | ||
267 | #ifdef CONFIG_SMP | |
268 | /* | |
269 | * For the moment we only implement delivery to all cpus or one cpu. | |
270 | * | |
271 | * If the requested affinity is cpu_all_mask, we set global affinity. | |
272 | * If not we set it to the first cpu in the mask, even if multiple cpus | |
273 | * are set. This is so things like irqbalance (which set core and package | |
274 | * wide affinities) do the right thing. | |
f6e17f9b BH |
275 | * |
276 | * We need to fix this to implement support for the links | |
0b05ac6e BH |
277 | */ |
278 | int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask, | |
279 | unsigned int strict_check) | |
280 | { | |
281 | ||
282 | if (!distribute_irqs) | |
283 | return xics_default_server; | |
284 | ||
285 | if (!cpumask_subset(cpu_possible_mask, cpumask)) { | |
286 | int server = cpumask_first_and(cpu_online_mask, cpumask); | |
287 | ||
288 | if (server < nr_cpu_ids) | |
289 | return get_hard_smp_processor_id(server); | |
290 | ||
291 | if (strict_check) | |
292 | return -1; | |
293 | } | |
294 | ||
295 | /* | |
296 | * Workaround issue with some versions of JS20 firmware that | |
297 | * deliver interrupts to cpus which haven't been started. This | |
298 | * happens when using the maxcpus= boot option. | |
299 | */ | |
300 | if (cpumask_equal(cpu_online_mask, cpu_present_mask)) | |
301 | return xics_default_distrib_server; | |
302 | ||
303 | return xics_default_server; | |
304 | } | |
305 | #endif /* CONFIG_SMP */ | |
306 | ||
ad3aedfb MZ |
307 | static int xics_host_match(struct irq_domain *h, struct device_node *node, |
308 | enum irq_domain_bus_token bus_token) | |
0b05ac6e | 309 | { |
298f6f95 CLG |
310 | if (WARN_ON(!xics_ics)) |
311 | return 0; | |
312 | return xics_ics->host_match(xics_ics, node) ? 1 : 0; | |
0b05ac6e BH |
313 | } |
314 | ||
315 | /* Dummies */ | |
316 | static void xics_ipi_unmask(struct irq_data *d) { } | |
317 | static void xics_ipi_mask(struct irq_data *d) { } | |
318 | ||
319 | static struct irq_chip xics_ipi_chip = { | |
320 | .name = "XICS", | |
321 | .irq_eoi = NULL, /* Patched at init time */ | |
322 | .irq_mask = xics_ipi_mask, | |
323 | .irq_unmask = xics_ipi_unmask, | |
324 | }; | |
325 | ||
248af248 CLG |
326 | static int xics_host_map(struct irq_domain *domain, unsigned int virq, |
327 | irq_hw_number_t hwirq) | |
0b05ac6e | 328 | { |
248af248 | 329 | pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hwirq); |
0b05ac6e | 330 | |
880a3d6a BH |
331 | /* |
332 | * Mark interrupts as edge sensitive by default so that resend | |
333 | * actually works. The device-tree parsing will turn the LSIs | |
334 | * back to level. | |
335 | */ | |
336 | irq_clear_status_flags(virq, IRQ_LEVEL); | |
0b05ac6e BH |
337 | |
338 | /* Don't call into ICS for IPIs */ | |
248af248 | 339 | if (hwirq == XICS_IPI) { |
0b05ac6e | 340 | irq_set_chip_and_handler(virq, &xics_ipi_chip, |
e085255e | 341 | handle_percpu_irq); |
0b05ac6e BH |
342 | return 0; |
343 | } | |
344 | ||
298f6f95 CLG |
345 | if (WARN_ON(!xics_ics)) |
346 | return -EINVAL; | |
347 | ||
248af248 | 348 | if (xics_ics->check(xics_ics, hwirq)) |
298f6f95 | 349 | return -EINVAL; |
e085255e | 350 | |
c006a065 | 351 | /* Let the ICS be the chip data for the XICS domain. For ICS native */ |
248af248 | 352 | irq_domain_set_info(domain, virq, hwirq, xics_ics->chip, |
c006a065 | 353 | xics_ics, handle_fasteoi_irq, NULL, NULL); |
248af248 | 354 | |
298f6f95 | 355 | return 0; |
0b05ac6e BH |
356 | } |
357 | ||
bae1d8f1 | 358 | static int xics_host_xlate(struct irq_domain *h, struct device_node *ct, |
0b05ac6e BH |
359 | const u32 *intspec, unsigned int intsize, |
360 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) | |
361 | ||
362 | { | |
0b05ac6e | 363 | *out_hwirq = intspec[0]; |
0b05ac6e | 364 | |
880a3d6a BH |
365 | /* |
366 | * If intsize is at least 2, we look for the type in the second cell, | |
367 | * we assume the LSB indicates a level interrupt. | |
368 | */ | |
369 | if (intsize > 1) { | |
370 | if (intspec[1] & 1) | |
371 | *out_flags = IRQ_TYPE_LEVEL_LOW; | |
372 | else | |
373 | *out_flags = IRQ_TYPE_EDGE_RISING; | |
374 | } else | |
375 | *out_flags = IRQ_TYPE_LEVEL_LOW; | |
376 | ||
377 | return 0; | |
378 | } | |
379 | ||
380 | int xics_set_irq_type(struct irq_data *d, unsigned int flow_type) | |
381 | { | |
382 | /* | |
383 | * We only support these. This has really no effect other than setting | |
384 | * the corresponding descriptor bits mind you but those will in turn | |
385 | * affect the resend function when re-enabling an edge interrupt. | |
386 | * | |
387 | * Set set the default to edge as explained in map(). | |
388 | */ | |
389 | if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE) | |
390 | flow_type = IRQ_TYPE_EDGE_RISING; | |
391 | ||
392 | if (flow_type != IRQ_TYPE_EDGE_RISING && | |
393 | flow_type != IRQ_TYPE_LEVEL_LOW) | |
394 | return -EINVAL; | |
395 | ||
396 | irqd_set_trigger_type(d, flow_type); | |
397 | ||
398 | return IRQ_SET_MASK_OK_NOCOPY; | |
399 | } | |
400 | ||
401 | int xics_retrigger(struct irq_data *data) | |
402 | { | |
403 | /* | |
404 | * We need to push a dummy CPPR when retriggering, since the subsequent | |
405 | * EOI will try to pop it. Passing 0 works, as the function hard codes | |
406 | * the priority value anyway. | |
407 | */ | |
408 | xics_push_cppr(0); | |
409 | ||
410 | /* Tell the core to do a soft retrigger */ | |
0b05ac6e BH |
411 | return 0; |
412 | } | |
413 | ||
e4f0aa3b CLG |
414 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
415 | static int xics_host_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, | |
416 | unsigned long *hwirq, unsigned int *type) | |
417 | { | |
418 | return xics_host_xlate(d, to_of_node(fwspec->fwnode), fwspec->param, | |
419 | fwspec->param_count, hwirq, type); | |
420 | } | |
421 | ||
422 | static int xics_host_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
423 | unsigned int nr_irqs, void *arg) | |
424 | { | |
425 | struct irq_fwspec *fwspec = arg; | |
426 | irq_hw_number_t hwirq; | |
427 | unsigned int type = IRQ_TYPE_NONE; | |
428 | int i, rc; | |
429 | ||
430 | rc = xics_host_domain_translate(domain, fwspec, &hwirq, &type); | |
431 | if (rc) | |
432 | return rc; | |
433 | ||
434 | pr_debug("%s %d/%lx #%d\n", __func__, virq, hwirq, nr_irqs); | |
435 | ||
436 | for (i = 0; i < nr_irqs; i++) | |
437 | irq_domain_set_info(domain, virq + i, hwirq + i, xics_ics->chip, | |
438 | xics_ics, handle_fasteoi_irq, NULL, NULL); | |
439 | ||
440 | return 0; | |
441 | } | |
442 | ||
443 | static void xics_host_domain_free(struct irq_domain *domain, | |
444 | unsigned int virq, unsigned int nr_irqs) | |
445 | { | |
446 | pr_debug("%s %d #%d\n", __func__, virq, nr_irqs); | |
447 | } | |
448 | #endif | |
449 | ||
202648a6 | 450 | static const struct irq_domain_ops xics_host_ops = { |
e4f0aa3b CLG |
451 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
452 | .alloc = xics_host_domain_alloc, | |
453 | .free = xics_host_domain_free, | |
454 | .translate = xics_host_domain_translate, | |
455 | #endif | |
0b05ac6e BH |
456 | .match = xics_host_match, |
457 | .map = xics_host_map, | |
458 | .xlate = xics_host_xlate, | |
459 | }; | |
460 | ||
7d14f6c6 | 461 | static int __init xics_allocate_domain(void) |
0b05ac6e | 462 | { |
7d14f6c6 CLG |
463 | struct fwnode_handle *fn; |
464 | ||
465 | fn = irq_domain_alloc_named_fwnode("XICS"); | |
466 | if (!fn) | |
467 | return -ENOMEM; | |
468 | ||
469 | xics_host = irq_domain_create_tree(fn, &xics_host_ops, NULL); | |
470 | if (!xics_host) { | |
471 | irq_domain_free_fwnode(fn); | |
472 | return -ENOMEM; | |
473 | } | |
474 | ||
0b05ac6e | 475 | irq_set_default_host(xics_host); |
7d14f6c6 | 476 | return 0; |
0b05ac6e BH |
477 | } |
478 | ||
479 | void __init xics_register_ics(struct ics *ics) | |
480 | { | |
298f6f95 CLG |
481 | if (WARN_ONCE(xics_ics, "XICS: Source Controller is already defined !")) |
482 | return; | |
483 | xics_ics = ics; | |
0b05ac6e BH |
484 | } |
485 | ||
486 | static void __init xics_get_server_size(void) | |
487 | { | |
488 | struct device_node *np; | |
d213dd53 | 489 | const __be32 *isize; |
0b05ac6e BH |
490 | |
491 | /* We fetch the interrupt server size from the first ICS node | |
492 | * we find if any | |
493 | */ | |
494 | np = of_find_compatible_node(NULL, NULL, "ibm,ppc-xics"); | |
495 | if (!np) | |
496 | return; | |
589b1f7e | 497 | |
0b05ac6e | 498 | isize = of_get_property(np, "ibm,interrupt-server#-size", NULL); |
589b1f7e Y |
499 | if (isize) |
500 | xics_interrupt_server_size = be32_to_cpu(*isize); | |
501 | ||
0b05ac6e BH |
502 | of_node_put(np); |
503 | } | |
504 | ||
505 | void __init xics_init(void) | |
506 | { | |
507 | int rc = -1; | |
508 | ||
509 | /* Fist locate ICP */ | |
0b05ac6e BH |
510 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
511 | rc = icp_hv_init(); | |
d7436188 | 512 | if (rc < 0) { |
0b05ac6e | 513 | rc = icp_native_init(); |
d7436188 BH |
514 | if (rc == -ENODEV) |
515 | rc = icp_opal_init(); | |
516 | } | |
0b05ac6e | 517 | if (rc < 0) { |
f2c2cbcc | 518 | pr_warn("XICS: Cannot find a Presentation Controller !\n"); |
0b05ac6e BH |
519 | return; |
520 | } | |
521 | ||
522 | /* Copy get_irq callback over to ppc_md */ | |
523 | ppc_md.get_irq = icp_ops->get_irq; | |
524 | ||
525 | /* Patch up IPI chip EOI */ | |
526 | xics_ipi_chip.irq_eoi = icp_ops->eoi; | |
527 | ||
528 | /* Now locate ICS */ | |
0b05ac6e | 529 | rc = ics_rtas_init(); |
5c7c1e94 BH |
530 | if (rc < 0) |
531 | rc = ics_opal_init(); | |
aa9c5adf BH |
532 | if (rc < 0) |
533 | rc = ics_native_init(); | |
0b05ac6e | 534 | if (rc < 0) |
f2c2cbcc | 535 | pr_warn("XICS: Cannot find a Source Controller !\n"); |
0b05ac6e BH |
536 | |
537 | /* Initialize common bits */ | |
538 | xics_get_server_size(); | |
539 | xics_update_irq_servers(); | |
7d14f6c6 CLG |
540 | rc = xics_allocate_domain(); |
541 | if (rc < 0) | |
542 | pr_err("XICS: Failed to create IRQ domain"); | |
0b05ac6e BH |
543 | xics_setup_cpu(); |
544 | } |