Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3c8c90ab LV |
2 | * Copyright IBM Corporation 2001, 2005, 2006 |
3 | * Copyright Dave Engebretsen & Todd Inglett 2001 | |
4 | * Copyright Linas Vepstas 2005, 2006 | |
cb3bc9d0 | 5 | * Copyright 2001-2012 IBM Corporation. |
69376502 | 6 | * |
1da177e4 LT |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
69376502 | 11 | * |
1da177e4 LT |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
69376502 | 16 | * |
1da177e4 LT |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
3c8c90ab LV |
20 | * |
21 | * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> | |
1da177e4 LT |
22 | */ |
23 | ||
6dee3fb9 | 24 | #include <linux/delay.h> |
cb3bc9d0 | 25 | #include <linux/sched.h> |
1da177e4 LT |
26 | #include <linux/init.h> |
27 | #include <linux/list.h> | |
1da177e4 LT |
28 | #include <linux/pci.h> |
29 | #include <linux/proc_fs.h> | |
30 | #include <linux/rbtree.h> | |
31 | #include <linux/seq_file.h> | |
32 | #include <linux/spinlock.h> | |
66b15db6 | 33 | #include <linux/export.h> |
acaa6176 SR |
34 | #include <linux/of.h> |
35 | ||
60063497 | 36 | #include <linux/atomic.h> |
1da177e4 | 37 | #include <asm/eeh.h> |
172ca926 | 38 | #include <asm/eeh_event.h> |
1da177e4 LT |
39 | #include <asm/io.h> |
40 | #include <asm/machdep.h> | |
172ca926 | 41 | #include <asm/ppc-pci.h> |
1da177e4 | 42 | #include <asm/rtas.h> |
1da177e4 | 43 | |
1da177e4 LT |
44 | |
45 | /** Overview: | |
46 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
47 | * dealing with PCI bus errors that can't be dealt with within the | |
48 | * usual PCI framework, except by check-stopping the CPU. Systems | |
49 | * that are designed for high-availability/reliability cannot afford | |
50 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
51 | * An EEH-capable bridge operates by converting a detected error | |
52 | * into a "slot freeze", taking the PCI adapter off-line, making | |
53 | * the slot behave, from the OS'es point of view, as if the slot | |
54 | * were "empty": all reads return 0xff's and all writes are silently | |
55 | * ignored. EEH slot isolation events can be triggered by parity | |
56 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
57 | * which in turn might be caused by low voltage on the bus, dust, |
58 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
59 | * |
60 | * Note, however, that one of the leading causes of EEH slot | |
61 | * freeze events are buggy device drivers, buggy device microcode, | |
62 | * or buggy device hardware. This is because any attempt by the | |
63 | * device to bus-master data to a memory address that is not | |
64 | * assigned to the device will trigger a slot freeze. (The idea | |
65 | * is to prevent devices-gone-wild from corrupting system memory). | |
66 | * Buggy hardware/drivers will have a miserable time co-existing | |
67 | * with EEH. | |
68 | * | |
69 | * Ideally, a PCI device driver, when suspecting that an isolation | |
25985edc | 70 | * event has occurred (e.g. by reading 0xff's), will then ask EEH |
1da177e4 LT |
71 | * whether this is the case, and then take appropriate steps to |
72 | * reset the PCI slot, the PCI device, and then resume operations. | |
73 | * However, until that day, the checking is done here, with the | |
74 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
75 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
76 | * and sent out for processing. | |
77 | */ | |
78 | ||
5c1344e9 | 79 | /* If a device driver keeps reading an MMIO register in an interrupt |
f36c5227 MM |
80 | * handler after a slot isolation event, it might be broken. |
81 | * This sets the threshold for how many read attempts we allow | |
82 | * before printing an error message. | |
1da177e4 | 83 | */ |
2fd30be8 | 84 | #define EEH_MAX_FAILS 2100000 |
1da177e4 | 85 | |
17213c3b | 86 | /* Time to wait for a PCI slot to report status, in milliseconds */ |
9c547768 LV |
87 | #define PCI_BUS_RESET_WAIT_MSEC (60*1000) |
88 | ||
aa1e6374 GS |
89 | /* Platform dependent EEH operations */ |
90 | struct eeh_ops *eeh_ops = NULL; | |
91 | ||
1e28a7dd DW |
92 | int eeh_subsystem_enabled; |
93 | EXPORT_SYMBOL(eeh_subsystem_enabled); | |
1da177e4 | 94 | |
646a8499 GS |
95 | /* Global EEH mutex */ |
96 | DEFINE_MUTEX(eeh_mutex); | |
97 | ||
fd761fd8 | 98 | /* Lock to avoid races due to multiple reports of an error */ |
3d372628 | 99 | static DEFINE_RAW_SPINLOCK(confirm_error_lock); |
fd761fd8 | 100 | |
17213c3b LV |
101 | /* Buffer for reporting pci register dumps. Its here in BSS, and |
102 | * not dynamically alloced, so that it ends up in RMO where RTAS | |
103 | * can access it. | |
104 | */ | |
d99bb1db LV |
105 | #define EEH_PCI_REGS_LOG_LEN 4096 |
106 | static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; | |
107 | ||
e575f8db GS |
108 | /* |
109 | * The struct is used to maintain the EEH global statistic | |
110 | * information. Besides, the EEH global statistics will be | |
111 | * exported to user space through procfs | |
112 | */ | |
113 | struct eeh_stats { | |
114 | u64 no_device; /* PCI device not found */ | |
115 | u64 no_dn; /* OF node not found */ | |
116 | u64 no_cfg_addr; /* Config address not found */ | |
117 | u64 ignored_check; /* EEH check skipped */ | |
118 | u64 total_mmio_ffs; /* Total EEH checks */ | |
119 | u64 false_positives; /* Unnecessary EEH checks */ | |
120 | u64 slot_resets; /* PE reset */ | |
121 | }; | |
122 | ||
123 | static struct eeh_stats eeh_stats; | |
1da177e4 | 124 | |
7684b40c LV |
125 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
126 | ||
d99bb1db | 127 | /** |
cce4b2d2 | 128 | * eeh_gather_pci_data - Copy assorted PCI config space registers to buff |
f631acd3 | 129 | * @edev: device to report data for |
d99bb1db LV |
130 | * @buf: point to buffer in which to log |
131 | * @len: amount of room in buffer | |
132 | * | |
133 | * This routine captures assorted PCI configuration space data, | |
134 | * and puts them into a buffer for RTAS error logging. | |
135 | */ | |
f631acd3 | 136 | static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len) |
d99bb1db | 137 | { |
f631acd3 GS |
138 | struct device_node *dn = eeh_dev_to_of_node(edev); |
139 | struct pci_dev *dev = eeh_dev_to_pci_dev(edev); | |
d99bb1db | 140 | u32 cfg; |
fcf9892b | 141 | int cap, i; |
d99bb1db LV |
142 | int n = 0; |
143 | ||
f631acd3 GS |
144 | n += scnprintf(buf+n, len-n, "%s\n", dn->full_name); |
145 | printk(KERN_WARNING "EEH: of node=%s\n", dn->full_name); | |
fcf9892b | 146 | |
3780444c | 147 | eeh_ops->read_config(dn, PCI_VENDOR_ID, 4, &cfg); |
fcf9892b LV |
148 | n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); |
149 | printk(KERN_WARNING "EEH: PCI device/vendor: %08x\n", cfg); | |
150 | ||
3780444c | 151 | eeh_ops->read_config(dn, PCI_COMMAND, 4, &cfg); |
d99bb1db | 152 | n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); |
fcf9892b LV |
153 | printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg); |
154 | ||
b37ceefe LV |
155 | if (!dev) { |
156 | printk(KERN_WARNING "EEH: no PCI device for this of node\n"); | |
157 | return n; | |
158 | } | |
159 | ||
0b9369f4 LV |
160 | /* Gather bridge-specific registers */ |
161 | if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) { | |
3780444c | 162 | eeh_ops->read_config(dn, PCI_SEC_STATUS, 2, &cfg); |
0b9369f4 LV |
163 | n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); |
164 | printk(KERN_WARNING "EEH: Bridge secondary status: %04x\n", cfg); | |
165 | ||
3780444c | 166 | eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &cfg); |
0b9369f4 LV |
167 | n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); |
168 | printk(KERN_WARNING "EEH: Bridge control: %04x\n", cfg); | |
169 | } | |
170 | ||
fcf9892b | 171 | /* Dump out the PCI-X command and status regs */ |
b37ceefe | 172 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
fcf9892b | 173 | if (cap) { |
3780444c | 174 | eeh_ops->read_config(dn, cap, 4, &cfg); |
fcf9892b LV |
175 | n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); |
176 | printk(KERN_WARNING "EEH: PCI-X cmd: %08x\n", cfg); | |
177 | ||
3780444c | 178 | eeh_ops->read_config(dn, cap+4, 4, &cfg); |
fcf9892b LV |
179 | n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); |
180 | printk(KERN_WARNING "EEH: PCI-X status: %08x\n", cfg); | |
181 | } | |
182 | ||
183 | /* If PCI-E capable, dump PCI-E cap 10, and the AER */ | |
b37ceefe | 184 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); |
fcf9892b LV |
185 | if (cap) { |
186 | n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); | |
187 | printk(KERN_WARNING | |
188 | "EEH: PCI-E capabilities and status follow:\n"); | |
189 | ||
190 | for (i=0; i<=8; i++) { | |
3780444c | 191 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); |
fcf9892b LV |
192 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
193 | printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg); | |
194 | } | |
195 | ||
b37ceefe | 196 | cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |
fcf9892b LV |
197 | if (cap) { |
198 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); | |
199 | printk(KERN_WARNING | |
200 | "EEH: PCI-E AER capability register set follows:\n"); | |
201 | ||
202 | for (i=0; i<14; i++) { | |
3780444c | 203 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); |
fcf9892b LV |
204 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
205 | printk(KERN_WARNING "EEH: PCI-E AER %02x: %08x\n", i, cfg); | |
206 | } | |
207 | } | |
208 | } | |
0b9369f4 | 209 | |
d99bb1db LV |
210 | return n; |
211 | } | |
212 | ||
cb3bc9d0 GS |
213 | /** |
214 | * eeh_slot_error_detail - Generate combined log including driver log and error log | |
ff477966 | 215 | * @pe: EEH PE |
cb3bc9d0 GS |
216 | * @severity: temporary or permanent error log |
217 | * | |
218 | * This routine should be called to generate the combined log, which | |
219 | * is comprised of driver log and error log. The driver log is figured | |
220 | * out from the config space of the corresponding PCI device, while | |
221 | * the error log is fetched through platform dependent function call. | |
222 | */ | |
ff477966 | 223 | void eeh_slot_error_detail(struct eeh_pe *pe, int severity) |
d99bb1db LV |
224 | { |
225 | size_t loglen = 0; | |
ff477966 | 226 | struct eeh_dev *edev; |
d99bb1db | 227 | |
ff477966 GS |
228 | eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); |
229 | eeh_ops->configure_bridge(pe); | |
230 | eeh_pe_restore_bars(pe); | |
d99bb1db | 231 | |
ff477966 GS |
232 | pci_regs_buf[0] = 0; |
233 | eeh_pe_for_each_dev(pe, edev) { | |
234 | loglen += eeh_gather_pci_data(edev, pci_regs_buf, | |
235 | EEH_PCI_REGS_LOG_LEN); | |
236 | } | |
237 | ||
238 | eeh_ops->get_log(pe, severity, pci_regs_buf, loglen); | |
d99bb1db LV |
239 | } |
240 | ||
1da177e4 | 241 | /** |
cb3bc9d0 GS |
242 | * eeh_token_to_phys - Convert EEH address token to phys address |
243 | * @token: I/O token, should be address in the form 0xA.... | |
244 | * | |
245 | * This routine should be called to convert virtual I/O address | |
246 | * to physical one. | |
1da177e4 LT |
247 | */ |
248 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
249 | { | |
250 | pte_t *ptep; | |
251 | unsigned long pa; | |
252 | ||
20cee16c | 253 | ptep = find_linux_pte(init_mm.pgd, token); |
1da177e4 LT |
254 | if (!ptep) |
255 | return token; | |
256 | pa = pte_pfn(*ptep) << PAGE_SHIFT; | |
257 | ||
258 | return pa | (token & (PAGE_SIZE-1)); | |
259 | } | |
260 | ||
261 | /** | |
cb3bc9d0 GS |
262 | * eeh_dn_check_failure - Check if all 1's data is due to EEH slot freeze |
263 | * @dn: device node | |
264 | * @dev: pci device, if known | |
1da177e4 LT |
265 | * |
266 | * Check for an EEH failure for the given device node. Call this | |
267 | * routine if the result of a read was all 0xff's and you want to | |
268 | * find out if this is due to an EEH slot freeze. This routine | |
269 | * will query firmware for the EEH status. | |
270 | * | |
271 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 272 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
273 | * |
274 | * It is safe to call this routine in an interrupt context. | |
275 | */ | |
276 | int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev) | |
277 | { | |
278 | int ret; | |
1da177e4 | 279 | unsigned long flags; |
66523d9f | 280 | struct eeh_pe *pe; |
f631acd3 | 281 | struct eeh_dev *edev; |
fd761fd8 | 282 | int rc = 0; |
f36c5227 | 283 | const char *location; |
1da177e4 | 284 | |
e575f8db | 285 | eeh_stats.total_mmio_ffs++; |
1da177e4 LT |
286 | |
287 | if (!eeh_subsystem_enabled) | |
288 | return 0; | |
289 | ||
66523d9f GS |
290 | if (dn) { |
291 | edev = of_node_to_eeh_dev(dn); | |
292 | } else if (dev) { | |
293 | edev = pci_dev_to_eeh_dev(dev); | |
294 | dn = pci_device_to_OF_node(dev); | |
295 | } else { | |
e575f8db | 296 | eeh_stats.no_dn++; |
1da177e4 | 297 | return 0; |
177bc936 | 298 | } |
66523d9f | 299 | pe = edev->pe; |
1da177e4 LT |
300 | |
301 | /* Access to IO BARs might get this far and still not want checking. */ | |
66523d9f | 302 | if (!pe) { |
e575f8db | 303 | eeh_stats.ignored_check++; |
66523d9f GS |
304 | pr_debug("EEH: Ignored check for %s %s\n", |
305 | eeh_pci_name(dev), dn->full_name); | |
1da177e4 LT |
306 | return 0; |
307 | } | |
308 | ||
66523d9f | 309 | if (!pe->addr && !pe->config_addr) { |
e575f8db | 310 | eeh_stats.no_cfg_addr++; |
1da177e4 LT |
311 | return 0; |
312 | } | |
313 | ||
fd761fd8 LV |
314 | /* If we already have a pending isolation event for this |
315 | * slot, we know it's bad already, we don't need to check. | |
316 | * Do this checking under a lock; as multiple PCI devices | |
317 | * in one slot might report errors simultaneously, and we | |
318 | * only want one error recovery routine running. | |
1da177e4 | 319 | */ |
3d372628 | 320 | raw_spin_lock_irqsave(&confirm_error_lock, flags); |
fd761fd8 | 321 | rc = 1; |
66523d9f GS |
322 | if (pe->state & EEH_PE_ISOLATED) { |
323 | pe->check_count++; | |
324 | if (pe->check_count % EEH_MAX_FAILS == 0) { | |
f36c5227 | 325 | location = of_get_property(dn, "ibm,loc-code", NULL); |
cb3bc9d0 | 326 | printk(KERN_ERR "EEH: %d reads ignored for recovering device at " |
f36c5227 | 327 | "location=%s driver=%s pci addr=%s\n", |
66523d9f | 328 | pe->check_count, location, |
778a785f | 329 | eeh_driver_name(dev), eeh_pci_name(dev)); |
cb3bc9d0 | 330 | printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n", |
778a785f | 331 | eeh_driver_name(dev)); |
5c1344e9 | 332 | dump_stack(); |
1da177e4 | 333 | } |
fd761fd8 | 334 | goto dn_unlock; |
1da177e4 LT |
335 | } |
336 | ||
337 | /* | |
338 | * Now test for an EEH failure. This is VERY expensive. | |
339 | * Note that the eeh_config_addr may be a parent device | |
340 | * in the case of a device behind a bridge, or it may be | |
341 | * function zero of a multi-function device. | |
342 | * In any case they must share a common PHB. | |
343 | */ | |
66523d9f | 344 | ret = eeh_ops->get_state(pe, NULL); |
76e6faf7 | 345 | |
39d16e29 | 346 | /* Note that config-io to empty slots may fail; |
cb3bc9d0 | 347 | * they are empty when they don't have children. |
eb594a47 GS |
348 | * We will punt with the following conditions: Failure to get |
349 | * PE's state, EEH not support and Permanently unavailable | |
350 | * state, PE is in good state. | |
cb3bc9d0 | 351 | */ |
eb594a47 GS |
352 | if ((ret < 0) || |
353 | (ret == EEH_STATE_NOT_SUPPORT) || | |
354 | (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) == | |
355 | (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) { | |
e575f8db | 356 | eeh_stats.false_positives++; |
66523d9f | 357 | pe->false_positives++; |
fd761fd8 LV |
358 | rc = 0; |
359 | goto dn_unlock; | |
76e6faf7 LV |
360 | } |
361 | ||
e575f8db | 362 | eeh_stats.slot_resets++; |
fd761fd8 LV |
363 | |
364 | /* Avoid repeated reports of this failure, including problems | |
365 | * with other functions on this device, and functions under | |
cb3bc9d0 GS |
366 | * bridges. |
367 | */ | |
66523d9f | 368 | eeh_pe_state_mark(pe, EEH_PE_ISOLATED); |
3d372628 | 369 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); |
1da177e4 | 370 | |
66523d9f | 371 | eeh_send_failure_event(pe); |
77bd7415 | 372 | |
1da177e4 LT |
373 | /* Most EEH events are due to device driver bugs. Having |
374 | * a stack trace will help the device-driver authors figure | |
cb3bc9d0 GS |
375 | * out what happened. So print that out. |
376 | */ | |
14fb1fa6 | 377 | WARN(1, "EEH: failure detected\n"); |
fd761fd8 LV |
378 | return 1; |
379 | ||
380 | dn_unlock: | |
3d372628 | 381 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); |
fd761fd8 | 382 | return rc; |
1da177e4 LT |
383 | } |
384 | ||
fd761fd8 | 385 | EXPORT_SYMBOL_GPL(eeh_dn_check_failure); |
1da177e4 LT |
386 | |
387 | /** | |
cb3bc9d0 GS |
388 | * eeh_check_failure - Check if all 1's data is due to EEH slot freeze |
389 | * @token: I/O token, should be address in the form 0xA.... | |
390 | * @val: value, should be all 1's (XXX why do we need this arg??) | |
1da177e4 | 391 | * |
1da177e4 LT |
392 | * Check for an EEH failure at the given token address. Call this |
393 | * routine if the result of a read was all 0xff's and you want to | |
394 | * find out if this is due to an EEH slot freeze event. This routine | |
395 | * will query firmware for the EEH status. | |
396 | * | |
397 | * Note this routine is safe to call in an interrupt context. | |
398 | */ | |
399 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
400 | { | |
401 | unsigned long addr; | |
402 | struct pci_dev *dev; | |
403 | struct device_node *dn; | |
404 | ||
405 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
406 | addr = eeh_token_to_phys((unsigned long __force) token); | |
def9d83d | 407 | dev = pci_addr_cache_get_device(addr); |
177bc936 | 408 | if (!dev) { |
e575f8db | 409 | eeh_stats.no_device++; |
1da177e4 | 410 | return val; |
177bc936 | 411 | } |
1da177e4 LT |
412 | |
413 | dn = pci_device_to_OF_node(dev); | |
cb3bc9d0 | 414 | eeh_dn_check_failure(dn, dev); |
1da177e4 LT |
415 | |
416 | pci_dev_put(dev); | |
417 | return val; | |
418 | } | |
419 | ||
420 | EXPORT_SYMBOL(eeh_check_failure); | |
421 | ||
6dee3fb9 | 422 | |
47b5c838 | 423 | /** |
cce4b2d2 | 424 | * eeh_pci_enable - Enable MMIO or DMA transfers for this slot |
ff477966 | 425 | * @pe: EEH PE |
cb3bc9d0 GS |
426 | * |
427 | * This routine should be called to reenable frozen MMIO or DMA | |
428 | * so that it would work correctly again. It's useful while doing | |
429 | * recovery or log collection on the indicated device. | |
47b5c838 | 430 | */ |
ff477966 | 431 | int eeh_pci_enable(struct eeh_pe *pe, int function) |
47b5c838 | 432 | { |
47b5c838 LV |
433 | int rc; |
434 | ||
ff477966 | 435 | rc = eeh_ops->set_option(pe, function); |
47b5c838 | 436 | if (rc) |
ff477966 GS |
437 | pr_warning("%s: Unexpected state change %d on PHB#%d-PE#%x, err=%d\n", |
438 | __func__, function, pe->phb->global_number, pe->addr, rc); | |
47b5c838 | 439 | |
ff477966 | 440 | rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); |
eb594a47 GS |
441 | if (rc > 0 && (rc & EEH_STATE_MMIO_ENABLED) && |
442 | (function == EEH_OPT_THAW_MMIO)) | |
fa1be476 LV |
443 | return 0; |
444 | ||
47b5c838 LV |
445 | return rc; |
446 | } | |
447 | ||
00c2ae35 BK |
448 | /** |
449 | * pcibios_set_pcie_slot_reset - Set PCI-E reset state | |
cb3bc9d0 GS |
450 | * @dev: pci device struct |
451 | * @state: reset state to enter | |
00c2ae35 BK |
452 | * |
453 | * Return value: | |
454 | * 0 if success | |
cb3bc9d0 | 455 | */ |
00c2ae35 BK |
456 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) |
457 | { | |
458 | struct device_node *dn = pci_device_to_OF_node(dev); | |
00c2ae35 BK |
459 | |
460 | switch (state) { | |
461 | case pcie_deassert_reset: | |
2652481f | 462 | eeh_ops->reset(dn, EEH_RESET_DEACTIVATE); |
00c2ae35 BK |
463 | break; |
464 | case pcie_hot_reset: | |
2652481f | 465 | eeh_ops->reset(dn, EEH_RESET_HOT); |
00c2ae35 BK |
466 | break; |
467 | case pcie_warm_reset: | |
2652481f | 468 | eeh_ops->reset(dn, EEH_RESET_FUNDAMENTAL); |
00c2ae35 BK |
469 | break; |
470 | default: | |
471 | return -EINVAL; | |
472 | }; | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
cb5b5624 | 477 | /** |
cb3bc9d0 GS |
478 | * __eeh_set_pe_freset - Check the required reset for child devices |
479 | * @parent: parent device | |
480 | * @freset: return value | |
481 | * | |
482 | * Each device might have its preferred reset type: fundamental or | |
483 | * hot reset. The routine is used to collect the information from | |
484 | * the child devices so that they could be reset accordingly. | |
6dee3fb9 | 485 | */ |
cb3bc9d0 GS |
486 | void __eeh_set_pe_freset(struct device_node *parent, unsigned int *freset) |
487 | { | |
488 | struct device_node *dn; | |
489 | ||
490 | for_each_child_of_node(parent, dn) { | |
f631acd3 GS |
491 | if (of_node_to_eeh_dev(dn)) { |
492 | struct pci_dev *dev = of_node_to_eeh_dev(dn)->pdev; | |
cb3bc9d0 GS |
493 | |
494 | if (dev && dev->driver) | |
495 | *freset |= dev->needs_freset; | |
496 | ||
497 | __eeh_set_pe_freset(dn, freset); | |
498 | } | |
499 | } | |
500 | } | |
501 | ||
502 | /** | |
503 | * eeh_set_pe_freset - Check the required reset for the indicated device and its children | |
504 | * @dn: parent device | |
505 | * @freset: return value | |
506 | * | |
507 | * Each device might have its preferred reset type: fundamental or | |
508 | * hot reset. The routine is used to collected the information for | |
509 | * the indicated device and its children so that the bunch of the | |
510 | * devices could be reset properly. | |
511 | */ | |
512 | void eeh_set_pe_freset(struct device_node *dn, unsigned int *freset) | |
513 | { | |
514 | struct pci_dev *dev; | |
cce4b2d2 | 515 | dn = eeh_find_device_pe(dn); |
cb3bc9d0 GS |
516 | |
517 | /* Back up one, since config addrs might be shared */ | |
f631acd3 | 518 | if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent)) |
cb3bc9d0 | 519 | dn = dn->parent; |
6dee3fb9 | 520 | |
f631acd3 | 521 | dev = of_node_to_eeh_dev(dn)->pdev; |
cb3bc9d0 GS |
522 | if (dev) |
523 | *freset |= dev->needs_freset; | |
524 | ||
525 | __eeh_set_pe_freset(dn, freset); | |
526 | } | |
527 | ||
528 | /** | |
cce4b2d2 | 529 | * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second |
f631acd3 | 530 | * @edev: pci device node to be reset. |
cb3bc9d0 GS |
531 | * |
532 | * Assert the PCI #RST line for 1/4 second. | |
533 | */ | |
f631acd3 | 534 | static void eeh_reset_pe_once(struct eeh_dev *edev) |
6dee3fb9 | 535 | { |
308fc4f8 | 536 | unsigned int freset = 0; |
f631acd3 | 537 | struct device_node *dn = eeh_dev_to_of_node(edev); |
6e19314c | 538 | |
308fc4f8 RL |
539 | /* Determine type of EEH reset required for |
540 | * Partitionable Endpoint, a hot-reset (1) | |
541 | * or a fundamental reset (3). | |
542 | * A fundamental reset required by any device under | |
543 | * Partitionable Endpoint trumps hot-reset. | |
544 | */ | |
f631acd3 | 545 | eeh_set_pe_freset(dn, &freset); |
308fc4f8 RL |
546 | |
547 | if (freset) | |
f631acd3 | 548 | eeh_ops->reset(dn, EEH_RESET_FUNDAMENTAL); |
6e19314c | 549 | else |
f631acd3 | 550 | eeh_ops->reset(dn, EEH_RESET_HOT); |
6dee3fb9 LV |
551 | |
552 | /* The PCI bus requires that the reset be held high for at least | |
cb3bc9d0 GS |
553 | * a 100 milliseconds. We wait a bit longer 'just in case'. |
554 | */ | |
6dee3fb9 | 555 | #define PCI_BUS_RST_HOLD_TIME_MSEC 250 |
cb3bc9d0 | 556 | msleep(PCI_BUS_RST_HOLD_TIME_MSEC); |
d9564ad1 LV |
557 | |
558 | /* We might get hit with another EEH freeze as soon as the | |
559 | * pci slot reset line is dropped. Make sure we don't miss | |
cb3bc9d0 GS |
560 | * these, and clear the flag now. |
561 | */ | |
f631acd3 | 562 | eeh_clear_slot(dn, EEH_MODE_ISOLATED); |
d9564ad1 | 563 | |
f631acd3 | 564 | eeh_ops->reset(dn, EEH_RESET_DEACTIVATE); |
6dee3fb9 LV |
565 | |
566 | /* After a PCI slot has been reset, the PCI Express spec requires | |
567 | * a 1.5 second idle time for the bus to stabilize, before starting | |
cb3bc9d0 GS |
568 | * up traffic. |
569 | */ | |
6dee3fb9 | 570 | #define PCI_BUS_SETTLE_TIME_MSEC 1800 |
cb3bc9d0 | 571 | msleep(PCI_BUS_SETTLE_TIME_MSEC); |
e1029263 LV |
572 | } |
573 | ||
cb3bc9d0 | 574 | /** |
cce4b2d2 | 575 | * eeh_reset_pe - Reset the indicated PE |
f631acd3 | 576 | * @edev: PCI device associated EEH device |
cb3bc9d0 GS |
577 | * |
578 | * This routine should be called to reset indicated device, including | |
579 | * PE. A PE might include multiple PCI devices and sometimes PCI bridges | |
580 | * might be involved as well. | |
581 | */ | |
f631acd3 | 582 | int eeh_reset_pe(struct eeh_dev *edev) |
e1029263 LV |
583 | { |
584 | int i, rc; | |
f631acd3 | 585 | struct device_node *dn = eeh_dev_to_of_node(edev); |
e1029263 | 586 | |
9c547768 LV |
587 | /* Take three shots at resetting the bus */ |
588 | for (i=0; i<3; i++) { | |
f631acd3 | 589 | eeh_reset_pe_once(edev); |
6dee3fb9 | 590 | |
f631acd3 | 591 | rc = eeh_ops->wait_state(dn, PCI_BUS_RESET_WAIT_MSEC); |
eb594a47 | 592 | if (rc == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) |
b6495c0c | 593 | return 0; |
e1029263 | 594 | |
e1029263 | 595 | if (rc < 0) { |
12588da7 | 596 | printk(KERN_ERR "EEH: unrecoverable slot failure %s\n", |
f631acd3 | 597 | dn->full_name); |
b6495c0c | 598 | return -1; |
e1029263 | 599 | } |
12588da7 | 600 | printk(KERN_ERR "EEH: bus reset %d failed on slot %s, rc=%d\n", |
f631acd3 | 601 | i+1, dn->full_name, rc); |
6dee3fb9 | 602 | } |
b6495c0c | 603 | |
9c547768 | 604 | return -1; |
6dee3fb9 LV |
605 | } |
606 | ||
8b553f32 | 607 | /** |
cb3bc9d0 | 608 | * eeh_save_bars - Save device bars |
f631acd3 | 609 | * @edev: PCI device associated EEH device |
8b553f32 LV |
610 | * |
611 | * Save the values of the device bars. Unlike the restore | |
612 | * routine, this routine is *not* recursive. This is because | |
31116f0b | 613 | * PCI devices are added individually; but, for the restore, |
8b553f32 LV |
614 | * an entire slot is reset at a time. |
615 | */ | |
f631acd3 | 616 | static void eeh_save_bars(struct eeh_dev *edev) |
8b553f32 LV |
617 | { |
618 | int i; | |
f631acd3 | 619 | struct device_node *dn; |
8b553f32 | 620 | |
f631acd3 | 621 | if (!edev) |
8b553f32 | 622 | return; |
f631acd3 | 623 | dn = eeh_dev_to_of_node(edev); |
8b553f32 LV |
624 | |
625 | for (i = 0; i < 16; i++) | |
3780444c | 626 | eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]); |
8b553f32 LV |
627 | } |
628 | ||
cb3bc9d0 | 629 | /** |
cce4b2d2 | 630 | * eeh_early_enable - Early enable EEH on the indicated device |
cb3bc9d0 GS |
631 | * @dn: device node |
632 | * @data: BUID | |
633 | * | |
634 | * Enable EEH functionality on the specified PCI device. The function | |
635 | * is expected to be called before real PCI probing is done. However, | |
636 | * the PHBs have been initialized at this point. | |
637 | */ | |
cce4b2d2 | 638 | static void *eeh_early_enable(struct device_node *dn, void *data) |
1da177e4 | 639 | { |
1da177e4 | 640 | int ret; |
e2eb6392 SR |
641 | const u32 *class_code = of_get_property(dn, "class-code", NULL); |
642 | const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL); | |
643 | const u32 *device_id = of_get_property(dn, "device-id", NULL); | |
954a46e2 | 644 | const u32 *regs; |
1da177e4 | 645 | int enable; |
f631acd3 | 646 | struct eeh_dev *edev = of_node_to_eeh_dev(dn); |
371a395d | 647 | struct eeh_pe pe; |
1da177e4 | 648 | |
f631acd3 GS |
649 | edev->class_code = 0; |
650 | edev->mode = 0; | |
651 | edev->check_count = 0; | |
652 | edev->freeze_count = 0; | |
653 | edev->false_positives = 0; | |
1da177e4 | 654 | |
c6d4d5a8 NL |
655 | if (!of_device_is_available(dn)) |
656 | return NULL; | |
1da177e4 LT |
657 | |
658 | /* Ignore bad nodes. */ | |
659 | if (!class_code || !vendor_id || !device_id) | |
660 | return NULL; | |
661 | ||
662 | /* There is nothing to check on PCI to ISA bridges */ | |
663 | if (dn->type && !strcmp(dn->type, "isa")) { | |
f631acd3 | 664 | edev->mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
665 | return NULL; |
666 | } | |
f631acd3 | 667 | edev->class_code = *class_code; |
1da177e4 | 668 | |
1da177e4 | 669 | /* Ok... see if this device supports EEH. Some do, some don't, |
cb3bc9d0 GS |
670 | * and the only way to find out is to check each and every one. |
671 | */ | |
e2eb6392 | 672 | regs = of_get_property(dn, "reg", NULL); |
1da177e4 | 673 | if (regs) { |
371a395d GS |
674 | /* Initialize the fake PE */ |
675 | memset(&pe, 0, sizeof(struct eeh_pe)); | |
676 | pe.phb = edev->phb; | |
677 | pe.config_addr = regs[0]; | |
678 | ||
1da177e4 LT |
679 | /* First register entry is addr (00BBSS00) */ |
680 | /* Try to enable eeh */ | |
371a395d | 681 | ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE); |
172ca926 | 682 | |
25c4a46f | 683 | enable = 0; |
1da177e4 | 684 | if (ret == 0) { |
f631acd3 | 685 | edev->config_addr = regs[0]; |
25e591f6 LV |
686 | |
687 | /* If the newer, better, ibm,get-config-addr-info is supported, | |
cb3bc9d0 GS |
688 | * then use that instead. |
689 | */ | |
371a395d GS |
690 | edev->pe_config_addr = eeh_ops->get_pe_addr(&pe); |
691 | pe.addr = edev->pe_config_addr; | |
25c4a46f LV |
692 | |
693 | /* Some older systems (Power4) allow the | |
694 | * ibm,set-eeh-option call to succeed even on nodes | |
695 | * where EEH is not supported. Verify support | |
cb3bc9d0 GS |
696 | * explicitly. |
697 | */ | |
371a395d | 698 | ret = eeh_ops->get_state(&pe, NULL); |
eb594a47 | 699 | if (ret > 0 && ret != EEH_STATE_NOT_SUPPORT) |
25c4a46f LV |
700 | enable = 1; |
701 | } | |
702 | ||
703 | if (enable) { | |
704 | eeh_subsystem_enabled = 1; | |
f631acd3 | 705 | edev->mode |= EEH_MODE_SUPPORTED; |
25c4a46f | 706 | |
9b84348c GS |
707 | eeh_add_to_parent_pe(edev); |
708 | ||
57b066ff | 709 | pr_debug("EEH: %s: eeh enabled, config=%x pe_config=%x\n", |
f631acd3 GS |
710 | dn->full_name, edev->config_addr, |
711 | edev->pe_config_addr); | |
1da177e4 LT |
712 | } else { |
713 | ||
714 | /* This device doesn't support EEH, but it may have an | |
cb3bc9d0 GS |
715 | * EEH parent, in which case we mark it as supported. |
716 | */ | |
f631acd3 GS |
717 | if (dn->parent && of_node_to_eeh_dev(dn->parent) && |
718 | (of_node_to_eeh_dev(dn->parent)->mode & EEH_MODE_SUPPORTED)) { | |
1da177e4 | 719 | /* Parent supports EEH. */ |
f631acd3 GS |
720 | edev->mode |= EEH_MODE_SUPPORTED; |
721 | edev->config_addr = of_node_to_eeh_dev(dn->parent)->config_addr; | |
9b84348c GS |
722 | edev->pe_config_addr = of_node_to_eeh_dev(dn->parent)->pe_config_addr; |
723 | ||
724 | eeh_add_to_parent_pe(edev); | |
725 | ||
1da177e4 LT |
726 | return NULL; |
727 | } | |
728 | } | |
729 | } else { | |
730 | printk(KERN_WARNING "EEH: %s: unable to get reg property.\n", | |
731 | dn->full_name); | |
732 | } | |
733 | ||
f631acd3 | 734 | eeh_save_bars(edev); |
69376502 | 735 | return NULL; |
1da177e4 LT |
736 | } |
737 | ||
aa1e6374 GS |
738 | /** |
739 | * eeh_ops_register - Register platform dependent EEH operations | |
740 | * @ops: platform dependent EEH operations | |
741 | * | |
742 | * Register the platform dependent EEH operation callback | |
743 | * functions. The platform should call this function before | |
744 | * any other EEH operations. | |
745 | */ | |
746 | int __init eeh_ops_register(struct eeh_ops *ops) | |
747 | { | |
748 | if (!ops->name) { | |
749 | pr_warning("%s: Invalid EEH ops name for %p\n", | |
750 | __func__, ops); | |
751 | return -EINVAL; | |
752 | } | |
753 | ||
754 | if (eeh_ops && eeh_ops != ops) { | |
755 | pr_warning("%s: EEH ops of platform %s already existing (%s)\n", | |
756 | __func__, eeh_ops->name, ops->name); | |
757 | return -EEXIST; | |
758 | } | |
759 | ||
760 | eeh_ops = ops; | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | /** | |
766 | * eeh_ops_unregister - Unreigster platform dependent EEH operations | |
767 | * @name: name of EEH platform operations | |
768 | * | |
769 | * Unregister the platform dependent EEH operation callback | |
770 | * functions. | |
771 | */ | |
772 | int __exit eeh_ops_unregister(const char *name) | |
773 | { | |
774 | if (!name || !strlen(name)) { | |
775 | pr_warning("%s: Invalid EEH ops name\n", | |
776 | __func__); | |
777 | return -EINVAL; | |
778 | } | |
779 | ||
780 | if (eeh_ops && !strcmp(eeh_ops->name, name)) { | |
781 | eeh_ops = NULL; | |
782 | return 0; | |
783 | } | |
784 | ||
785 | return -EEXIST; | |
786 | } | |
787 | ||
cb3bc9d0 GS |
788 | /** |
789 | * eeh_init - EEH initialization | |
790 | * | |
1da177e4 LT |
791 | * Initialize EEH by trying to enable it for all of the adapters in the system. |
792 | * As a side effect we can determine here if eeh is supported at all. | |
793 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
794 | * check. If a user turns off EEH for a particular adapter they are really | |
795 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
796 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
797 | * EEH for all slots/all devices. | |
798 | * | |
799 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
800 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
801 | * newer systems can boot. | |
802 | */ | |
35e5cfe2 | 803 | static int __init eeh_init(void) |
1da177e4 | 804 | { |
1a5c2e63 GS |
805 | struct pci_controller *hose, *tmp; |
806 | struct device_node *phb; | |
e2af155c GS |
807 | int ret; |
808 | ||
809 | /* call platform initialization function */ | |
810 | if (!eeh_ops) { | |
811 | pr_warning("%s: Platform EEH operation not found\n", | |
812 | __func__); | |
35e5cfe2 | 813 | return -EEXIST; |
e2af155c GS |
814 | } else if ((ret = eeh_ops->init())) { |
815 | pr_warning("%s: Failed to call platform init function (%d)\n", | |
816 | __func__, ret); | |
35e5cfe2 | 817 | return ret; |
e2af155c | 818 | } |
1da177e4 | 819 | |
3d372628 | 820 | raw_spin_lock_init(&confirm_error_lock); |
df7242b1 | 821 | |
1a5c2e63 GS |
822 | /* Enable EEH for all adapters */ |
823 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
824 | phb = hose->dn; | |
c8c29b38 | 825 | traverse_pci_devices(phb, eeh_early_enable, NULL); |
1da177e4 LT |
826 | } |
827 | ||
828 | if (eeh_subsystem_enabled) | |
829 | printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n"); | |
830 | else | |
831 | printk(KERN_WARNING "EEH: No capable adapters found\n"); | |
35e5cfe2 GS |
832 | |
833 | return ret; | |
1da177e4 LT |
834 | } |
835 | ||
35e5cfe2 GS |
836 | core_initcall_sync(eeh_init); |
837 | ||
1da177e4 | 838 | /** |
cb3bc9d0 | 839 | * eeh_add_device_early - Enable EEH for the indicated device_node |
1da177e4 LT |
840 | * @dn: device node for which to set up EEH |
841 | * | |
842 | * This routine must be used to perform EEH initialization for PCI | |
843 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
844 | * This routine must be called before any i/o is performed to the | |
845 | * adapter (inluding any config-space i/o). | |
846 | * Whether this actually enables EEH or not for this device depends | |
847 | * on the CEC architecture, type of the device, on earlier boot | |
848 | * command-line arguments & etc. | |
849 | */ | |
794e085e | 850 | static void eeh_add_device_early(struct device_node *dn) |
1da177e4 LT |
851 | { |
852 | struct pci_controller *phb; | |
1da177e4 | 853 | |
f631acd3 | 854 | if (!dn || !of_node_to_eeh_dev(dn)) |
1da177e4 | 855 | return; |
f631acd3 | 856 | phb = of_node_to_eeh_dev(dn)->phb; |
f751f841 LV |
857 | |
858 | /* USB Bus children of PCI devices will not have BUID's */ | |
859 | if (NULL == phb || 0 == phb->buid) | |
1da177e4 | 860 | return; |
1da177e4 | 861 | |
c8c29b38 | 862 | eeh_early_enable(dn, NULL); |
1da177e4 | 863 | } |
1da177e4 | 864 | |
cb3bc9d0 GS |
865 | /** |
866 | * eeh_add_device_tree_early - Enable EEH for the indicated device | |
867 | * @dn: device node | |
868 | * | |
869 | * This routine must be used to perform EEH initialization for the | |
870 | * indicated PCI device that was added after system boot (e.g. | |
871 | * hotplug, dlpar). | |
872 | */ | |
e2a296ee LV |
873 | void eeh_add_device_tree_early(struct device_node *dn) |
874 | { | |
875 | struct device_node *sib; | |
acaa6176 SR |
876 | |
877 | for_each_child_of_node(dn, sib) | |
e2a296ee LV |
878 | eeh_add_device_tree_early(sib); |
879 | eeh_add_device_early(dn); | |
880 | } | |
881 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
882 | ||
1da177e4 | 883 | /** |
cb3bc9d0 | 884 | * eeh_add_device_late - Perform EEH initialization for the indicated pci device |
1da177e4 LT |
885 | * @dev: pci device for which to set up EEH |
886 | * | |
887 | * This routine must be used to complete EEH initialization for PCI | |
888 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
889 | */ | |
794e085e | 890 | static void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 891 | { |
56b0fca3 | 892 | struct device_node *dn; |
f631acd3 | 893 | struct eeh_dev *edev; |
56b0fca3 | 894 | |
1da177e4 LT |
895 | if (!dev || !eeh_subsystem_enabled) |
896 | return; | |
897 | ||
57b066ff | 898 | pr_debug("EEH: Adding device %s\n", pci_name(dev)); |
1da177e4 | 899 | |
56b0fca3 | 900 | dn = pci_device_to_OF_node(dev); |
2ef822c5 | 901 | edev = of_node_to_eeh_dev(dn); |
f631acd3 | 902 | if (edev->pdev == dev) { |
57b066ff BH |
903 | pr_debug("EEH: Already referenced !\n"); |
904 | return; | |
905 | } | |
f631acd3 | 906 | WARN_ON(edev->pdev); |
57b066ff | 907 | |
cb3bc9d0 | 908 | pci_dev_get(dev); |
f631acd3 GS |
909 | edev->pdev = dev; |
910 | dev->dev.archdata.edev = edev; | |
56b0fca3 | 911 | |
e1d04c97 LV |
912 | pci_addr_cache_insert_device(dev); |
913 | eeh_sysfs_add_device(dev); | |
1da177e4 | 914 | } |
794e085e | 915 | |
cb3bc9d0 GS |
916 | /** |
917 | * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus | |
918 | * @bus: PCI bus | |
919 | * | |
920 | * This routine must be used to perform EEH initialization for PCI | |
921 | * devices which are attached to the indicated PCI bus. The PCI bus | |
922 | * is added after system boot through hotplug or dlpar. | |
923 | */ | |
794e085e NF |
924 | void eeh_add_device_tree_late(struct pci_bus *bus) |
925 | { | |
926 | struct pci_dev *dev; | |
927 | ||
928 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
929 | eeh_add_device_late(dev); | |
930 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
931 | struct pci_bus *subbus = dev->subordinate; | |
932 | if (subbus) | |
933 | eeh_add_device_tree_late(subbus); | |
934 | } | |
935 | } | |
936 | } | |
937 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 LT |
938 | |
939 | /** | |
cb3bc9d0 | 940 | * eeh_remove_device - Undo EEH setup for the indicated pci device |
1da177e4 LT |
941 | * @dev: pci device to be removed |
942 | * | |
794e085e NF |
943 | * This routine should be called when a device is removed from |
944 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
945 | * the PCI device from the EEH subsystem. I/O errors affecting | |
946 | * this device will no longer be detected after this call; thus, | |
947 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 948 | */ |
794e085e | 949 | static void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 950 | { |
f631acd3 GS |
951 | struct eeh_dev *edev; |
952 | ||
1da177e4 LT |
953 | if (!dev || !eeh_subsystem_enabled) |
954 | return; | |
f631acd3 | 955 | edev = pci_dev_to_eeh_dev(dev); |
1da177e4 LT |
956 | |
957 | /* Unregister the device with the EEH/PCI address search system */ | |
57b066ff | 958 | pr_debug("EEH: Removing device %s\n", pci_name(dev)); |
56b0fca3 | 959 | |
f631acd3 | 960 | if (!edev || !edev->pdev) { |
57b066ff BH |
961 | pr_debug("EEH: Not referenced !\n"); |
962 | return; | |
b055a9e1 | 963 | } |
f631acd3 GS |
964 | edev->pdev = NULL; |
965 | dev->dev.archdata.edev = NULL; | |
cb3bc9d0 | 966 | pci_dev_put(dev); |
57b066ff | 967 | |
82e8882f | 968 | eeh_rmv_from_parent_pe(edev); |
57b066ff BH |
969 | pci_addr_cache_remove_device(dev); |
970 | eeh_sysfs_remove_device(dev); | |
1da177e4 | 971 | } |
1da177e4 | 972 | |
cb3bc9d0 GS |
973 | /** |
974 | * eeh_remove_bus_device - Undo EEH setup for the indicated PCI device | |
975 | * @dev: PCI device | |
976 | * | |
977 | * This routine must be called when a device is removed from the | |
978 | * running system through hotplug or dlpar. The corresponding | |
979 | * PCI address cache will be removed. | |
980 | */ | |
e2a296ee LV |
981 | void eeh_remove_bus_device(struct pci_dev *dev) |
982 | { | |
794e085e NF |
983 | struct pci_bus *bus = dev->subordinate; |
984 | struct pci_dev *child, *tmp; | |
985 | ||
e2a296ee | 986 | eeh_remove_device(dev); |
794e085e NF |
987 | |
988 | if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
989 | list_for_each_entry_safe(child, tmp, &bus->devices, bus_list) | |
990 | eeh_remove_bus_device(child); | |
e2a296ee LV |
991 | } |
992 | } | |
993 | EXPORT_SYMBOL_GPL(eeh_remove_bus_device); | |
994 | ||
1da177e4 LT |
995 | static int proc_eeh_show(struct seq_file *m, void *v) |
996 | { | |
1da177e4 LT |
997 | if (0 == eeh_subsystem_enabled) { |
998 | seq_printf(m, "EEH Subsystem is globally disabled\n"); | |
e575f8db | 999 | seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs); |
1da177e4 LT |
1000 | } else { |
1001 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 | 1002 | seq_printf(m, |
e575f8db GS |
1003 | "no device=%llu\n" |
1004 | "no device node=%llu\n" | |
1005 | "no config address=%llu\n" | |
1006 | "check not wanted=%llu\n" | |
1007 | "eeh_total_mmio_ffs=%llu\n" | |
1008 | "eeh_false_positives=%llu\n" | |
1009 | "eeh_slot_resets=%llu\n", | |
1010 | eeh_stats.no_device, | |
1011 | eeh_stats.no_dn, | |
1012 | eeh_stats.no_cfg_addr, | |
1013 | eeh_stats.ignored_check, | |
1014 | eeh_stats.total_mmio_ffs, | |
1015 | eeh_stats.false_positives, | |
1016 | eeh_stats.slot_resets); | |
1da177e4 LT |
1017 | } |
1018 | ||
1019 | return 0; | |
1020 | } | |
1021 | ||
1022 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1023 | { | |
1024 | return single_open(file, proc_eeh_show, NULL); | |
1025 | } | |
1026 | ||
5dfe4c96 | 1027 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1028 | .open = proc_eeh_open, |
1029 | .read = seq_read, | |
1030 | .llseek = seq_lseek, | |
1031 | .release = single_release, | |
1032 | }; | |
1033 | ||
1034 | static int __init eeh_init_proc(void) | |
1035 | { | |
66747138 | 1036 | if (machine_is(pseries)) |
8feaa434 | 1037 | proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations); |
1da177e4 LT |
1038 | return 0; |
1039 | } | |
1040 | __initcall(eeh_init_proc); |