Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * eeh.c | |
3c8c90ab LV |
3 | * Copyright IBM Corporation 2001, 2005, 2006 |
4 | * Copyright Dave Engebretsen & Todd Inglett 2001 | |
5 | * Copyright Linas Vepstas 2005, 2006 | |
69376502 | 6 | * |
1da177e4 LT |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
69376502 | 11 | * |
1da177e4 LT |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
69376502 | 16 | * |
1da177e4 LT |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
3c8c90ab LV |
20 | * |
21 | * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> | |
1da177e4 LT |
22 | */ |
23 | ||
57b066ff BH |
24 | #undef DEBUG |
25 | ||
6dee3fb9 | 26 | #include <linux/delay.h> |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/list.h> | |
1da177e4 LT |
29 | #include <linux/pci.h> |
30 | #include <linux/proc_fs.h> | |
31 | #include <linux/rbtree.h> | |
32 | #include <linux/seq_file.h> | |
33 | #include <linux/spinlock.h> | |
acaa6176 SR |
34 | #include <linux/of.h> |
35 | ||
69376502 | 36 | #include <asm/atomic.h> |
1da177e4 | 37 | #include <asm/eeh.h> |
172ca926 | 38 | #include <asm/eeh_event.h> |
1da177e4 LT |
39 | #include <asm/io.h> |
40 | #include <asm/machdep.h> | |
172ca926 | 41 | #include <asm/ppc-pci.h> |
1da177e4 | 42 | #include <asm/rtas.h> |
1da177e4 | 43 | |
1da177e4 LT |
44 | |
45 | /** Overview: | |
46 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
47 | * dealing with PCI bus errors that can't be dealt with within the | |
48 | * usual PCI framework, except by check-stopping the CPU. Systems | |
49 | * that are designed for high-availability/reliability cannot afford | |
50 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
51 | * An EEH-capable bridge operates by converting a detected error | |
52 | * into a "slot freeze", taking the PCI adapter off-line, making | |
53 | * the slot behave, from the OS'es point of view, as if the slot | |
54 | * were "empty": all reads return 0xff's and all writes are silently | |
55 | * ignored. EEH slot isolation events can be triggered by parity | |
56 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
57 | * which in turn might be caused by low voltage on the bus, dust, |
58 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
59 | * |
60 | * Note, however, that one of the leading causes of EEH slot | |
61 | * freeze events are buggy device drivers, buggy device microcode, | |
62 | * or buggy device hardware. This is because any attempt by the | |
63 | * device to bus-master data to a memory address that is not | |
64 | * assigned to the device will trigger a slot freeze. (The idea | |
65 | * is to prevent devices-gone-wild from corrupting system memory). | |
66 | * Buggy hardware/drivers will have a miserable time co-existing | |
67 | * with EEH. | |
68 | * | |
69 | * Ideally, a PCI device driver, when suspecting that an isolation | |
70 | * event has occured (e.g. by reading 0xff's), will then ask EEH | |
71 | * whether this is the case, and then take appropriate steps to | |
72 | * reset the PCI slot, the PCI device, and then resume operations. | |
73 | * However, until that day, the checking is done here, with the | |
74 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
75 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
76 | * and sent out for processing. | |
77 | */ | |
78 | ||
5c1344e9 | 79 | /* If a device driver keeps reading an MMIO register in an interrupt |
f36c5227 MM |
80 | * handler after a slot isolation event, it might be broken. |
81 | * This sets the threshold for how many read attempts we allow | |
82 | * before printing an error message. | |
1da177e4 | 83 | */ |
2fd30be8 | 84 | #define EEH_MAX_FAILS 2100000 |
1da177e4 | 85 | |
17213c3b | 86 | /* Time to wait for a PCI slot to report status, in milliseconds */ |
9c547768 LV |
87 | #define PCI_BUS_RESET_WAIT_MSEC (60*1000) |
88 | ||
1da177e4 LT |
89 | /* RTAS tokens */ |
90 | static int ibm_set_eeh_option; | |
91 | static int ibm_set_slot_reset; | |
92 | static int ibm_read_slot_reset_state; | |
93 | static int ibm_read_slot_reset_state2; | |
94 | static int ibm_slot_error_detail; | |
25e591f6 | 95 | static int ibm_get_config_addr_info; |
147d6a37 | 96 | static int ibm_get_config_addr_info2; |
21e464dd | 97 | static int ibm_configure_bridge; |
1da177e4 | 98 | |
1e28a7dd DW |
99 | int eeh_subsystem_enabled; |
100 | EXPORT_SYMBOL(eeh_subsystem_enabled); | |
1da177e4 | 101 | |
fd761fd8 LV |
102 | /* Lock to avoid races due to multiple reports of an error */ |
103 | static DEFINE_SPINLOCK(confirm_error_lock); | |
104 | ||
17213c3b LV |
105 | /* Buffer for reporting slot-error-detail rtas calls. Its here |
106 | * in BSS, and not dynamically alloced, so that it ends up in | |
107 | * RMO where RTAS can access it. | |
108 | */ | |
1da177e4 LT |
109 | static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX]; |
110 | static DEFINE_SPINLOCK(slot_errbuf_lock); | |
111 | static int eeh_error_buf_size; | |
112 | ||
17213c3b LV |
113 | /* Buffer for reporting pci register dumps. Its here in BSS, and |
114 | * not dynamically alloced, so that it ends up in RMO where RTAS | |
115 | * can access it. | |
116 | */ | |
d99bb1db LV |
117 | #define EEH_PCI_REGS_LOG_LEN 4096 |
118 | static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; | |
119 | ||
1da177e4 | 120 | /* System monitoring statistics */ |
257ffc64 LV |
121 | static unsigned long no_device; |
122 | static unsigned long no_dn; | |
123 | static unsigned long no_cfg_addr; | |
124 | static unsigned long ignored_check; | |
125 | static unsigned long total_mmio_ffs; | |
126 | static unsigned long false_positives; | |
257ffc64 | 127 | static unsigned long slot_resets; |
1da177e4 | 128 | |
7684b40c LV |
129 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
130 | ||
1da177e4 | 131 | /* --------------------------------------------------------------- */ |
5d5a0936 | 132 | /* Below lies the EEH event infrastructure */ |
1da177e4 | 133 | |
d99bb1db LV |
134 | static void rtas_slot_error_detail(struct pci_dn *pdn, int severity, |
135 | char *driver_log, size_t loglen) | |
df7242b1 | 136 | { |
fcb7543e | 137 | int config_addr; |
df7242b1 LV |
138 | unsigned long flags; |
139 | int rc; | |
140 | ||
141 | /* Log the error with the rtas logger */ | |
142 | spin_lock_irqsave(&slot_errbuf_lock, flags); | |
143 | memset(slot_errbuf, 0, eeh_error_buf_size); | |
144 | ||
fcb7543e LV |
145 | /* Use PE configuration address, if present */ |
146 | config_addr = pdn->eeh_config_addr; | |
147 | if (pdn->eeh_pe_config_addr) | |
148 | config_addr = pdn->eeh_pe_config_addr; | |
149 | ||
df7242b1 | 150 | rc = rtas_call(ibm_slot_error_detail, |
fcb7543e | 151 | 8, 1, NULL, config_addr, |
df7242b1 | 152 | BUID_HI(pdn->phb->buid), |
d99bb1db LV |
153 | BUID_LO(pdn->phb->buid), |
154 | virt_to_phys(driver_log), loglen, | |
df7242b1 LV |
155 | virt_to_phys(slot_errbuf), |
156 | eeh_error_buf_size, | |
157 | severity); | |
158 | ||
159 | if (rc == 0) | |
160 | log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0); | |
161 | spin_unlock_irqrestore(&slot_errbuf_lock, flags); | |
162 | } | |
163 | ||
d99bb1db LV |
164 | /** |
165 | * gather_pci_data - copy assorted PCI config space registers to buff | |
166 | * @pdn: device to report data for | |
167 | * @buf: point to buffer in which to log | |
168 | * @len: amount of room in buffer | |
169 | * | |
170 | * This routine captures assorted PCI configuration space data, | |
171 | * and puts them into a buffer for RTAS error logging. | |
172 | */ | |
173 | static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len) | |
174 | { | |
0b9369f4 | 175 | struct pci_dev *dev = pdn->pcidev; |
d99bb1db | 176 | u32 cfg; |
fcf9892b | 177 | int cap, i; |
d99bb1db LV |
178 | int n = 0; |
179 | ||
fcf9892b LV |
180 | n += scnprintf(buf+n, len-n, "%s\n", pdn->node->full_name); |
181 | printk(KERN_WARNING "EEH: of node=%s\n", pdn->node->full_name); | |
182 | ||
d99bb1db | 183 | rtas_read_config(pdn, PCI_VENDOR_ID, 4, &cfg); |
fcf9892b LV |
184 | n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); |
185 | printk(KERN_WARNING "EEH: PCI device/vendor: %08x\n", cfg); | |
186 | ||
d99bb1db LV |
187 | rtas_read_config(pdn, PCI_COMMAND, 4, &cfg); |
188 | n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); | |
fcf9892b LV |
189 | printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg); |
190 | ||
b37ceefe LV |
191 | if (!dev) { |
192 | printk(KERN_WARNING "EEH: no PCI device for this of node\n"); | |
193 | return n; | |
194 | } | |
195 | ||
0b9369f4 LV |
196 | /* Gather bridge-specific registers */ |
197 | if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) { | |
198 | rtas_read_config(pdn, PCI_SEC_STATUS, 2, &cfg); | |
199 | n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); | |
200 | printk(KERN_WARNING "EEH: Bridge secondary status: %04x\n", cfg); | |
201 | ||
202 | rtas_read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg); | |
203 | n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); | |
204 | printk(KERN_WARNING "EEH: Bridge control: %04x\n", cfg); | |
205 | } | |
206 | ||
fcf9892b | 207 | /* Dump out the PCI-X command and status regs */ |
b37ceefe | 208 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
fcf9892b LV |
209 | if (cap) { |
210 | rtas_read_config(pdn, cap, 4, &cfg); | |
211 | n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); | |
212 | printk(KERN_WARNING "EEH: PCI-X cmd: %08x\n", cfg); | |
213 | ||
214 | rtas_read_config(pdn, cap+4, 4, &cfg); | |
215 | n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); | |
216 | printk(KERN_WARNING "EEH: PCI-X status: %08x\n", cfg); | |
217 | } | |
218 | ||
219 | /* If PCI-E capable, dump PCI-E cap 10, and the AER */ | |
b37ceefe | 220 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); |
fcf9892b LV |
221 | if (cap) { |
222 | n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); | |
223 | printk(KERN_WARNING | |
224 | "EEH: PCI-E capabilities and status follow:\n"); | |
225 | ||
226 | for (i=0; i<=8; i++) { | |
227 | rtas_read_config(pdn, cap+4*i, 4, &cfg); | |
228 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
229 | printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg); | |
230 | } | |
231 | ||
b37ceefe | 232 | cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |
fcf9892b LV |
233 | if (cap) { |
234 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); | |
235 | printk(KERN_WARNING | |
236 | "EEH: PCI-E AER capability register set follows:\n"); | |
237 | ||
238 | for (i=0; i<14; i++) { | |
239 | rtas_read_config(pdn, cap+4*i, 4, &cfg); | |
240 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
241 | printk(KERN_WARNING "EEH: PCI-E AER %02x: %08x\n", i, cfg); | |
242 | } | |
243 | } | |
244 | } | |
0b9369f4 LV |
245 | |
246 | /* Gather status on devices under the bridge */ | |
247 | if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) { | |
acaa6176 SR |
248 | struct device_node *dn; |
249 | ||
250 | for_each_child_of_node(pdn->node, dn) { | |
0b9369f4 LV |
251 | pdn = PCI_DN(dn); |
252 | if (pdn) | |
253 | n += gather_pci_data(pdn, buf+n, len-n); | |
0b9369f4 LV |
254 | } |
255 | } | |
256 | ||
d99bb1db LV |
257 | return n; |
258 | } | |
259 | ||
260 | void eeh_slot_error_detail(struct pci_dn *pdn, int severity) | |
261 | { | |
262 | size_t loglen = 0; | |
17213c3b | 263 | pci_regs_buf[0] = 0; |
d99bb1db LV |
264 | |
265 | rtas_pci_enable(pdn, EEH_THAW_MMIO); | |
266 | loglen = gather_pci_data(pdn, pci_regs_buf, EEH_PCI_REGS_LOG_LEN); | |
267 | ||
268 | rtas_slot_error_detail(pdn, severity, pci_regs_buf, loglen); | |
269 | } | |
270 | ||
1da177e4 LT |
271 | /** |
272 | * read_slot_reset_state - Read the reset state of a device node's slot | |
273 | * @dn: device node to read | |
274 | * @rets: array to return results in | |
275 | */ | |
69376502 | 276 | static int read_slot_reset_state(struct pci_dn *pdn, int rets[]) |
1da177e4 LT |
277 | { |
278 | int token, outputs; | |
fcb7543e | 279 | int config_addr; |
1da177e4 LT |
280 | |
281 | if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) { | |
282 | token = ibm_read_slot_reset_state2; | |
283 | outputs = 4; | |
284 | } else { | |
285 | token = ibm_read_slot_reset_state; | |
69376502 | 286 | rets[2] = 0; /* fake PE Unavailable info */ |
1da177e4 LT |
287 | outputs = 3; |
288 | } | |
289 | ||
fcb7543e LV |
290 | /* Use PE configuration address, if present */ |
291 | config_addr = pdn->eeh_config_addr; | |
292 | if (pdn->eeh_pe_config_addr) | |
293 | config_addr = pdn->eeh_pe_config_addr; | |
294 | ||
295 | return rtas_call(token, 3, outputs, rets, config_addr, | |
1635317f | 296 | BUID_HI(pdn->phb->buid), BUID_LO(pdn->phb->buid)); |
1da177e4 LT |
297 | } |
298 | ||
9c547768 LV |
299 | /** |
300 | * eeh_wait_for_slot_status - returns error status of slot | |
301 | * @pdn pci device node | |
302 | * @max_wait_msecs maximum number to millisecs to wait | |
303 | * | |
304 | * Return negative value if a permanent error, else return | |
305 | * Partition Endpoint (PE) status value. | |
306 | * | |
307 | * If @max_wait_msecs is positive, then this routine will | |
308 | * sleep until a valid status can be obtained, or until | |
309 | * the max allowed wait time is exceeded, in which case | |
310 | * a -2 is returned. | |
311 | */ | |
312 | int | |
313 | eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs) | |
314 | { | |
315 | int rc; | |
316 | int rets[3]; | |
317 | int mwait; | |
318 | ||
319 | while (1) { | |
320 | rc = read_slot_reset_state(pdn, rets); | |
321 | if (rc) return rc; | |
322 | if (rets[1] == 0) return -1; /* EEH is not supported */ | |
323 | ||
324 | if (rets[0] != 5) return rets[0]; /* return actual status */ | |
325 | ||
326 | if (rets[2] == 0) return -1; /* permanently unavailable */ | |
327 | ||
2c84b407 | 328 | if (max_wait_msecs <= 0) break; |
9c547768 LV |
329 | |
330 | mwait = rets[2]; | |
331 | if (mwait <= 0) { | |
332 | printk (KERN_WARNING | |
333 | "EEH: Firmware returned bad wait value=%d\n", mwait); | |
334 | mwait = 1000; | |
335 | } else if (mwait > 300*1000) { | |
336 | printk (KERN_WARNING | |
337 | "EEH: Firmware is taking too long, time=%d\n", mwait); | |
338 | mwait = 300*1000; | |
339 | } | |
340 | max_wait_msecs -= mwait; | |
341 | msleep (mwait); | |
342 | } | |
343 | ||
344 | printk(KERN_WARNING "EEH: Timed out waiting for slot status\n"); | |
345 | return -2; | |
346 | } | |
347 | ||
1da177e4 LT |
348 | /** |
349 | * eeh_token_to_phys - convert EEH address token to phys address | |
69376502 | 350 | * @token i/o token, should be address in the form 0xA.... |
1da177e4 LT |
351 | */ |
352 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
353 | { | |
354 | pte_t *ptep; | |
355 | unsigned long pa; | |
356 | ||
20cee16c | 357 | ptep = find_linux_pte(init_mm.pgd, token); |
1da177e4 LT |
358 | if (!ptep) |
359 | return token; | |
360 | pa = pte_pfn(*ptep) << PAGE_SHIFT; | |
361 | ||
362 | return pa | (token & (PAGE_SIZE-1)); | |
363 | } | |
364 | ||
fd761fd8 LV |
365 | /** |
366 | * Return the "partitionable endpoint" (pe) under which this device lies | |
367 | */ | |
9fb40eb8 | 368 | struct device_node * find_device_pe(struct device_node *dn) |
fd761fd8 LV |
369 | { |
370 | while ((dn->parent) && PCI_DN(dn->parent) && | |
371 | (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) { | |
372 | dn = dn->parent; | |
373 | } | |
374 | return dn; | |
375 | } | |
376 | ||
acaa6176 | 377 | /** Mark all devices that are children of this device as failed. |
fd761fd8 LV |
378 | * Mark the device driver too, so that it can see the failure |
379 | * immediately; this is critical, since some drivers poll | |
380 | * status registers in interrupts ... If a driver is polling, | |
381 | * and the slot is frozen, then the driver can deadlock in | |
382 | * an interrupt context, which is bad. | |
383 | */ | |
384 | ||
acaa6176 | 385 | static void __eeh_mark_slot(struct device_node *parent, int mode_flag) |
fd761fd8 | 386 | { |
acaa6176 SR |
387 | struct device_node *dn; |
388 | ||
389 | for_each_child_of_node(parent, dn) { | |
d9564ad1 | 390 | if (PCI_DN(dn)) { |
77bd7415 LV |
391 | /* Mark the pci device driver too */ |
392 | struct pci_dev *dev = PCI_DN(dn)->pcidev; | |
ea183a95 OJ |
393 | |
394 | PCI_DN(dn)->eeh_mode |= mode_flag; | |
395 | ||
77bd7415 LV |
396 | if (dev && dev->driver) |
397 | dev->error_state = pci_channel_io_frozen; | |
398 | ||
acaa6176 | 399 | __eeh_mark_slot(dn, mode_flag); |
d9564ad1 | 400 | } |
fd761fd8 LV |
401 | } |
402 | } | |
403 | ||
d9564ad1 LV |
404 | void eeh_mark_slot (struct device_node *dn, int mode_flag) |
405 | { | |
022d51b1 | 406 | struct pci_dev *dev; |
d9564ad1 | 407 | dn = find_device_pe (dn); |
3914ac7b LV |
408 | |
409 | /* Back up one, since config addrs might be shared */ | |
4980d5eb | 410 | if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent)) |
3914ac7b LV |
411 | dn = dn->parent; |
412 | ||
d9564ad1 | 413 | PCI_DN(dn)->eeh_mode |= mode_flag; |
022d51b1 LV |
414 | |
415 | /* Mark the pci device too */ | |
416 | dev = PCI_DN(dn)->pcidev; | |
417 | if (dev) | |
418 | dev->error_state = pci_channel_io_frozen; | |
419 | ||
acaa6176 | 420 | __eeh_mark_slot(dn, mode_flag); |
d9564ad1 LV |
421 | } |
422 | ||
acaa6176 | 423 | static void __eeh_clear_slot(struct device_node *parent, int mode_flag) |
fd761fd8 | 424 | { |
acaa6176 SR |
425 | struct device_node *dn; |
426 | ||
427 | for_each_child_of_node(parent, dn) { | |
d9564ad1 LV |
428 | if (PCI_DN(dn)) { |
429 | PCI_DN(dn)->eeh_mode &= ~mode_flag; | |
430 | PCI_DN(dn)->eeh_check_count = 0; | |
acaa6176 | 431 | __eeh_clear_slot(dn, mode_flag); |
d9564ad1 | 432 | } |
fd761fd8 LV |
433 | } |
434 | } | |
435 | ||
d9564ad1 | 436 | void eeh_clear_slot (struct device_node *dn, int mode_flag) |
fd761fd8 LV |
437 | { |
438 | unsigned long flags; | |
439 | spin_lock_irqsave(&confirm_error_lock, flags); | |
3914ac7b | 440 | |
d9564ad1 | 441 | dn = find_device_pe (dn); |
3914ac7b LV |
442 | |
443 | /* Back up one, since config addrs might be shared */ | |
4980d5eb | 444 | if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent)) |
3914ac7b LV |
445 | dn = dn->parent; |
446 | ||
d9564ad1 LV |
447 | PCI_DN(dn)->eeh_mode &= ~mode_flag; |
448 | PCI_DN(dn)->eeh_check_count = 0; | |
acaa6176 | 449 | __eeh_clear_slot(dn, mode_flag); |
fd761fd8 LV |
450 | spin_unlock_irqrestore(&confirm_error_lock, flags); |
451 | } | |
452 | ||
1da177e4 LT |
453 | /** |
454 | * eeh_dn_check_failure - check if all 1's data is due to EEH slot freeze | |
455 | * @dn device node | |
456 | * @dev pci device, if known | |
457 | * | |
458 | * Check for an EEH failure for the given device node. Call this | |
459 | * routine if the result of a read was all 0xff's and you want to | |
460 | * find out if this is due to an EEH slot freeze. This routine | |
461 | * will query firmware for the EEH status. | |
462 | * | |
463 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 464 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
465 | * |
466 | * It is safe to call this routine in an interrupt context. | |
467 | */ | |
468 | int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev) | |
469 | { | |
470 | int ret; | |
471 | int rets[3]; | |
472 | unsigned long flags; | |
1635317f | 473 | struct pci_dn *pdn; |
fd761fd8 | 474 | int rc = 0; |
f36c5227 | 475 | const char *location; |
1da177e4 | 476 | |
257ffc64 | 477 | total_mmio_ffs++; |
1da177e4 LT |
478 | |
479 | if (!eeh_subsystem_enabled) | |
480 | return 0; | |
481 | ||
177bc936 | 482 | if (!dn) { |
257ffc64 | 483 | no_dn++; |
1da177e4 | 484 | return 0; |
177bc936 | 485 | } |
307d46e8 | 486 | dn = find_device_pe(dn); |
69376502 | 487 | pdn = PCI_DN(dn); |
1da177e4 LT |
488 | |
489 | /* Access to IO BARs might get this far and still not want checking. */ | |
f8632c82 | 490 | if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) || |
1635317f | 491 | pdn->eeh_mode & EEH_MODE_NOCHECK) { |
257ffc64 | 492 | ignored_check++; |
57b066ff BH |
493 | pr_debug("EEH: Ignored check (%x) for %s %s\n", |
494 | pdn->eeh_mode, pci_name (dev), dn->full_name); | |
1da177e4 LT |
495 | return 0; |
496 | } | |
497 | ||
fcb7543e | 498 | if (!pdn->eeh_config_addr && !pdn->eeh_pe_config_addr) { |
257ffc64 | 499 | no_cfg_addr++; |
1da177e4 LT |
500 | return 0; |
501 | } | |
502 | ||
fd761fd8 LV |
503 | /* If we already have a pending isolation event for this |
504 | * slot, we know it's bad already, we don't need to check. | |
505 | * Do this checking under a lock; as multiple PCI devices | |
506 | * in one slot might report errors simultaneously, and we | |
507 | * only want one error recovery routine running. | |
1da177e4 | 508 | */ |
fd761fd8 LV |
509 | spin_lock_irqsave(&confirm_error_lock, flags); |
510 | rc = 1; | |
1635317f | 511 | if (pdn->eeh_mode & EEH_MODE_ISOLATED) { |
5c1344e9 | 512 | pdn->eeh_check_count ++; |
f36c5227 MM |
513 | if (pdn->eeh_check_count % EEH_MAX_FAILS == 0) { |
514 | location = of_get_property(dn, "ibm,loc-code", NULL); | |
515 | printk (KERN_ERR "EEH: %d reads ignored for recovering device at " | |
516 | "location=%s driver=%s pci addr=%s\n", | |
517 | pdn->eeh_check_count, location, | |
518 | dev->driver->name, pci_name(dev)); | |
519 | printk (KERN_ERR "EEH: Might be infinite loop in %s driver\n", | |
520 | dev->driver->name); | |
5c1344e9 | 521 | dump_stack(); |
1da177e4 | 522 | } |
fd761fd8 | 523 | goto dn_unlock; |
1da177e4 LT |
524 | } |
525 | ||
526 | /* | |
527 | * Now test for an EEH failure. This is VERY expensive. | |
528 | * Note that the eeh_config_addr may be a parent device | |
529 | * in the case of a device behind a bridge, or it may be | |
530 | * function zero of a multi-function device. | |
531 | * In any case they must share a common PHB. | |
532 | */ | |
69376502 | 533 | ret = read_slot_reset_state(pdn, rets); |
76e6faf7 LV |
534 | |
535 | /* If the call to firmware failed, punt */ | |
536 | if (ret != 0) { | |
537 | printk(KERN_WARNING "EEH: read_slot_reset_state() failed; rc=%d dn=%s\n", | |
538 | ret, dn->full_name); | |
257ffc64 | 539 | false_positives++; |
858955bd | 540 | pdn->eeh_false_positives ++; |
fd761fd8 LV |
541 | rc = 0; |
542 | goto dn_unlock; | |
76e6faf7 LV |
543 | } |
544 | ||
39d16e29 LV |
545 | /* Note that config-io to empty slots may fail; |
546 | * they are empty when they don't have children. */ | |
c9b65a7d | 547 | if ((rets[0] == 5) && (rets[2] == 0) && (dn->child == NULL)) { |
39d16e29 | 548 | false_positives++; |
858955bd | 549 | pdn->eeh_false_positives ++; |
39d16e29 LV |
550 | rc = 0; |
551 | goto dn_unlock; | |
552 | } | |
553 | ||
76e6faf7 LV |
554 | /* If EEH is not supported on this device, punt. */ |
555 | if (rets[1] != 1) { | |
556 | printk(KERN_WARNING "EEH: event on unsupported device, rc=%d dn=%s\n", | |
557 | ret, dn->full_name); | |
257ffc64 | 558 | false_positives++; |
858955bd | 559 | pdn->eeh_false_positives ++; |
fd761fd8 LV |
560 | rc = 0; |
561 | goto dn_unlock; | |
76e6faf7 LV |
562 | } |
563 | ||
564 | /* If not the kind of error we know about, punt. */ | |
90375f53 | 565 | if (rets[0] != 1 && rets[0] != 2 && rets[0] != 4 && rets[0] != 5) { |
257ffc64 | 566 | false_positives++; |
858955bd | 567 | pdn->eeh_false_positives ++; |
fd761fd8 LV |
568 | rc = 0; |
569 | goto dn_unlock; | |
76e6faf7 LV |
570 | } |
571 | ||
257ffc64 | 572 | slot_resets++; |
fd761fd8 LV |
573 | |
574 | /* Avoid repeated reports of this failure, including problems | |
575 | * with other functions on this device, and functions under | |
576 | * bridges. */ | |
d9564ad1 | 577 | eeh_mark_slot (dn, EEH_MODE_ISOLATED); |
fd761fd8 | 578 | spin_unlock_irqrestore(&confirm_error_lock, flags); |
1da177e4 | 579 | |
d0ab95ca | 580 | eeh_send_failure_event (dn, dev); |
77bd7415 | 581 | |
1da177e4 LT |
582 | /* Most EEH events are due to device driver bugs. Having |
583 | * a stack trace will help the device-driver authors figure | |
584 | * out what happened. So print that out. */ | |
90375f53 | 585 | dump_stack(); |
fd761fd8 LV |
586 | return 1; |
587 | ||
588 | dn_unlock: | |
589 | spin_unlock_irqrestore(&confirm_error_lock, flags); | |
590 | return rc; | |
1da177e4 LT |
591 | } |
592 | ||
fd761fd8 | 593 | EXPORT_SYMBOL_GPL(eeh_dn_check_failure); |
1da177e4 LT |
594 | |
595 | /** | |
596 | * eeh_check_failure - check if all 1's data is due to EEH slot freeze | |
597 | * @token i/o token, should be address in the form 0xA.... | |
598 | * @val value, should be all 1's (XXX why do we need this arg??) | |
599 | * | |
1da177e4 LT |
600 | * Check for an EEH failure at the given token address. Call this |
601 | * routine if the result of a read was all 0xff's and you want to | |
602 | * find out if this is due to an EEH slot freeze event. This routine | |
603 | * will query firmware for the EEH status. | |
604 | * | |
605 | * Note this routine is safe to call in an interrupt context. | |
606 | */ | |
607 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
608 | { | |
609 | unsigned long addr; | |
610 | struct pci_dev *dev; | |
611 | struct device_node *dn; | |
612 | ||
613 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
614 | addr = eeh_token_to_phys((unsigned long __force) token); | |
615 | dev = pci_get_device_by_addr(addr); | |
177bc936 | 616 | if (!dev) { |
257ffc64 | 617 | no_device++; |
1da177e4 | 618 | return val; |
177bc936 | 619 | } |
1da177e4 LT |
620 | |
621 | dn = pci_device_to_OF_node(dev); | |
622 | eeh_dn_check_failure (dn, dev); | |
623 | ||
624 | pci_dev_put(dev); | |
625 | return val; | |
626 | } | |
627 | ||
628 | EXPORT_SYMBOL(eeh_check_failure); | |
629 | ||
6dee3fb9 LV |
630 | /* ------------------------------------------------------------- */ |
631 | /* The code below deals with error recovery */ | |
632 | ||
47b5c838 LV |
633 | /** |
634 | * rtas_pci_enable - enable MMIO or DMA transfers for this slot | |
635 | * @pdn pci device node | |
636 | */ | |
637 | ||
638 | int | |
639 | rtas_pci_enable(struct pci_dn *pdn, int function) | |
640 | { | |
641 | int config_addr; | |
642 | int rc; | |
643 | ||
644 | /* Use PE configuration address, if present */ | |
645 | config_addr = pdn->eeh_config_addr; | |
646 | if (pdn->eeh_pe_config_addr) | |
647 | config_addr = pdn->eeh_pe_config_addr; | |
648 | ||
649 | rc = rtas_call(ibm_set_eeh_option, 4, 1, NULL, | |
650 | config_addr, | |
651 | BUID_HI(pdn->phb->buid), | |
652 | BUID_LO(pdn->phb->buid), | |
653 | function); | |
654 | ||
655 | if (rc) | |
fa1be476 | 656 | printk(KERN_WARNING "EEH: Unexpected state change %d, err=%d dn=%s\n", |
47b5c838 LV |
657 | function, rc, pdn->node->full_name); |
658 | ||
fa1be476 LV |
659 | rc = eeh_wait_for_slot_status (pdn, PCI_BUS_RESET_WAIT_MSEC); |
660 | if ((rc == 4) && (function == EEH_THAW_MMIO)) | |
661 | return 0; | |
662 | ||
47b5c838 LV |
663 | return rc; |
664 | } | |
665 | ||
cb5b5624 LV |
666 | /** |
667 | * rtas_pci_slot_reset - raises/lowers the pci #RST line | |
668 | * @pdn pci device node | |
669 | * @state: 1/0 to raise/lower the #RST | |
6dee3fb9 LV |
670 | * |
671 | * Clear the EEH-frozen condition on a slot. This routine | |
672 | * asserts the PCI #RST line if the 'state' argument is '1', | |
673 | * and drops the #RST line if 'state is '0'. This routine is | |
674 | * safe to call in an interrupt context. | |
675 | * | |
676 | */ | |
677 | ||
678 | static void | |
679 | rtas_pci_slot_reset(struct pci_dn *pdn, int state) | |
680 | { | |
25e591f6 | 681 | int config_addr; |
6dee3fb9 LV |
682 | int rc; |
683 | ||
684 | BUG_ON (pdn==NULL); | |
685 | ||
686 | if (!pdn->phb) { | |
687 | printk (KERN_WARNING "EEH: in slot reset, device node %s has no phb\n", | |
688 | pdn->node->full_name); | |
689 | return; | |
690 | } | |
691 | ||
25e591f6 LV |
692 | /* Use PE configuration address, if present */ |
693 | config_addr = pdn->eeh_config_addr; | |
694 | if (pdn->eeh_pe_config_addr) | |
695 | config_addr = pdn->eeh_pe_config_addr; | |
696 | ||
6dee3fb9 | 697 | rc = rtas_call(ibm_set_slot_reset,4,1, NULL, |
25e591f6 | 698 | config_addr, |
6dee3fb9 LV |
699 | BUID_HI(pdn->phb->buid), |
700 | BUID_LO(pdn->phb->buid), | |
701 | state); | |
e1029263 LV |
702 | if (rc) |
703 | printk (KERN_WARNING "EEH: Unable to reset the failed slot," | |
704 | " (%d) #RST=%d dn=%s\n", | |
6dee3fb9 | 705 | rc, state, pdn->node->full_name); |
6dee3fb9 LV |
706 | } |
707 | ||
00c2ae35 BK |
708 | /** |
709 | * pcibios_set_pcie_slot_reset - Set PCI-E reset state | |
710 | * @dev: pci device struct | |
711 | * @state: reset state to enter | |
712 | * | |
713 | * Return value: | |
714 | * 0 if success | |
715 | **/ | |
716 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
717 | { | |
718 | struct device_node *dn = pci_device_to_OF_node(dev); | |
719 | struct pci_dn *pdn = PCI_DN(dn); | |
720 | ||
721 | switch (state) { | |
722 | case pcie_deassert_reset: | |
723 | rtas_pci_slot_reset(pdn, 0); | |
724 | break; | |
725 | case pcie_hot_reset: | |
726 | rtas_pci_slot_reset(pdn, 1); | |
727 | break; | |
728 | case pcie_warm_reset: | |
729 | rtas_pci_slot_reset(pdn, 3); | |
730 | break; | |
731 | default: | |
732 | return -EINVAL; | |
733 | }; | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
cb5b5624 LV |
738 | /** |
739 | * rtas_set_slot_reset -- assert the pci #RST line for 1/4 second | |
740 | * @pdn: pci device node to be reset. | |
b6495c0c LV |
741 | * |
742 | * Return 0 if success, else a non-zero value. | |
6dee3fb9 LV |
743 | */ |
744 | ||
e1029263 | 745 | static void __rtas_set_slot_reset(struct pci_dn *pdn) |
6dee3fb9 | 746 | { |
6dee3fb9 LV |
747 | rtas_pci_slot_reset (pdn, 1); |
748 | ||
749 | /* The PCI bus requires that the reset be held high for at least | |
750 | * a 100 milliseconds. We wait a bit longer 'just in case'. */ | |
751 | ||
752 | #define PCI_BUS_RST_HOLD_TIME_MSEC 250 | |
753 | msleep (PCI_BUS_RST_HOLD_TIME_MSEC); | |
d9564ad1 LV |
754 | |
755 | /* We might get hit with another EEH freeze as soon as the | |
756 | * pci slot reset line is dropped. Make sure we don't miss | |
757 | * these, and clear the flag now. */ | |
758 | eeh_clear_slot (pdn->node, EEH_MODE_ISOLATED); | |
759 | ||
6dee3fb9 LV |
760 | rtas_pci_slot_reset (pdn, 0); |
761 | ||
762 | /* After a PCI slot has been reset, the PCI Express spec requires | |
763 | * a 1.5 second idle time for the bus to stabilize, before starting | |
764 | * up traffic. */ | |
765 | #define PCI_BUS_SETTLE_TIME_MSEC 1800 | |
766 | msleep (PCI_BUS_SETTLE_TIME_MSEC); | |
e1029263 LV |
767 | } |
768 | ||
769 | int rtas_set_slot_reset(struct pci_dn *pdn) | |
770 | { | |
771 | int i, rc; | |
772 | ||
9c547768 LV |
773 | /* Take three shots at resetting the bus */ |
774 | for (i=0; i<3; i++) { | |
775 | __rtas_set_slot_reset(pdn); | |
6dee3fb9 | 776 | |
9c547768 | 777 | rc = eeh_wait_for_slot_status(pdn, PCI_BUS_RESET_WAIT_MSEC); |
b6495c0c LV |
778 | if (rc == 0) |
779 | return 0; | |
e1029263 | 780 | |
e1029263 | 781 | if (rc < 0) { |
12588da7 LV |
782 | printk(KERN_ERR "EEH: unrecoverable slot failure %s\n", |
783 | pdn->node->full_name); | |
b6495c0c | 784 | return -1; |
e1029263 | 785 | } |
12588da7 LV |
786 | printk(KERN_ERR "EEH: bus reset %d failed on slot %s, rc=%d\n", |
787 | i+1, pdn->node->full_name, rc); | |
6dee3fb9 | 788 | } |
b6495c0c | 789 | |
9c547768 | 790 | return -1; |
6dee3fb9 LV |
791 | } |
792 | ||
8b553f32 LV |
793 | /* ------------------------------------------------------- */ |
794 | /** Save and restore of PCI BARs | |
795 | * | |
796 | * Although firmware will set up BARs during boot, it doesn't | |
797 | * set up device BAR's after a device reset, although it will, | |
798 | * if requested, set up bridge configuration. Thus, we need to | |
799 | * configure the PCI devices ourselves. | |
800 | */ | |
801 | ||
802 | /** | |
803 | * __restore_bars - Restore the Base Address Registers | |
cb5b5624 LV |
804 | * @pdn: pci device node |
805 | * | |
8b553f32 LV |
806 | * Loads the PCI configuration space base address registers, |
807 | * the expansion ROM base address, the latency timer, and etc. | |
808 | * from the saved values in the device node. | |
809 | */ | |
810 | static inline void __restore_bars (struct pci_dn *pdn) | |
811 | { | |
812 | int i; | |
cde274c0 | 813 | u32 cmd; |
8b553f32 LV |
814 | |
815 | if (NULL==pdn->phb) return; | |
816 | for (i=4; i<10; i++) { | |
817 | rtas_write_config(pdn, i*4, 4, pdn->config_space[i]); | |
818 | } | |
819 | ||
820 | /* 12 == Expansion ROM Address */ | |
821 | rtas_write_config(pdn, 12*4, 4, pdn->config_space[12]); | |
822 | ||
823 | #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF)) | |
824 | #define SAVED_BYTE(OFF) (((u8 *)(pdn->config_space))[BYTE_SWAP(OFF)]) | |
825 | ||
826 | rtas_write_config (pdn, PCI_CACHE_LINE_SIZE, 1, | |
827 | SAVED_BYTE(PCI_CACHE_LINE_SIZE)); | |
828 | ||
829 | rtas_write_config (pdn, PCI_LATENCY_TIMER, 1, | |
830 | SAVED_BYTE(PCI_LATENCY_TIMER)); | |
831 | ||
832 | /* max latency, min grant, interrupt pin and line */ | |
833 | rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]); | |
cde274c0 MM |
834 | |
835 | /* Restore PERR & SERR bits, some devices require it, | |
836 | don't touch the other command bits */ | |
837 | rtas_read_config(pdn, PCI_COMMAND, 4, &cmd); | |
838 | if (pdn->config_space[1] & PCI_COMMAND_PARITY) | |
839 | cmd |= PCI_COMMAND_PARITY; | |
840 | else | |
841 | cmd &= ~PCI_COMMAND_PARITY; | |
842 | if (pdn->config_space[1] & PCI_COMMAND_SERR) | |
843 | cmd |= PCI_COMMAND_SERR; | |
844 | else | |
845 | cmd &= ~PCI_COMMAND_SERR; | |
846 | rtas_write_config(pdn, PCI_COMMAND, 4, cmd); | |
8b553f32 LV |
847 | } |
848 | ||
849 | /** | |
850 | * eeh_restore_bars - restore the PCI config space info | |
851 | * | |
852 | * This routine performs a recursive walk to the children | |
853 | * of this device as well. | |
854 | */ | |
855 | void eeh_restore_bars(struct pci_dn *pdn) | |
856 | { | |
857 | struct device_node *dn; | |
858 | if (!pdn) | |
859 | return; | |
860 | ||
7684b40c | 861 | if ((pdn->eeh_mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(pdn->class_code)) |
8b553f32 LV |
862 | __restore_bars (pdn); |
863 | ||
acaa6176 | 864 | for_each_child_of_node(pdn->node, dn) |
8b553f32 | 865 | eeh_restore_bars (PCI_DN(dn)); |
8b553f32 LV |
866 | } |
867 | ||
868 | /** | |
869 | * eeh_save_bars - save device bars | |
870 | * | |
871 | * Save the values of the device bars. Unlike the restore | |
872 | * routine, this routine is *not* recursive. This is because | |
873 | * PCI devices are added individuallly; but, for the restore, | |
874 | * an entire slot is reset at a time. | |
875 | */ | |
7684b40c | 876 | static void eeh_save_bars(struct pci_dn *pdn) |
8b553f32 LV |
877 | { |
878 | int i; | |
879 | ||
7684b40c | 880 | if (!pdn ) |
8b553f32 LV |
881 | return; |
882 | ||
883 | for (i = 0; i < 16; i++) | |
7684b40c | 884 | rtas_read_config(pdn, i * 4, 4, &pdn->config_space[i]); |
8b553f32 LV |
885 | } |
886 | ||
887 | void | |
888 | rtas_configure_bridge(struct pci_dn *pdn) | |
889 | { | |
fcb7543e | 890 | int config_addr; |
8b553f32 LV |
891 | int rc; |
892 | ||
fcb7543e LV |
893 | /* Use PE configuration address, if present */ |
894 | config_addr = pdn->eeh_config_addr; | |
895 | if (pdn->eeh_pe_config_addr) | |
896 | config_addr = pdn->eeh_pe_config_addr; | |
897 | ||
21e464dd | 898 | rc = rtas_call(ibm_configure_bridge,3,1, NULL, |
fcb7543e | 899 | config_addr, |
8b553f32 LV |
900 | BUID_HI(pdn->phb->buid), |
901 | BUID_LO(pdn->phb->buid)); | |
902 | if (rc) { | |
903 | printk (KERN_WARNING "EEH: Unable to configure device bridge (%d) for %s\n", | |
904 | rc, pdn->node->full_name); | |
905 | } | |
906 | } | |
907 | ||
172ca926 LV |
908 | /* ------------------------------------------------------------- */ |
909 | /* The code below deals with enabling EEH for devices during the | |
910 | * early boot sequence. EEH must be enabled before any PCI probing | |
911 | * can be done. | |
912 | */ | |
913 | ||
914 | #define EEH_ENABLE 1 | |
915 | ||
1da177e4 LT |
916 | struct eeh_early_enable_info { |
917 | unsigned int buid_hi; | |
918 | unsigned int buid_lo; | |
919 | }; | |
920 | ||
147d6a37 LV |
921 | static int get_pe_addr (int config_addr, |
922 | struct eeh_early_enable_info *info) | |
923 | { | |
924 | unsigned int rets[3]; | |
925 | int ret; | |
926 | ||
927 | /* Use latest config-addr token on power6 */ | |
928 | if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) { | |
929 | /* Make sure we have a PE in hand */ | |
930 | ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets, | |
931 | config_addr, info->buid_hi, info->buid_lo, 1); | |
932 | if (ret || (rets[0]==0)) | |
933 | return 0; | |
934 | ||
935 | ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets, | |
936 | config_addr, info->buid_hi, info->buid_lo, 0); | |
937 | if (ret) | |
938 | return 0; | |
939 | return rets[0]; | |
940 | } | |
941 | ||
942 | /* Use older config-addr token on power5 */ | |
943 | if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) { | |
944 | ret = rtas_call (ibm_get_config_addr_info, 4, 2, rets, | |
945 | config_addr, info->buid_hi, info->buid_lo, 0); | |
946 | if (ret) | |
947 | return 0; | |
948 | return rets[0]; | |
949 | } | |
950 | return 0; | |
951 | } | |
952 | ||
1da177e4 LT |
953 | /* Enable eeh for the given device node. */ |
954 | static void *early_enable_eeh(struct device_node *dn, void *data) | |
955 | { | |
25c4a46f | 956 | unsigned int rets[3]; |
1da177e4 LT |
957 | struct eeh_early_enable_info *info = data; |
958 | int ret; | |
e2eb6392 SR |
959 | const u32 *class_code = of_get_property(dn, "class-code", NULL); |
960 | const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL); | |
961 | const u32 *device_id = of_get_property(dn, "device-id", NULL); | |
954a46e2 | 962 | const u32 *regs; |
1da177e4 | 963 | int enable; |
69376502 | 964 | struct pci_dn *pdn = PCI_DN(dn); |
1da177e4 | 965 | |
0f17574a | 966 | pdn->class_code = 0; |
1635317f | 967 | pdn->eeh_mode = 0; |
5c1344e9 LV |
968 | pdn->eeh_check_count = 0; |
969 | pdn->eeh_freeze_count = 0; | |
858955bd | 970 | pdn->eeh_false_positives = 0; |
1da177e4 | 971 | |
c6d4d5a8 NL |
972 | if (!of_device_is_available(dn)) |
973 | return NULL; | |
1da177e4 LT |
974 | |
975 | /* Ignore bad nodes. */ | |
976 | if (!class_code || !vendor_id || !device_id) | |
977 | return NULL; | |
978 | ||
979 | /* There is nothing to check on PCI to ISA bridges */ | |
980 | if (dn->type && !strcmp(dn->type, "isa")) { | |
1635317f | 981 | pdn->eeh_mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
982 | return NULL; |
983 | } | |
0f17574a | 984 | pdn->class_code = *class_code; |
1da177e4 | 985 | |
1da177e4 LT |
986 | /* Ok... see if this device supports EEH. Some do, some don't, |
987 | * and the only way to find out is to check each and every one. */ | |
e2eb6392 | 988 | regs = of_get_property(dn, "reg", NULL); |
1da177e4 LT |
989 | if (regs) { |
990 | /* First register entry is addr (00BBSS00) */ | |
991 | /* Try to enable eeh */ | |
992 | ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL, | |
172ca926 LV |
993 | regs[0], info->buid_hi, info->buid_lo, |
994 | EEH_ENABLE); | |
995 | ||
25c4a46f | 996 | enable = 0; |
1da177e4 | 997 | if (ret == 0) { |
1635317f | 998 | pdn->eeh_config_addr = regs[0]; |
25e591f6 LV |
999 | |
1000 | /* If the newer, better, ibm,get-config-addr-info is supported, | |
1001 | * then use that instead. */ | |
147d6a37 | 1002 | pdn->eeh_pe_config_addr = get_pe_addr(pdn->eeh_config_addr, info); |
25c4a46f LV |
1003 | |
1004 | /* Some older systems (Power4) allow the | |
1005 | * ibm,set-eeh-option call to succeed even on nodes | |
1006 | * where EEH is not supported. Verify support | |
1007 | * explicitly. */ | |
1008 | ret = read_slot_reset_state(pdn, rets); | |
1009 | if ((ret == 0) && (rets[1] == 1)) | |
1010 | enable = 1; | |
1011 | } | |
1012 | ||
1013 | if (enable) { | |
1014 | eeh_subsystem_enabled = 1; | |
1015 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; | |
1016 | ||
57b066ff BH |
1017 | pr_debug("EEH: %s: eeh enabled, config=%x pe_config=%x\n", |
1018 | dn->full_name, pdn->eeh_config_addr, | |
1019 | pdn->eeh_pe_config_addr); | |
1da177e4 LT |
1020 | } else { |
1021 | ||
1022 | /* This device doesn't support EEH, but it may have an | |
1023 | * EEH parent, in which case we mark it as supported. */ | |
69376502 | 1024 | if (dn->parent && PCI_DN(dn->parent) |
1635317f | 1025 | && (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) { |
1da177e4 | 1026 | /* Parent supports EEH. */ |
1635317f PM |
1027 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; |
1028 | pdn->eeh_config_addr = PCI_DN(dn->parent)->eeh_config_addr; | |
1da177e4 LT |
1029 | return NULL; |
1030 | } | |
1031 | } | |
1032 | } else { | |
1033 | printk(KERN_WARNING "EEH: %s: unable to get reg property.\n", | |
1034 | dn->full_name); | |
1035 | } | |
1036 | ||
7684b40c | 1037 | eeh_save_bars(pdn); |
69376502 | 1038 | return NULL; |
1da177e4 LT |
1039 | } |
1040 | ||
1041 | /* | |
1042 | * Initialize EEH by trying to enable it for all of the adapters in the system. | |
1043 | * As a side effect we can determine here if eeh is supported at all. | |
1044 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
1045 | * check. If a user turns off EEH for a particular adapter they are really | |
1046 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
1047 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
1048 | * EEH for all slots/all devices. | |
1049 | * | |
1050 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
1051 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
1052 | * newer systems can boot. | |
1053 | */ | |
1054 | void __init eeh_init(void) | |
1055 | { | |
1056 | struct device_node *phb, *np; | |
1057 | struct eeh_early_enable_info info; | |
1058 | ||
fd761fd8 | 1059 | spin_lock_init(&confirm_error_lock); |
df7242b1 LV |
1060 | spin_lock_init(&slot_errbuf_lock); |
1061 | ||
1da177e4 LT |
1062 | np = of_find_node_by_path("/rtas"); |
1063 | if (np == NULL) | |
1064 | return; | |
1065 | ||
1066 | ibm_set_eeh_option = rtas_token("ibm,set-eeh-option"); | |
1067 | ibm_set_slot_reset = rtas_token("ibm,set-slot-reset"); | |
1068 | ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2"); | |
1069 | ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state"); | |
1070 | ibm_slot_error_detail = rtas_token("ibm,slot-error-detail"); | |
25e591f6 | 1071 | ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info"); |
147d6a37 | 1072 | ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2"); |
21e464dd | 1073 | ibm_configure_bridge = rtas_token ("ibm,configure-bridge"); |
1da177e4 LT |
1074 | |
1075 | if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) | |
1076 | return; | |
1077 | ||
1078 | eeh_error_buf_size = rtas_token("rtas-error-log-max"); | |
1079 | if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) { | |
1080 | eeh_error_buf_size = 1024; | |
1081 | } | |
1082 | if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) { | |
1083 | printk(KERN_WARNING "EEH: rtas-error-log-max is bigger than allocated " | |
1084 | "buffer ! (%d vs %d)", eeh_error_buf_size, RTAS_ERROR_LOG_MAX); | |
1085 | eeh_error_buf_size = RTAS_ERROR_LOG_MAX; | |
1086 | } | |
1087 | ||
1088 | /* Enable EEH for all adapters. Note that eeh requires buid's */ | |
1089 | for (phb = of_find_node_by_name(NULL, "pci"); phb; | |
1090 | phb = of_find_node_by_name(phb, "pci")) { | |
1091 | unsigned long buid; | |
1092 | ||
1093 | buid = get_phb_buid(phb); | |
69376502 | 1094 | if (buid == 0 || PCI_DN(phb) == NULL) |
1da177e4 LT |
1095 | continue; |
1096 | ||
1097 | info.buid_lo = BUID_LO(buid); | |
1098 | info.buid_hi = BUID_HI(buid); | |
1099 | traverse_pci_devices(phb, early_enable_eeh, &info); | |
1100 | } | |
1101 | ||
1102 | if (eeh_subsystem_enabled) | |
1103 | printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n"); | |
1104 | else | |
1105 | printk(KERN_WARNING "EEH: No capable adapters found\n"); | |
1106 | } | |
1107 | ||
1108 | /** | |
1109 | * eeh_add_device_early - enable EEH for the indicated device_node | |
1110 | * @dn: device node for which to set up EEH | |
1111 | * | |
1112 | * This routine must be used to perform EEH initialization for PCI | |
1113 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1114 | * This routine must be called before any i/o is performed to the | |
1115 | * adapter (inluding any config-space i/o). | |
1116 | * Whether this actually enables EEH or not for this device depends | |
1117 | * on the CEC architecture, type of the device, on earlier boot | |
1118 | * command-line arguments & etc. | |
1119 | */ | |
794e085e | 1120 | static void eeh_add_device_early(struct device_node *dn) |
1da177e4 LT |
1121 | { |
1122 | struct pci_controller *phb; | |
1123 | struct eeh_early_enable_info info; | |
1124 | ||
69376502 | 1125 | if (!dn || !PCI_DN(dn)) |
1da177e4 | 1126 | return; |
1635317f | 1127 | phb = PCI_DN(dn)->phb; |
f751f841 LV |
1128 | |
1129 | /* USB Bus children of PCI devices will not have BUID's */ | |
1130 | if (NULL == phb || 0 == phb->buid) | |
1da177e4 | 1131 | return; |
1da177e4 LT |
1132 | |
1133 | info.buid_hi = BUID_HI(phb->buid); | |
1134 | info.buid_lo = BUID_LO(phb->buid); | |
1135 | early_enable_eeh(dn, &info); | |
1136 | } | |
1da177e4 | 1137 | |
e2a296ee LV |
1138 | void eeh_add_device_tree_early(struct device_node *dn) |
1139 | { | |
1140 | struct device_node *sib; | |
acaa6176 SR |
1141 | |
1142 | for_each_child_of_node(dn, sib) | |
e2a296ee LV |
1143 | eeh_add_device_tree_early(sib); |
1144 | eeh_add_device_early(dn); | |
1145 | } | |
1146 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
1147 | ||
1da177e4 LT |
1148 | /** |
1149 | * eeh_add_device_late - perform EEH initialization for the indicated pci device | |
1150 | * @dev: pci device for which to set up EEH | |
1151 | * | |
1152 | * This routine must be used to complete EEH initialization for PCI | |
1153 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1154 | */ | |
794e085e | 1155 | static void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 1156 | { |
56b0fca3 | 1157 | struct device_node *dn; |
8b553f32 | 1158 | struct pci_dn *pdn; |
56b0fca3 | 1159 | |
1da177e4 LT |
1160 | if (!dev || !eeh_subsystem_enabled) |
1161 | return; | |
1162 | ||
57b066ff | 1163 | pr_debug("EEH: Adding device %s\n", pci_name(dev)); |
1da177e4 | 1164 | |
56b0fca3 | 1165 | dn = pci_device_to_OF_node(dev); |
8b553f32 | 1166 | pdn = PCI_DN(dn); |
57b066ff BH |
1167 | if (pdn->pcidev == dev) { |
1168 | pr_debug("EEH: Already referenced !\n"); | |
1169 | return; | |
1170 | } | |
1171 | WARN_ON(pdn->pcidev); | |
1172 | ||
1173 | pci_dev_get (dev); | |
8b553f32 | 1174 | pdn->pcidev = dev; |
56b0fca3 | 1175 | |
e1d04c97 LV |
1176 | pci_addr_cache_insert_device(dev); |
1177 | eeh_sysfs_add_device(dev); | |
1da177e4 | 1178 | } |
794e085e NF |
1179 | |
1180 | void eeh_add_device_tree_late(struct pci_bus *bus) | |
1181 | { | |
1182 | struct pci_dev *dev; | |
1183 | ||
1184 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1185 | eeh_add_device_late(dev); | |
1186 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1187 | struct pci_bus *subbus = dev->subordinate; | |
1188 | if (subbus) | |
1189 | eeh_add_device_tree_late(subbus); | |
1190 | } | |
1191 | } | |
1192 | } | |
1193 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 LT |
1194 | |
1195 | /** | |
1196 | * eeh_remove_device - undo EEH setup for the indicated pci device | |
1197 | * @dev: pci device to be removed | |
1198 | * | |
794e085e NF |
1199 | * This routine should be called when a device is removed from |
1200 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
1201 | * the PCI device from the EEH subsystem. I/O errors affecting | |
1202 | * this device will no longer be detected after this call; thus, | |
1203 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 1204 | */ |
794e085e | 1205 | static void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 1206 | { |
56b0fca3 | 1207 | struct device_node *dn; |
1da177e4 LT |
1208 | if (!dev || !eeh_subsystem_enabled) |
1209 | return; | |
1210 | ||
1211 | /* Unregister the device with the EEH/PCI address search system */ | |
57b066ff | 1212 | pr_debug("EEH: Removing device %s\n", pci_name(dev)); |
56b0fca3 LV |
1213 | |
1214 | dn = pci_device_to_OF_node(dev); | |
57b066ff BH |
1215 | if (PCI_DN(dn)->pcidev == NULL) { |
1216 | pr_debug("EEH: Not referenced !\n"); | |
1217 | return; | |
b055a9e1 | 1218 | } |
57b066ff BH |
1219 | PCI_DN(dn)->pcidev = NULL; |
1220 | pci_dev_put (dev); | |
1221 | ||
1222 | pci_addr_cache_remove_device(dev); | |
1223 | eeh_sysfs_remove_device(dev); | |
1da177e4 | 1224 | } |
1da177e4 | 1225 | |
e2a296ee LV |
1226 | void eeh_remove_bus_device(struct pci_dev *dev) |
1227 | { | |
794e085e NF |
1228 | struct pci_bus *bus = dev->subordinate; |
1229 | struct pci_dev *child, *tmp; | |
1230 | ||
e2a296ee | 1231 | eeh_remove_device(dev); |
794e085e NF |
1232 | |
1233 | if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1234 | list_for_each_entry_safe(child, tmp, &bus->devices, bus_list) | |
1235 | eeh_remove_bus_device(child); | |
e2a296ee LV |
1236 | } |
1237 | } | |
1238 | EXPORT_SYMBOL_GPL(eeh_remove_bus_device); | |
1239 | ||
1da177e4 LT |
1240 | static int proc_eeh_show(struct seq_file *m, void *v) |
1241 | { | |
1da177e4 LT |
1242 | if (0 == eeh_subsystem_enabled) { |
1243 | seq_printf(m, "EEH Subsystem is globally disabled\n"); | |
257ffc64 | 1244 | seq_printf(m, "eeh_total_mmio_ffs=%ld\n", total_mmio_ffs); |
1da177e4 LT |
1245 | } else { |
1246 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 LV |
1247 | seq_printf(m, |
1248 | "no device=%ld\n" | |
1249 | "no device node=%ld\n" | |
1250 | "no config address=%ld\n" | |
1251 | "check not wanted=%ld\n" | |
1252 | "eeh_total_mmio_ffs=%ld\n" | |
1253 | "eeh_false_positives=%ld\n" | |
177bc936 | 1254 | "eeh_slot_resets=%ld\n", |
257ffc64 LV |
1255 | no_device, no_dn, no_cfg_addr, |
1256 | ignored_check, total_mmio_ffs, | |
42253a68 | 1257 | false_positives, |
257ffc64 | 1258 | slot_resets); |
1da177e4 LT |
1259 | } |
1260 | ||
1261 | return 0; | |
1262 | } | |
1263 | ||
1264 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1265 | { | |
1266 | return single_open(file, proc_eeh_show, NULL); | |
1267 | } | |
1268 | ||
5dfe4c96 | 1269 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1270 | .open = proc_eeh_open, |
1271 | .read = seq_read, | |
1272 | .llseek = seq_lseek, | |
1273 | .release = single_release, | |
1274 | }; | |
1275 | ||
1276 | static int __init eeh_init_proc(void) | |
1277 | { | |
66747138 DL |
1278 | if (machine_is(pseries)) |
1279 | proc_create("ppc64/eeh", 0, NULL, &proc_eeh_operations); | |
1da177e4 LT |
1280 | return 0; |
1281 | } | |
1282 | __initcall(eeh_init_proc); |