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[POWERPC] Fix warning in prom_parse.c of_irq_map_oldworld()
[linux-2.6-block.git] / arch / powerpc / platforms / powermac / feature.c
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14cf11af 1/*
14cf11af
PM		 2 * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au)
3 * Ben. Herrenschmidt (benh@kernel.crashing.org)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 * TODO:
11 *
12 * - Replace mdelay with some schedule loop if possible
13 * - Shorten some obfuscated delays on some routines (like modem
14 * power)
15 * - Refcount some clocks (see darwin)
16 * - Split split split...
17 *
18 */
14cf11af
PM		 19#include <linux/types.h>
20#include <linux/init.h>
21#include <linux/delay.h>
22#include <linux/kernel.h>
23#include <linux/sched.h>
24#include <linux/spinlock.h>
25#include <linux/adb.h>
26#include <linux/pmu.h>
27#include <linux/ioport.h>
28#include <linux/pci.h>
29#include <asm/sections.h>
30#include <asm/errno.h>
31#include <asm/ohare.h>
32#include <asm/heathrow.h>
33#include <asm/keylargo.h>
34#include <asm/uninorth.h>
35#include <asm/io.h>
36#include <asm/prom.h>
37#include <asm/machdep.h>
38#include <asm/pmac_feature.h>
39#include <asm/dbdma.h>
40#include <asm/pci-bridge.h>
41#include <asm/pmac_low_i2c.h>
42
43#undef DEBUG_FEATURE
44
45#ifdef DEBUG_FEATURE
46#define DBG(fmt...) printk(KERN_DEBUG fmt)
47#else
48#define DBG(fmt...)
49#endif
50
51#ifdef CONFIG_6xx
52extern int powersave_lowspeed;
53#endif
54
55extern int powersave_nap;
56extern struct device_node *k2_skiplist[2];
57
14cf11af
PM		 58/*
59 * We use a single global lock to protect accesses. Each driver has
60 * to take care of its own locking
61 */
5b9ca526 62DEFINE_SPINLOCK(feature_lock);
14cf11af
PM		 63
64#define LOCK(flags) spin_lock_irqsave(&feature_lock, flags);
65#define UNLOCK(flags) spin_unlock_irqrestore(&feature_lock, flags);
66
67
68/*
69 * Instance of some macio stuffs
70 */
71struct macio_chip macio_chips[MAX_MACIO_CHIPS];
72
73struct macio_chip *macio_find(struct device_node *child, int type)
74{
75 while(child) {
76 int i;
77
78 for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++)
79 if (child == macio_chips[i].of_node &&
80 (!type || macio_chips[i].type == type))
81 return &macio_chips[i];
82 child = child->parent;
83 }
84 return NULL;
85}
86EXPORT_SYMBOL_GPL(macio_find);
87
88static const char *macio_names[] =
89{
90 "Unknown",
91 "Grand Central",
92 "OHare",
93 "OHareII",
94 "Heathrow",
95 "Gatwick",
96 "Paddington",
97 "Keylargo",
98 "Pangea",
99 "Intrepid",
1beb6a7d
BH		 100 "K2",
101 "Shasta",
14cf11af
PM		 102};
103
104
5b9ca526
BH		 105struct device_node *uninorth_node;
106u32 __iomem *uninorth_base;
14cf11af 107
14cf11af 108static u32 uninorth_rev;
1beb6a7d 109static int uninorth_maj;
5b9ca526 110static void __iomem *u3_ht_base;
14cf11af
PM		 111
112/*
113 * For each motherboard family, we have a table of functions pointers
114 * that handle the various features.
115 */
116
117typedef long (*feature_call)(struct device_node *node, long param, long value);
118
119struct feature_table_entry {
120 unsigned int selector;
121 feature_call function;
122};
123
124struct pmac_mb_def
125{
126 const char* model_string;
127 const char* model_name;
128 int model_id;
129 struct feature_table_entry* features;
130 unsigned long board_flags;
131};
132static struct pmac_mb_def pmac_mb;
133
134/*
135 * Here are the chip specific feature functions
136 */
137
138static inline int simple_feature_tweak(struct device_node *node, int type,
139 int reg, u32 mask, int value)
140{
141 struct macio_chip* macio;
142 unsigned long flags;
143
144 macio = macio_find(node, type);
145 if (!macio)
146 return -ENODEV;
147 LOCK(flags);
148 if (value)
149 MACIO_BIS(reg, mask);
150 else
151 MACIO_BIC(reg, mask);
152 (void)MACIO_IN32(reg);
153 UNLOCK(flags);
154
155 return 0;
156}
157
158#ifndef CONFIG_POWER4
159
160static long ohare_htw_scc_enable(struct device_node *node, long param,
161 long value)
162{
163 struct macio_chip* macio;
164 unsigned long chan_mask;
165 unsigned long fcr;
166 unsigned long flags;
167 int htw, trans;
168 unsigned long rmask;
169
170 macio = macio_find(node, 0);
171 if (!macio)
172 return -ENODEV;
173 if (!strcmp(node->name, "ch-a"))
174 chan_mask = MACIO_FLAG_SCCA_ON;
175 else if (!strcmp(node->name, "ch-b"))
176 chan_mask = MACIO_FLAG_SCCB_ON;
177 else
178 return -ENODEV;
179
180 htw = (macio->type == macio_heathrow || macio->type == macio_paddington
181 || macio->type == macio_gatwick);
182 /* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */
183 trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
184 pmac_mb.model_id != PMAC_TYPE_YIKES);
185 if (value) {
186#ifdef CONFIG_ADB_PMU
187 if ((param & 0xfff) == PMAC_SCC_IRDA)
188 pmu_enable_irled(1);
189#endif /* CONFIG_ADB_PMU */
190 LOCK(flags);
191 fcr = MACIO_IN32(OHARE_FCR);
192 /* Check if scc cell need enabling */
193 if (!(fcr & OH_SCC_ENABLE)) {
194 fcr |= OH_SCC_ENABLE;
195 if (htw) {
196 /* Side effect: this will also power up the
197 * modem, but it's too messy to figure out on which
198 * ports this controls the tranceiver and on which
199 * it controls the modem
200 */
201 if (trans)
202 fcr &= ~HRW_SCC_TRANS_EN_N;
203 MACIO_OUT32(OHARE_FCR, fcr);
204 fcr |= (rmask = HRW_RESET_SCC);
205 MACIO_OUT32(OHARE_FCR, fcr);
206 } else {
207 fcr |= (rmask = OH_SCC_RESET);
208 MACIO_OUT32(OHARE_FCR, fcr);
209 }
210 UNLOCK(flags);
211 (void)MACIO_IN32(OHARE_FCR);
212 mdelay(15);
213 LOCK(flags);
214 fcr &= ~rmask;
215 MACIO_OUT32(OHARE_FCR, fcr);
216 }
217 if (chan_mask & MACIO_FLAG_SCCA_ON)
218 fcr |= OH_SCCA_IO;
219 if (chan_mask & MACIO_FLAG_SCCB_ON)
220 fcr |= OH_SCCB_IO;
221 MACIO_OUT32(OHARE_FCR, fcr);
222 macio->flags |= chan_mask;
223 UNLOCK(flags);
224 if (param & PMAC_SCC_FLAG_XMON)
225 macio->flags |= MACIO_FLAG_SCC_LOCKED;
226 } else {
227 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
228 return -EPERM;
229 LOCK(flags);
230 fcr = MACIO_IN32(OHARE_FCR);
231 if (chan_mask & MACIO_FLAG_SCCA_ON)
232 fcr &= ~OH_SCCA_IO;
233 if (chan_mask & MACIO_FLAG_SCCB_ON)
234 fcr &= ~OH_SCCB_IO;
235 MACIO_OUT32(OHARE_FCR, fcr);
236 if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) {
237 fcr &= ~OH_SCC_ENABLE;
238 if (htw && trans)
239 fcr |= HRW_SCC_TRANS_EN_N;
240 MACIO_OUT32(OHARE_FCR, fcr);
241 }
242 macio->flags &= ~(chan_mask);
243 UNLOCK(flags);
244 mdelay(10);
245#ifdef CONFIG_ADB_PMU
246 if ((param & 0xfff) == PMAC_SCC_IRDA)
247 pmu_enable_irled(0);
248#endif /* CONFIG_ADB_PMU */
249 }
250 return 0;
251}
252
253static long ohare_floppy_enable(struct device_node *node, long param,
254 long value)
255{
256 return simple_feature_tweak(node, macio_ohare,
257 OHARE_FCR, OH_FLOPPY_ENABLE, value);
258}
259
260static long ohare_mesh_enable(struct device_node *node, long param, long value)
261{
262 return simple_feature_tweak(node, macio_ohare,
263 OHARE_FCR, OH_MESH_ENABLE, value);
264}
265
266static long ohare_ide_enable(struct device_node *node, long param, long value)
267{
268 switch(param) {
269 case 0:
270 /* For some reason, setting the bit in set_initial_features()
271 * doesn't stick. I'm still investigating... --BenH.
272 */
273 if (value)
274 simple_feature_tweak(node, macio_ohare,
275 OHARE_FCR, OH_IOBUS_ENABLE, 1);
276 return simple_feature_tweak(node, macio_ohare,
277 OHARE_FCR, OH_IDE0_ENABLE, value);
278 case 1:
279 return simple_feature_tweak(node, macio_ohare,
280 OHARE_FCR, OH_BAY_IDE_ENABLE, value);
281 default:
282 return -ENODEV;
283 }
284}
285
286static long ohare_ide_reset(struct device_node *node, long param, long value)
287{
288 switch(param) {
289 case 0:
290 return simple_feature_tweak(node, macio_ohare,
291 OHARE_FCR, OH_IDE0_RESET_N, !value);
292 case 1:
293 return simple_feature_tweak(node, macio_ohare,
294 OHARE_FCR, OH_IDE1_RESET_N, !value);
295 default:
296 return -ENODEV;
297 }
298}
299
300static long ohare_sleep_state(struct device_node *node, long param, long value)
301{
302 struct macio_chip* macio = &macio_chips[0];
303
304 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
305 return -EPERM;
306 if (value == 1) {
307 MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE);
308 } else if (value == 0) {
309 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
310 }
311
312 return 0;
313}
314
315static long heathrow_modem_enable(struct device_node *node, long param,
316 long value)
317{
318 struct macio_chip* macio;
319 u8 gpio;
320 unsigned long flags;
321
322 macio = macio_find(node, macio_unknown);
323 if (!macio)
324 return -ENODEV;
325 gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1;
326 if (!value) {
327 LOCK(flags);
328 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
329 UNLOCK(flags);
330 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
331 mdelay(250);
332 }
333 if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
334 pmac_mb.model_id != PMAC_TYPE_YIKES) {
335 LOCK(flags);
336 if (value)
337 MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
338 else
339 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
340 UNLOCK(flags);
341 (void)MACIO_IN32(HEATHROW_FCR);
342 mdelay(250);
343 }
344 if (value) {
345 LOCK(flags);
346 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
347 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
348 UNLOCK(flags); mdelay(250); LOCK(flags);
349 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
350 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
351 UNLOCK(flags); mdelay(250); LOCK(flags);
352 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
353 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
354 UNLOCK(flags); mdelay(250);
355 }
356 return 0;
357}
358
359static long heathrow_floppy_enable(struct device_node *node, long param,
360 long value)
361{
362 return simple_feature_tweak(node, macio_unknown,
363 HEATHROW_FCR,
364 HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE,
365 value);
366}
367
368static long heathrow_mesh_enable(struct device_node *node, long param,
369 long value)
370{
371 struct macio_chip* macio;
372 unsigned long flags;
373
374 macio = macio_find(node, macio_unknown);
375 if (!macio)
376 return -ENODEV;
377 LOCK(flags);
378 /* Set clear mesh cell enable */
379 if (value)
380 MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE);
381 else
382 MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE);
383 (void)MACIO_IN32(HEATHROW_FCR);
384 udelay(10);
385 /* Set/Clear termination power */
386 if (value)
387 MACIO_BIC(HEATHROW_MBCR, 0x04000000);
388 else
389 MACIO_BIS(HEATHROW_MBCR, 0x04000000);
390 (void)MACIO_IN32(HEATHROW_MBCR);
391 udelay(10);
392 UNLOCK(flags);
393
394 return 0;
395}
396
397static long heathrow_ide_enable(struct device_node *node, long param,
398 long value)
399{
400 switch(param) {
401 case 0:
402 return simple_feature_tweak(node, macio_unknown,
403 HEATHROW_FCR, HRW_IDE0_ENABLE, value);
404 case 1:
405 return simple_feature_tweak(node, macio_unknown,
406 HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value);
407 default:
408 return -ENODEV;
409 }
410}
411
412static long heathrow_ide_reset(struct device_node *node, long param,
413 long value)
414{
415 switch(param) {
416 case 0:
417 return simple_feature_tweak(node, macio_unknown,
418 HEATHROW_FCR, HRW_IDE0_RESET_N, !value);
419 case 1:
420 return simple_feature_tweak(node, macio_unknown,
421 HEATHROW_FCR, HRW_IDE1_RESET_N, !value);
422 default:
423 return -ENODEV;
424 }
425}
426
427static long heathrow_bmac_enable(struct device_node *node, long param,
428 long value)
429{
430 struct macio_chip* macio;
431 unsigned long flags;
432
433 macio = macio_find(node, 0);
434 if (!macio)
435 return -ENODEV;
436 if (value) {
437 LOCK(flags);
438 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
439 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET);
440 UNLOCK(flags);
441 (void)MACIO_IN32(HEATHROW_FCR);
442 mdelay(10);
443 LOCK(flags);
444 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET);
445 UNLOCK(flags);
446 (void)MACIO_IN32(HEATHROW_FCR);
447 mdelay(10);
448 } else {
449 LOCK(flags);
450 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
451 UNLOCK(flags);
452 }
453 return 0;
454}
455
456static long heathrow_sound_enable(struct device_node *node, long param,
457 long value)
458{
459 struct macio_chip* macio;
460 unsigned long flags;
461
462 /* B&W G3 and Yikes don't support that properly (the
463 * sound appear to never come back after beeing shut down).
464 */
465 if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE ||
466 pmac_mb.model_id == PMAC_TYPE_YIKES)
467 return 0;
468
469 macio = macio_find(node, 0);
470 if (!macio)
471 return -ENODEV;
472 if (value) {
473 LOCK(flags);
474 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
475 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
476 UNLOCK(flags);
477 (void)MACIO_IN32(HEATHROW_FCR);
478 } else {
479 LOCK(flags);
480 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
481 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
482 UNLOCK(flags);
483 }
484 return 0;
485}
486
487static u32 save_fcr[6];
488static u32 save_mbcr;
14cf11af
PM		 489static struct dbdma_regs save_dbdma[13];
490static struct dbdma_regs save_alt_dbdma[13];
491
492static void dbdma_save(struct macio_chip *macio, struct dbdma_regs *save)
493{
494 int i;
495
496 /* Save state & config of DBDMA channels */
497 for (i = 0; i < 13; i++) {
498 volatile struct dbdma_regs __iomem * chan = (void __iomem *)
499 (macio->base + ((0x8000+i*0x100)>>2));
500 save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi);
501 save[i].cmdptr = in_le32(&chan->cmdptr);
502 save[i].intr_sel = in_le32(&chan->intr_sel);
503 save[i].br_sel = in_le32(&chan->br_sel);
504 save[i].wait_sel = in_le32(&chan->wait_sel);
505 }
506}
507
508static void dbdma_restore(struct macio_chip *macio, struct dbdma_regs *save)
509{
510 int i;
511
512 /* Save state & config of DBDMA channels */
513 for (i = 0; i < 13; i++) {
514 volatile struct dbdma_regs __iomem * chan = (void __iomem *)
515 (macio->base + ((0x8000+i*0x100)>>2));
516 out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);
517 while (in_le32(&chan->status) & ACTIVE)
518 mb();
519 out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi);
520 out_le32(&chan->cmdptr, save[i].cmdptr);
521 out_le32(&chan->intr_sel, save[i].intr_sel);
522 out_le32(&chan->br_sel, save[i].br_sel);
523 out_le32(&chan->wait_sel, save[i].wait_sel);
524 }
525}
526
527static void heathrow_sleep(struct macio_chip *macio, int secondary)
528{
529 if (secondary) {
530 dbdma_save(macio, save_alt_dbdma);
531 save_fcr[2] = MACIO_IN32(0x38);
532 save_fcr[3] = MACIO_IN32(0x3c);
533 } else {
534 dbdma_save(macio, save_dbdma);
535 save_fcr[0] = MACIO_IN32(0x38);
536 save_fcr[1] = MACIO_IN32(0x3c);
537 save_mbcr = MACIO_IN32(0x34);
538 /* Make sure sound is shut down */
539 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
540 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
541 /* This seems to be necessary as well or the fan
542 * keeps coming up and battery drains fast */
543 MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE);
544 MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N);
545 /* Make sure eth is down even if module or sleep
546 * won't work properly */
547 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET);
548 }
549 /* Make sure modem is shut down */
550 MACIO_OUT8(HRW_GPIO_MODEM_RESET,
551 MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1);
552 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
553 MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE);
554
555 /* Let things settle */
556 (void)MACIO_IN32(HEATHROW_FCR);
557}
558
559static void heathrow_wakeup(struct macio_chip *macio, int secondary)
560{
561 if (secondary) {
562 MACIO_OUT32(0x38, save_fcr[2]);
563 (void)MACIO_IN32(0x38);
564 mdelay(1);
565 MACIO_OUT32(0x3c, save_fcr[3]);
566 (void)MACIO_IN32(0x38);
567 mdelay(10);
568 dbdma_restore(macio, save_alt_dbdma);
569 } else {
570 MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE);
571 (void)MACIO_IN32(0x38);
572 mdelay(1);
573 MACIO_OUT32(0x3c, save_fcr[1]);
574 (void)MACIO_IN32(0x38);
575 mdelay(1);
576 MACIO_OUT32(0x34, save_mbcr);
577 (void)MACIO_IN32(0x38);
578 mdelay(10);
579 dbdma_restore(macio, save_dbdma);
580 }
581}
582
583static long heathrow_sleep_state(struct device_node *node, long param,
584 long value)
585{
586 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
587 return -EPERM;
588 if (value == 1) {
589 if (macio_chips[1].type == macio_gatwick)
590 heathrow_sleep(&macio_chips[0], 1);
591 heathrow_sleep(&macio_chips[0], 0);
592 } else if (value == 0) {
593 heathrow_wakeup(&macio_chips[0], 0);
594 if (macio_chips[1].type == macio_gatwick)
595 heathrow_wakeup(&macio_chips[0], 1);
596 }
597 return 0;
598}
599
600static long core99_scc_enable(struct device_node *node, long param, long value)
601{
602 struct macio_chip* macio;
603 unsigned long flags;
604 unsigned long chan_mask;
605 u32 fcr;
606
607 macio = macio_find(node, 0);
608 if (!macio)
609 return -ENODEV;
610 if (!strcmp(node->name, "ch-a"))
611 chan_mask = MACIO_FLAG_SCCA_ON;
612 else if (!strcmp(node->name, "ch-b"))
613 chan_mask = MACIO_FLAG_SCCB_ON;
614 else
615 return -ENODEV;
616
617 if (value) {
618 int need_reset_scc = 0;
619 int need_reset_irda = 0;
620
621 LOCK(flags);
622 fcr = MACIO_IN32(KEYLARGO_FCR0);
623 /* Check if scc cell need enabling */
624 if (!(fcr & KL0_SCC_CELL_ENABLE)) {
625 fcr |= KL0_SCC_CELL_ENABLE;
626 need_reset_scc = 1;
627 }
628 if (chan_mask & MACIO_FLAG_SCCA_ON) {
629 fcr |= KL0_SCCA_ENABLE;
630 /* Don't enable line drivers for I2S modem */
631 if ((param & 0xfff) == PMAC_SCC_I2S1)
632 fcr &= ~KL0_SCC_A_INTF_ENABLE;
633 else
634 fcr |= KL0_SCC_A_INTF_ENABLE;
635 }
636 if (chan_mask & MACIO_FLAG_SCCB_ON) {
637 fcr |= KL0_SCCB_ENABLE;
638 /* Perform irda specific inits */
639 if ((param & 0xfff) == PMAC_SCC_IRDA) {
640 fcr &= ~KL0_SCC_B_INTF_ENABLE;
641 fcr |= KL0_IRDA_ENABLE;
642 fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE;
643 fcr |= KL0_IRDA_SOURCE1_SEL;
644 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
645 fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
646 need_reset_irda = 1;
647 } else
648 fcr |= KL0_SCC_B_INTF_ENABLE;
649 }
650 MACIO_OUT32(KEYLARGO_FCR0, fcr);
651 macio->flags |= chan_mask;
652 if (need_reset_scc) {
653 MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET);
654 (void)MACIO_IN32(KEYLARGO_FCR0);
655 UNLOCK(flags);
656 mdelay(15);
657 LOCK(flags);
658 MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET);
659 }
660 if (need_reset_irda) {
661 MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET);
662 (void)MACIO_IN32(KEYLARGO_FCR0);
663 UNLOCK(flags);
664 mdelay(15);
665 LOCK(flags);
666 MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET);
667 }
668 UNLOCK(flags);
669 if (param & PMAC_SCC_FLAG_XMON)
670 macio->flags |= MACIO_FLAG_SCC_LOCKED;
671 } else {
672 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
673 return -EPERM;
674 LOCK(flags);
675 fcr = MACIO_IN32(KEYLARGO_FCR0);
676 if (chan_mask & MACIO_FLAG_SCCA_ON)
677 fcr &= ~KL0_SCCA_ENABLE;
678 if (chan_mask & MACIO_FLAG_SCCB_ON) {
679 fcr &= ~KL0_SCCB_ENABLE;
680 /* Perform irda specific clears */
681 if ((param & 0xfff) == PMAC_SCC_IRDA) {
682 fcr &= ~KL0_IRDA_ENABLE;
683 fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE);
684 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
685 fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
686 }
687 }
688 MACIO_OUT32(KEYLARGO_FCR0, fcr);
689 if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) {
690 fcr &= ~KL0_SCC_CELL_ENABLE;
691 MACIO_OUT32(KEYLARGO_FCR0, fcr);
692 }
693 macio->flags &= ~(chan_mask);
694 UNLOCK(flags);
695 mdelay(10);
696 }
697 return 0;
698}
699
700static long
701core99_modem_enable(struct device_node *node, long param, long value)
702{
703 struct macio_chip* macio;
704 u8 gpio;
705 unsigned long flags;
706
707 /* Hack for internal USB modem */
708 if (node == NULL) {
709 if (macio_chips[0].type != macio_keylargo)
710 return -ENODEV;
711 node = macio_chips[0].of_node;
712 }
713 macio = macio_find(node, 0);
714 if (!macio)
715 return -ENODEV;
716 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
717 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
718 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
719
720 if (!value) {
721 LOCK(flags);
722 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
723 UNLOCK(flags);
724 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
725 mdelay(250);
726 }
727 LOCK(flags);
728 if (value) {
729 MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
730 UNLOCK(flags);
731 (void)MACIO_IN32(KEYLARGO_FCR2);
732 mdelay(250);
733 } else {
734 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
735 UNLOCK(flags);
736 }
737 if (value) {
738 LOCK(flags);
739 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
740 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
741 UNLOCK(flags); mdelay(250); LOCK(flags);
742 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
743 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
744 UNLOCK(flags); mdelay(250); LOCK(flags);
745 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
746 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
747 UNLOCK(flags); mdelay(250);
748 }
749 return 0;
750}
751
752static long
753pangea_modem_enable(struct device_node *node, long param, long value)
754{
755 struct macio_chip* macio;
756 u8 gpio;
757 unsigned long flags;
758
759 /* Hack for internal USB modem */
760 if (node == NULL) {
761 if (macio_chips[0].type != macio_pangea &&
762 macio_chips[0].type != macio_intrepid)
763 return -ENODEV;
764 node = macio_chips[0].of_node;
765 }
766 macio = macio_find(node, 0);
767 if (!macio)
768 return -ENODEV;
769 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
770 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
771 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
772
773 if (!value) {
774 LOCK(flags);
775 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
776 UNLOCK(flags);
777 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
778 mdelay(250);
779 }
780 LOCK(flags);
781 if (value) {
782 MACIO_OUT8(KL_GPIO_MODEM_POWER,
783 KEYLARGO_GPIO_OUTPUT_ENABLE);
784 UNLOCK(flags);
785 (void)MACIO_IN32(KEYLARGO_FCR2);
786 mdelay(250);
787 } else {
788 MACIO_OUT8(KL_GPIO_MODEM_POWER,
789 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
790 UNLOCK(flags);
791 }
792 if (value) {
793 LOCK(flags);
794 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
795 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
796 UNLOCK(flags); mdelay(250); LOCK(flags);
797 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
798 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
799 UNLOCK(flags); mdelay(250); LOCK(flags);
800 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
801 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
802 UNLOCK(flags); mdelay(250);
803 }
804 return 0;
805}
806
807static long
808core99_ata100_enable(struct device_node *node, long value)
809{
810 unsigned long flags;
811 struct pci_dev *pdev = NULL;
812 u8 pbus, pid;
813
814 if (uninorth_rev < 0x24)
815 return -ENODEV;
816
817 LOCK(flags);
818 if (value)
819 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
820 else
821 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
822 (void)UN_IN(UNI_N_CLOCK_CNTL);
823 UNLOCK(flags);
824 udelay(20);
825
826 if (value) {
827 if (pci_device_from_OF_node(node, &pbus, &pid) == 0)
828 pdev = pci_find_slot(pbus, pid);
829 if (pdev == NULL)
830 return 0;
831 pci_enable_device(pdev);
832 pci_set_master(pdev);
833 }
834 return 0;
835}
836
837static long
838core99_ide_enable(struct device_node *node, long param, long value)
839{
840 /* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2
841 * based ata-100
842 */
843 switch(param) {
844 case 0:
845 return simple_feature_tweak(node, macio_unknown,
846 KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value);
847 case 1:
848 return simple_feature_tweak(node, macio_unknown,
849 KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value);
850 case 2:
851 return simple_feature_tweak(node, macio_unknown,
852 KEYLARGO_FCR1, KL1_UIDE_ENABLE, value);
853 case 3:
854 return core99_ata100_enable(node, value);
855 default:
856 return -ENODEV;
857 }
858}
859
860static long
861core99_ide_reset(struct device_node *node, long param, long value)
862{
863 switch(param) {
864 case 0:
865 return simple_feature_tweak(node, macio_unknown,
866 KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value);
867 case 1:
868 return simple_feature_tweak(node, macio_unknown,
869 KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value);
870 case 2:
871 return simple_feature_tweak(node, macio_unknown,
872 KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value);
873 default:
874 return -ENODEV;
875 }
876}
877
878static long
879core99_gmac_enable(struct device_node *node, long param, long value)
880{
881 unsigned long flags;
882
883 LOCK(flags);
884 if (value)
885 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
886 else
887 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
888 (void)UN_IN(UNI_N_CLOCK_CNTL);
889 UNLOCK(flags);
890 udelay(20);
891
892 return 0;
893}
894
895static long
896core99_gmac_phy_reset(struct device_node *node, long param, long value)
897{
898 unsigned long flags;
899 struct macio_chip *macio;
900
901 macio = &macio_chips[0];
902 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
903 macio->type != macio_intrepid)
904 return -ENODEV;
905
906 LOCK(flags);
907 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE);
908 (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET);
909 UNLOCK(flags);
910 mdelay(10);
911 LOCK(flags);
912 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */
913 KEYLARGO_GPIO_OUTOUT_DATA);
914 UNLOCK(flags);
915 mdelay(10);
916
917 return 0;
918}
919
920static long
921core99_sound_chip_enable(struct device_node *node, long param, long value)
922{
923 struct macio_chip* macio;
924 unsigned long flags;
925
926 macio = macio_find(node, 0);
927 if (!macio)
928 return -ENODEV;
929
930 /* Do a better probe code, screamer G4 desktops &
931 * iMacs can do that too, add a recalibrate in
932 * the driver as well
933 */
934 if (pmac_mb.model_id == PMAC_TYPE_PISMO ||
935 pmac_mb.model_id == PMAC_TYPE_TITANIUM) {
936 LOCK(flags);
937 if (value)
938 MACIO_OUT8(KL_GPIO_SOUND_POWER,
939 KEYLARGO_GPIO_OUTPUT_ENABLE |
940 KEYLARGO_GPIO_OUTOUT_DATA);
941 else
942 MACIO_OUT8(KL_GPIO_SOUND_POWER,
943 KEYLARGO_GPIO_OUTPUT_ENABLE);
944 (void)MACIO_IN8(KL_GPIO_SOUND_POWER);
945 UNLOCK(flags);
946 }
947 return 0;
948}
949
950static long
951core99_airport_enable(struct device_node *node, long param, long value)
952{
953 struct macio_chip* macio;
954 unsigned long flags;
955 int state;
956
957 macio = macio_find(node, 0);
958 if (!macio)
959 return -ENODEV;
960
961 /* Hint: we allow passing of macio itself for the sake of the
962 * sleep code
963 */
964 if (node != macio->of_node &&
965 (!node->parent || node->parent != macio->of_node))
966 return -ENODEV;
967 state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0;
968 if (value == state)
969 return 0;
970 if (value) {
971 /* This code is a reproduction of OF enable-cardslot
972 * and init-wireless methods, slightly hacked until
973 * I got it working.
974 */
975 LOCK(flags);
976 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5);
977 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
978 UNLOCK(flags);
979 mdelay(10);
980 LOCK(flags);
981 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4);
982 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
983 UNLOCK(flags);
984
985 mdelay(10);
986
987 LOCK(flags);
988 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
989 (void)MACIO_IN32(KEYLARGO_FCR2);
990 udelay(10);
991 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0);
992 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb);
993 udelay(10);
994 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28);
995 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa);
996 udelay(10);
997 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28);
998 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd);
999 udelay(10);
1000 MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28);
1001 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xd);
1002 udelay(10);
1003 MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28);
1004 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xe);
1005 UNLOCK(flags);
1006 udelay(10);
1007 MACIO_OUT32(0x1c000, 0);
1008 mdelay(1);
1009 MACIO_OUT8(0x1a3e0, 0x41);
1010 (void)MACIO_IN8(0x1a3e0);
1011 udelay(10);
1012 LOCK(flags);
1013 MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16);
1014 (void)MACIO_IN32(KEYLARGO_FCR2);
1015 UNLOCK(flags);
1016 mdelay(100);
1017
1018 macio->flags |= MACIO_FLAG_AIRPORT_ON;
1019 } else {
1020 LOCK(flags);
1021 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
1022 (void)MACIO_IN32(KEYLARGO_FCR2);
1023 MACIO_OUT8(KL_GPIO_AIRPORT_0, 0);
1024 MACIO_OUT8(KL_GPIO_AIRPORT_1, 0);
1025 MACIO_OUT8(KL_GPIO_AIRPORT_2, 0);
1026 MACIO_OUT8(KL_GPIO_AIRPORT_3, 0);
1027 MACIO_OUT8(KL_GPIO_AIRPORT_4, 0);
1028 (void)MACIO_IN8(KL_GPIO_AIRPORT_4);
1029 UNLOCK(flags);
1030
1031 macio->flags &= ~MACIO_FLAG_AIRPORT_ON;
1032 }
1033 return 0;
1034}
1035
1036#ifdef CONFIG_SMP
1037static long
1038core99_reset_cpu(struct device_node *node, long param, long value)
1039{
1040 unsigned int reset_io = 0;
1041 unsigned long flags;
1042 struct macio_chip *macio;
1043 struct device_node *np;
1044 const int dflt_reset_lines[] = { KL_GPIO_RESET_CPU0,
1045 KL_GPIO_RESET_CPU1,
1046 KL_GPIO_RESET_CPU2,
1047 KL_GPIO_RESET_CPU3 };
1048
1049 macio = &macio_chips[0];
1050 if (macio->type != macio_keylargo)
1051 return -ENODEV;
1052
1053 np = find_path_device("/cpus");
1054 if (np == NULL)
1055 return -ENODEV;
1056 for (np = np->child; np != NULL; np = np->sibling) {
13b5aecc
AV		 1057 const u32 *num = get_property(np, "reg", NULL);
1058 const u32 *rst = get_property(np, "soft-reset", NULL);
14cf11af
PM		 1059 if (num == NULL || rst == NULL)
1060 continue;
1061 if (param == *num) {
1062 reset_io = *rst;
1063 break;
1064 }
1065 }
1066 if (np == NULL || reset_io == 0)
1067 reset_io = dflt_reset_lines[param];
1068
1069 LOCK(flags);
1070 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1071 (void)MACIO_IN8(reset_io);
1072 udelay(1);
1073 MACIO_OUT8(reset_io, 0);
1074 (void)MACIO_IN8(reset_io);
1075 UNLOCK(flags);
1076
1077 return 0;
1078}
1079#endif /* CONFIG_SMP */
1080
1081static long
1082core99_usb_enable(struct device_node *node, long param, long value)
1083{
1084 struct macio_chip *macio;
1085 unsigned long flags;
018a3d1d 1086 const char *prop;
14cf11af
PM		 1087 int number;
1088 u32 reg;
1089
1090 macio = &macio_chips[0];
1091 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1092 macio->type != macio_intrepid)
1093 return -ENODEV;
1094
018a3d1d 1095 prop = get_property(node, "AAPL,clock-id", NULL);
14cf11af
PM		 1096 if (!prop)
1097 return -ENODEV;
1098 if (strncmp(prop, "usb0u048", 8) == 0)
1099 number = 0;
1100 else if (strncmp(prop, "usb1u148", 8) == 0)
1101 number = 2;
1102 else if (strncmp(prop, "usb2u248", 8) == 0)
1103 number = 4;
1104 else
1105 return -ENODEV;
1106
1107 /* Sorry for the brute-force locking, but this is only used during
1108 * sleep and the timing seem to be critical
1109 */
1110 LOCK(flags);
1111 if (value) {
1112 /* Turn ON */
1113 if (number == 0) {
1114 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1115 (void)MACIO_IN32(KEYLARGO_FCR0);
1116 UNLOCK(flags);
1117 mdelay(1);
1118 LOCK(flags);
1119 MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1120 } else if (number == 2) {
1121 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1122 UNLOCK(flags);
1123 (void)MACIO_IN32(KEYLARGO_FCR0);
1124 mdelay(1);
1125 LOCK(flags);
1126 MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1127 } else if (number == 4) {
1128 MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1129 UNLOCK(flags);
1130 (void)MACIO_IN32(KEYLARGO_FCR1);
1131 mdelay(1);
1132 LOCK(flags);
1133 MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE);
1134 }
1135 if (number < 4) {
1136 reg = MACIO_IN32(KEYLARGO_FCR4);
1137 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1138 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number));
1139 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1140 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1));
1141 MACIO_OUT32(KEYLARGO_FCR4, reg);
1142 (void)MACIO_IN32(KEYLARGO_FCR4);
1143 udelay(10);
1144 } else {
1145 reg = MACIO_IN32(KEYLARGO_FCR3);
1146 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1147 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0));
1148 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1149 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1));
1150 MACIO_OUT32(KEYLARGO_FCR3, reg);
1151 (void)MACIO_IN32(KEYLARGO_FCR3);
1152 udelay(10);
1153 }
1154 if (macio->type == macio_intrepid) {
1155 /* wait for clock stopped bits to clear */
1156 u32 test0 = 0, test1 = 0;
1157 u32 status0, status1;
1158 int timeout = 1000;
1159
1160 UNLOCK(flags);
1161 switch (number) {
1162 case 0:
1163 test0 = UNI_N_CLOCK_STOPPED_USB0;
1164 test1 = UNI_N_CLOCK_STOPPED_USB0PCI;
1165 break;
1166 case 2:
1167 test0 = UNI_N_CLOCK_STOPPED_USB1;
1168 test1 = UNI_N_CLOCK_STOPPED_USB1PCI;
1169 break;
1170 case 4:
1171 test0 = UNI_N_CLOCK_STOPPED_USB2;
1172 test1 = UNI_N_CLOCK_STOPPED_USB2PCI;
1173 break;
1174 }
1175 do {
1176 if (--timeout <= 0) {
1177 printk(KERN_ERR "core99_usb_enable: "
1178 "Timeout waiting for clocks\n");
1179 break;
1180 }
1181 mdelay(1);
1182 status0 = UN_IN(UNI_N_CLOCK_STOP_STATUS0);
1183 status1 = UN_IN(UNI_N_CLOCK_STOP_STATUS1);
1184 } while ((status0 & test0) | (status1 & test1));
1185 LOCK(flags);
1186 }
1187 } else {
1188 /* Turn OFF */
1189 if (number < 4) {
1190 reg = MACIO_IN32(KEYLARGO_FCR4);
1191 reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1192 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number);
1193 reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1194 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1);
1195 MACIO_OUT32(KEYLARGO_FCR4, reg);
1196 (void)MACIO_IN32(KEYLARGO_FCR4);
1197 udelay(1);
1198 } else {
1199 reg = MACIO_IN32(KEYLARGO_FCR3);
1200 reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1201 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0);
1202 reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1203 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1);
1204 MACIO_OUT32(KEYLARGO_FCR3, reg);
1205 (void)MACIO_IN32(KEYLARGO_FCR3);
1206 udelay(1);
1207 }
1208 if (number == 0) {
1209 if (macio->type != macio_intrepid)
1210 MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1211 (void)MACIO_IN32(KEYLARGO_FCR0);
1212 udelay(1);
1213 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1214 (void)MACIO_IN32(KEYLARGO_FCR0);
1215 } else if (number == 2) {
1216 if (macio->type != macio_intrepid)
1217 MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1218 (void)MACIO_IN32(KEYLARGO_FCR0);
1219 udelay(1);
1220 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1221 (void)MACIO_IN32(KEYLARGO_FCR0);
1222 } else if (number == 4) {
1223 udelay(1);
1224 MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1225 (void)MACIO_IN32(KEYLARGO_FCR1);
1226 }
1227 udelay(1);
1228 }
1229 UNLOCK(flags);
1230
1231 return 0;
1232}
1233
1234static long
1235core99_firewire_enable(struct device_node *node, long param, long value)
1236{
1237 unsigned long flags;
1238 struct macio_chip *macio;
1239
1240 macio = &macio_chips[0];
1241 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1242 macio->type != macio_intrepid)
1243 return -ENODEV;
1244 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1245 return -ENODEV;
1246
1247 LOCK(flags);
1248 if (value) {
1249 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1250 (void)UN_IN(UNI_N_CLOCK_CNTL);
1251 } else {
1252 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1253 (void)UN_IN(UNI_N_CLOCK_CNTL);
1254 }
1255 UNLOCK(flags);
1256 mdelay(1);
1257
1258 return 0;
1259}
1260
1261static long
1262core99_firewire_cable_power(struct device_node *node, long param, long value)
1263{
1264 unsigned long flags;
1265 struct macio_chip *macio;
1266
1267 /* Trick: we allow NULL node */
1268 if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0)
1269 return -ENODEV;
1270 macio = &macio_chips[0];
1271 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1272 macio->type != macio_intrepid)
1273 return -ENODEV;
1274 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1275 return -ENODEV;
1276
1277 LOCK(flags);
1278 if (value) {
1279 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0);
1280 MACIO_IN8(KL_GPIO_FW_CABLE_POWER);
1281 udelay(10);
1282 } else {
1283 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4);
1284 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10);
1285 }
1286 UNLOCK(flags);
1287 mdelay(1);
1288
1289 return 0;
1290}
1291
1292static long
1293intrepid_aack_delay_enable(struct device_node *node, long param, long value)
1294{
1295 unsigned long flags;
1296
1297 if (uninorth_rev < 0xd2)
1298 return -ENODEV;
1299
1300 LOCK(flags);
1301 if (param)
1302 UN_BIS(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1303 else
1304 UN_BIC(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1305 UNLOCK(flags);
1306
1307 return 0;
1308}
1309
1310
1311#endif /* CONFIG_POWER4 */
1312
1313static long
1314core99_read_gpio(struct device_node *node, long param, long value)
1315{
1316 struct macio_chip *macio = &macio_chips[0];
1317
1318 return MACIO_IN8(param);
1319}
1320
1321
1322static long
1323core99_write_gpio(struct device_node *node, long param, long value)
1324{
1325 struct macio_chip *macio = &macio_chips[0];
1326
1327 MACIO_OUT8(param, (u8)(value & 0xff));
1328 return 0;
1329}
1330
1331#ifdef CONFIG_POWER4
1332static long g5_gmac_enable(struct device_node *node, long param, long value)
1333{
1334 struct macio_chip *macio = &macio_chips[0];
1335 unsigned long flags;
1336
1337 if (node == NULL)
1338 return -ENODEV;
1339
1340 LOCK(flags);
1341 if (value) {
1342 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1343 mb();
1344 k2_skiplist[0] = NULL;
1345 } else {
1346 k2_skiplist[0] = node;
1347 mb();
1348 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1349 }
1350
1351 UNLOCK(flags);
1352 mdelay(1);
1353
1354 return 0;
1355}
1356
1357static long g5_fw_enable(struct device_node *node, long param, long value)
1358{
1359 struct macio_chip *macio = &macio_chips[0];
1360 unsigned long flags;
1361
1362 if (node == NULL)
1363 return -ENODEV;
1364
1365 LOCK(flags);
1366 if (value) {
1367 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1368 mb();
1369 k2_skiplist[1] = NULL;
1370 } else {
1371 k2_skiplist[1] = node;
1372 mb();
1373 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1374 }
1375
1376 UNLOCK(flags);
1377 mdelay(1);
1378
1379 return 0;
1380}
1381
1382static long g5_mpic_enable(struct device_node *node, long param, long value)
1383{
1384 unsigned long flags;
1beb6a7d
BH		 1385 struct device_node *parent = of_get_parent(node);
1386 int is_u3;
14cf11af 1387
1beb6a7d
BH		 1388 if (parent == NULL)
1389 return 0;
1390 is_u3 = strcmp(parent->name, "u3") == 0 ||
1391 strcmp(parent->name, "u4") == 0;
1392 of_node_put(parent);
1393 if (!is_u3)
14cf11af
PM		 1394 return 0;
1395
1396 LOCK(flags);
1397 UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE);
1398 UNLOCK(flags);
1399
1400 return 0;
1401}
1402
1403static long g5_eth_phy_reset(struct device_node *node, long param, long value)
1404{
1405 struct macio_chip *macio = &macio_chips[0];
1406 struct device_node *phy;
1407 int need_reset;
1408
1409 /*
1410 * We must not reset the combo PHYs, only the BCM5221 found in
1411 * the iMac G5.
1412 */
1413 phy = of_get_next_child(node, NULL);
1414 if (!phy)
1415 return -ENODEV;
1416 need_reset = device_is_compatible(phy, "B5221");
1417 of_node_put(phy);
1418 if (!need_reset)
1419 return 0;
1420
1421 /* PHY reset is GPIO 29, not in device-tree unfortunately */
1422 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29,
1423 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
1424 /* Thankfully, this is now always called at a time when we can
1425 * schedule by sungem.
1426 */
1427 msleep(10);
1428 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 0);
1429
1430 return 0;
1431}
1432
1433static long g5_i2s_enable(struct device_node *node, long param, long value)
1434{
1435 /* Very crude implementation for now */
1436 struct macio_chip *macio = &macio_chips[0];
1437 unsigned long flags;
cc5d0189
BH		 1438 int cell;
1439 u32 fcrs[3][3] = {
1440 { 0,
1441 K2_FCR1_I2S0_CELL_ENABLE |
1442 K2_FCR1_I2S0_CLK_ENABLE_BIT | K2_FCR1_I2S0_ENABLE,
1443 KL3_I2S0_CLK18_ENABLE
1444 },
1445 { KL0_SCC_A_INTF_ENABLE,
1446 K2_FCR1_I2S1_CELL_ENABLE |
1447 K2_FCR1_I2S1_CLK_ENABLE_BIT | K2_FCR1_I2S1_ENABLE,
1448 KL3_I2S1_CLK18_ENABLE
1449 },
1450 { KL0_SCC_B_INTF_ENABLE,
1451 SH_FCR1_I2S2_CELL_ENABLE |
1452 SH_FCR1_I2S2_CLK_ENABLE_BIT | SH_FCR1_I2S2_ENABLE,
1453 SH_FCR3_I2S2_CLK18_ENABLE
1454 },
1455 };
1456
1beb6a7d 1457 if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
cc5d0189
BH		 1458 return -ENODEV;
1459 if (strncmp(node->name, "i2s-", 4))
1460 return -ENODEV;
1461 cell = node->name[4] - 'a';
1462 switch(cell) {
1463 case 0:
1464 case 1:
1465 break;
cc5d0189
BH		 1466 case 2:
1467 if (macio->type == macio_shasta)
1468 break;
cc5d0189
BH		 1469 default:
1470 return -ENODEV;
1471 }
14cf11af
PM		 1472
1473 LOCK(flags);
cc5d0189
BH		 1474 if (value) {
1475 MACIO_BIC(KEYLARGO_FCR0, fcrs[cell][0]);
1476 MACIO_BIS(KEYLARGO_FCR1, fcrs[cell][1]);
1477 MACIO_BIS(KEYLARGO_FCR3, fcrs[cell][2]);
1478 } else {
1479 MACIO_BIC(KEYLARGO_FCR3, fcrs[cell][2]);
1480 MACIO_BIC(KEYLARGO_FCR1, fcrs[cell][1]);
1481 MACIO_BIS(KEYLARGO_FCR0, fcrs[cell][0]);
1482 }
14cf11af 1483 udelay(10);
14cf11af 1484 UNLOCK(flags);
14cf11af
PM		 1485
1486 return 0;
1487}
1488
1489
1490#ifdef CONFIG_SMP
1491static long g5_reset_cpu(struct device_node *node, long param, long value)
1492{
1493 unsigned int reset_io = 0;
1494 unsigned long flags;
1495 struct macio_chip *macio;
1496 struct device_node *np;
1497
1498 macio = &macio_chips[0];
1beb6a7d 1499 if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
14cf11af
PM		 1500 return -ENODEV;
1501
1502 np = find_path_device("/cpus");
1503 if (np == NULL)
1504 return -ENODEV;
1505 for (np = np->child; np != NULL; np = np->sibling) {
018a3d1d
JK		 1506 const u32 *num = get_property(np, "reg", NULL);
1507 const u32 *rst = get_property(np, "soft-reset", NULL);
14cf11af
PM		 1508 if (num == NULL || rst == NULL)
1509 continue;
1510 if (param == *num) {
1511 reset_io = *rst;
1512 break;
1513 }
1514 }
1515 if (np == NULL || reset_io == 0)
1516 return -ENODEV;
1517
1518 LOCK(flags);
1519 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1520 (void)MACIO_IN8(reset_io);
1521 udelay(1);
1522 MACIO_OUT8(reset_io, 0);
1523 (void)MACIO_IN8(reset_io);
1524 UNLOCK(flags);
1525
1526 return 0;
1527}
1528#endif /* CONFIG_SMP */
1529
1530/*
1531 * This can be called from pmac_smp so isn't static
1532 *
1533 * This takes the second CPU off the bus on dual CPU machines
1534 * running UP
1535 */
1536void g5_phy_disable_cpu1(void)
1537{
1beb6a7d
BH		 1538 if (uninorth_maj == 3)
1539 UN_OUT(U3_API_PHY_CONFIG_1, 0);
14cf11af
PM		 1540}
1541#endif /* CONFIG_POWER4 */
1542
1543#ifndef CONFIG_POWER4
1544
5b9ca526
BH		 1545
1546#ifdef CONFIG_PM
0613ffbf
OH		 1547static u32 save_gpio_levels[2];
1548static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT];
1549static u8 save_gpio_normal[KEYLARGO_GPIO_CNT];
1550static u32 save_unin_clock_ctl;
5b9ca526
BH		 1551
1552static void keylargo_shutdown(struct macio_chip *macio, int sleep_mode)
14cf11af
PM		 1553{
1554 u32 temp;
1555
1556 if (sleep_mode) {
1557 mdelay(1);
1558 MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND);
1559 (void)MACIO_IN32(KEYLARGO_FCR0);
1560 mdelay(1);
1561 }
1562
1563 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1564 KL0_SCC_CELL_ENABLE |
1565 KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE |
1566 KL0_IRDA_CLK19_ENABLE);
1567
1568 MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK);
1569 MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE);
1570
1571 MACIO_BIC(KEYLARGO_FCR1,
1572 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1573 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1574 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1575 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1576 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1577 KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N |
1578 KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N |
1579 KL1_UIDE_ENABLE);
1580
1581 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1582 MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE);
1583
1584 temp = MACIO_IN32(KEYLARGO_FCR3);
1585 if (macio->rev >= 2) {
1586 temp |= KL3_SHUTDOWN_PLL2X;
1587 if (sleep_mode)
1588 temp |= KL3_SHUTDOWN_PLL_TOTAL;
1589 }
1590
1591 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1592 KL3_SHUTDOWN_PLLKW35;
1593 if (sleep_mode)
1594 temp |= KL3_SHUTDOWN_PLLKW12;
1595 temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE
1596 | KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1597 if (sleep_mode)
1598 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE);
1599 MACIO_OUT32(KEYLARGO_FCR3, temp);
1600
1601 /* Flush posted writes & wait a bit */
1602 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1603}
1604
5b9ca526 1605static void pangea_shutdown(struct macio_chip *macio, int sleep_mode)
14cf11af
PM		 1606{
1607 u32 temp;
1608
1609 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1610 KL0_SCC_CELL_ENABLE |
1611 KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE);
1612
1613 MACIO_BIC(KEYLARGO_FCR1,
1614 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1615 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1616 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1617 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1618 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1619 KL1_UIDE_ENABLE);
1620 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1621 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1622
1623 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1624
1625 temp = MACIO_IN32(KEYLARGO_FCR3);
1626 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1627 KL3_SHUTDOWN_PLLKW35;
1628 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE
1629 | KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE);
1630 if (sleep_mode)
1631 temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE);
1632 MACIO_OUT32(KEYLARGO_FCR3, temp);
1633
1634 /* Flush posted writes & wait a bit */
1635 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1636}
1637
5b9ca526 1638static void intrepid_shutdown(struct macio_chip *macio, int sleep_mode)
14cf11af
PM		 1639{
1640 u32 temp;
1641
1642 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1643 KL0_SCC_CELL_ENABLE);
1644
1645 MACIO_BIC(KEYLARGO_FCR1,
14cf11af
PM		 1646 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1647 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
c8b8b1f2
BH		 1648 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1649 KL1_EIDE0_ENABLE);
14cf11af
PM		 1650 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1651 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1652
1653 temp = MACIO_IN32(KEYLARGO_FCR3);
1654 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE |
1655 KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1656 if (sleep_mode)
1657 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE);
1658 MACIO_OUT32(KEYLARGO_FCR3, temp);
1659
1660 /* Flush posted writes & wait a bit */
1661 (void)MACIO_IN32(KEYLARGO_FCR0);
1662 mdelay(10);
1663}
1664
1665
14cf11af
PM		 1666static int
1667core99_sleep(void)
1668{
1669 struct macio_chip *macio;
1670 int i;
1671
1672 macio = &macio_chips[0];
1673 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1674 macio->type != macio_intrepid)
1675 return -ENODEV;
1676
1677 /* We power off the wireless slot in case it was not done
1678 * by the driver. We don't power it on automatically however
1679 */
1680 if (macio->flags & MACIO_FLAG_AIRPORT_ON)
1681 core99_airport_enable(macio->of_node, 0, 0);
1682
1683 /* We power off the FW cable. Should be done by the driver... */
1684 if (macio->flags & MACIO_FLAG_FW_SUPPORTED) {
1685 core99_firewire_enable(NULL, 0, 0);
1686 core99_firewire_cable_power(NULL, 0, 0);
1687 }
1688
1689 /* We make sure int. modem is off (in case driver lost it) */
1690 if (macio->type == macio_keylargo)
1691 core99_modem_enable(macio->of_node, 0, 0);
1692 else
1693 pangea_modem_enable(macio->of_node, 0, 0);
1694
1695 /* We make sure the sound is off as well */
1696 core99_sound_chip_enable(macio->of_node, 0, 0);
1697
1698 /*
1699 * Save various bits of KeyLargo
1700 */
1701
1702 /* Save the state of the various GPIOs */
1703 save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0);
1704 save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1);
1705 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1706 save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i);
1707 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1708 save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i);
1709
1710 /* Save the FCRs */
1711 if (macio->type == macio_keylargo)
1712 save_mbcr = MACIO_IN32(KEYLARGO_MBCR);
1713 save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0);
1714 save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1);
1715 save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2);
1716 save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3);
1717 save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4);
1718 if (macio->type == macio_pangea || macio->type == macio_intrepid)
1719 save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5);
1720
1721 /* Save state & config of DBDMA channels */
1722 dbdma_save(macio, save_dbdma);
1723
1724 /*
1725 * Turn off as much as we can
1726 */
1727 if (macio->type == macio_pangea)
1728 pangea_shutdown(macio, 1);
1729 else if (macio->type == macio_intrepid)
1730 intrepid_shutdown(macio, 1);
1731 else if (macio->type == macio_keylargo)
1732 keylargo_shutdown(macio, 1);
1733
1734 /*
1735 * Put the host bridge to sleep
1736 */
1737
1738 save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL);
1739 /* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it
1740 * enabled !
1741 */
1742 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl &
1743 ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/));
1744 udelay(100);
1745 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1746 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP);
1747 mdelay(10);
1748
1749 /*
1750 * FIXME: A bit of black magic with OpenPIC (don't ask me why)
1751 */
1752 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1753 MACIO_BIS(0x506e0, 0x00400000);
1754 MACIO_BIS(0x506e0, 0x80000000);
1755 }
1756 return 0;
1757}
1758
1759static int
1760core99_wake_up(void)
1761{
1762 struct macio_chip *macio;
1763 int i;
1764
1765 macio = &macio_chips[0];
1766 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1767 macio->type != macio_intrepid)
1768 return -ENODEV;
1769
1770 /*
1771 * Wakeup the host bridge
1772 */
1773 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1774 udelay(10);
1775 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1776 udelay(10);
1777
1778 /*
1779 * Restore KeyLargo
1780 */
1781
1782 if (macio->type == macio_keylargo) {
1783 MACIO_OUT32(KEYLARGO_MBCR, save_mbcr);
1784 (void)MACIO_IN32(KEYLARGO_MBCR); udelay(10);
1785 }
1786 MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]);
1787 (void)MACIO_IN32(KEYLARGO_FCR0); udelay(10);
1788 MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]);
1789 (void)MACIO_IN32(KEYLARGO_FCR1); udelay(10);
1790 MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]);
1791 (void)MACIO_IN32(KEYLARGO_FCR2); udelay(10);
1792 MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]);
1793 (void)MACIO_IN32(KEYLARGO_FCR3); udelay(10);
1794 MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]);
1795 (void)MACIO_IN32(KEYLARGO_FCR4); udelay(10);
1796 if (macio->type == macio_pangea || macio->type == macio_intrepid) {
1797 MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]);
1798 (void)MACIO_IN32(KEYLARGO_FCR5); udelay(10);
1799 }
1800
1801 dbdma_restore(macio, save_dbdma);
1802
1803 MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]);
1804 MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]);
1805 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1806 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]);
1807 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1808 MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]);
1809
1810 /* FIXME more black magic with OpenPIC ... */
1811 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1812 MACIO_BIC(0x506e0, 0x00400000);
1813 MACIO_BIC(0x506e0, 0x80000000);
1814 }
1815
1816 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl);
1817 udelay(100);
1818
1819 return 0;
1820}
1821
5b9ca526
BH		 1822#endif /* CONFIG_PM */
1823
14cf11af
PM		 1824static long
1825core99_sleep_state(struct device_node *node, long param, long value)
1826{
1827 /* Param == 1 means to enter the "fake sleep" mode that is
1828 * used for CPU speed switch
1829 */
1830 if (param == 1) {
1831 if (value == 1) {
1832 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1833 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2);
1834 } else {
1835 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1836 udelay(10);
1837 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1838 udelay(10);
1839 }
1840 return 0;
1841 }
1842 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
1843 return -EPERM;
1844
5b9ca526 1845#ifdef CONFIG_PM
14cf11af
PM		 1846 if (value == 1)
1847 return core99_sleep();
1848 else if (value == 0)
1849 return core99_wake_up();
5b9ca526
BH		 1850
1851#endif /* CONFIG_PM */
14cf11af
PM		 1852 return 0;
1853}
1854
1855#endif /* CONFIG_POWER4 */
1856
1857static long
1858generic_dev_can_wake(struct device_node *node, long param, long value)
1859{
1860 /* Todo: eventually check we are really dealing with on-board
1861 * video device ...
1862 */
1863
1864 if (pmac_mb.board_flags & PMAC_MB_MAY_SLEEP)
1865 pmac_mb.board_flags |= PMAC_MB_CAN_SLEEP;
1866 return 0;
1867}
1868
1869static long generic_get_mb_info(struct device_node *node, long param, long value)
1870{
1871 switch(param) {
1872 case PMAC_MB_INFO_MODEL:
1873 return pmac_mb.model_id;
1874 case PMAC_MB_INFO_FLAGS:
1875 return pmac_mb.board_flags;
1876 case PMAC_MB_INFO_NAME:
1877 /* hack hack hack... but should work */
1878 *((const char **)value) = pmac_mb.model_name;
1879 return 0;
1880 }
1881 return -EINVAL;
1882}
1883
1884
1885/*
1886 * Table definitions
1887 */
1888
1889/* Used on any machine
1890 */
1891static struct feature_table_entry any_features[] = {
1892 { PMAC_FTR_GET_MB_INFO, generic_get_mb_info },
1893 { PMAC_FTR_DEVICE_CAN_WAKE, generic_dev_can_wake },
1894 { 0, NULL }
1895};
1896
1897#ifndef CONFIG_POWER4
1898
1899/* OHare based motherboards. Currently, we only use these on the
1900 * 2400,3400 and 3500 series powerbooks. Some older desktops seem
1901 * to have issues with turning on/off those asic cells
1902 */
1903static struct feature_table_entry ohare_features[] = {
1904 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1905 { PMAC_FTR_SWIM3_ENABLE, ohare_floppy_enable },
1906 { PMAC_FTR_MESH_ENABLE, ohare_mesh_enable },
1907 { PMAC_FTR_IDE_ENABLE, ohare_ide_enable},
1908 { PMAC_FTR_IDE_RESET, ohare_ide_reset},
1909 { PMAC_FTR_SLEEP_STATE, ohare_sleep_state },
1910 { 0, NULL }
1911};
1912
1913/* Heathrow desktop machines (Beige G3).
1914 * Separated as some features couldn't be properly tested
1915 * and the serial port control bits appear to confuse it.
1916 */
1917static struct feature_table_entry heathrow_desktop_features[] = {
1918 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1919 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1920 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1921 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1922 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1923 { 0, NULL }
1924};
1925
1926/* Heathrow based laptop, that is the Wallstreet and mainstreet
1927 * powerbooks.
1928 */
1929static struct feature_table_entry heathrow_laptop_features[] = {
1930 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1931 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
1932 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1933 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1934 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1935 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1936 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1937 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
1938 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
1939 { 0, NULL }
1940};
1941
1942/* Paddington based machines
1943 * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4.
1944 */
1945static struct feature_table_entry paddington_features[] = {
1946 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1947 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
1948 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1949 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1950 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1951 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1952 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1953 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
1954 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
1955 { 0, NULL }
1956};
1957
1958/* Core99 & MacRISC 2 machines (all machines released since the
1959 * iBook (included), that is all AGP machines, except pangea
1960 * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo
1961 * used on iBook2 & iMac "flow power".
1962 */
1963static struct feature_table_entry core99_features[] = {
1964 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
1965 { PMAC_FTR_MODEM_ENABLE, core99_modem_enable },
1966 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
1967 { PMAC_FTR_IDE_RESET, core99_ide_reset },
1968 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
1969 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
1970 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
1971 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
1972 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
1973 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
1974 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
5b9ca526 1975#ifdef CONFIG_PM
14cf11af 1976 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
5b9ca526 1977#endif
14cf11af
PM		 1978#ifdef CONFIG_SMP
1979 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
1980#endif /* CONFIG_SMP */
1981 { PMAC_FTR_READ_GPIO, core99_read_gpio },
1982 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
1983 { 0, NULL }
1984};
1985
1986/* RackMac
1987 */
1988static struct feature_table_entry rackmac_features[] = {
1989 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
1990 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
1991 { PMAC_FTR_IDE_RESET, core99_ide_reset },
1992 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
1993 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
1994 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
1995 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
1996 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
1997 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
1998#ifdef CONFIG_SMP
1999 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
2000#endif /* CONFIG_SMP */
2001 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2002 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2003 { 0, NULL }
2004};
2005
2006/* Pangea features
2007 */
2008static struct feature_table_entry pangea_features[] = {
2009 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2010 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
2011 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2012 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2013 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2014 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2015 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2016 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2017 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2018 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2019 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2020 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2021 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2022 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2023 { 0, NULL }
2024};
2025
2026/* Intrepid features
2027 */
2028static struct feature_table_entry intrepid_features[] = {
2029 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2030 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
2031 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2032 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2033 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2034 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2035 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2036 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2037 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2038 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2039 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2040 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2041 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2042 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2043 { PMAC_FTR_AACK_DELAY_ENABLE, intrepid_aack_delay_enable },
2044 { 0, NULL }
2045};
2046
2047#else /* CONFIG_POWER4 */
2048
2049/* G5 features
2050 */
2051static struct feature_table_entry g5_features[] = {
2052 { PMAC_FTR_GMAC_ENABLE, g5_gmac_enable },
2053 { PMAC_FTR_1394_ENABLE, g5_fw_enable },
2054 { PMAC_FTR_ENABLE_MPIC, g5_mpic_enable },
2055 { PMAC_FTR_GMAC_PHY_RESET, g5_eth_phy_reset },
2056 { PMAC_FTR_SOUND_CHIP_ENABLE, g5_i2s_enable },
2057#ifdef CONFIG_SMP
2058 { PMAC_FTR_RESET_CPU, g5_reset_cpu },
2059#endif /* CONFIG_SMP */
2060 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2061 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2062 { 0, NULL }
2063};
2064
2065#endif /* CONFIG_POWER4 */
2066
2067static struct pmac_mb_def pmac_mb_defs[] = {
2068#ifndef CONFIG_POWER4
2069 /*
2070 * Desktops
2071 */
2072
2073 { "AAPL,8500", "PowerMac 8500/8600",
2074 PMAC_TYPE_PSURGE, NULL,
2075 0
2076 },
2077 { "AAPL,9500", "PowerMac 9500/9600",
2078 PMAC_TYPE_PSURGE, NULL,
2079 0
2080 },
2081 { "AAPL,7200", "PowerMac 7200",
2082 PMAC_TYPE_PSURGE, NULL,
2083 0
2084 },
2085 { "AAPL,7300", "PowerMac 7200/7300",
2086 PMAC_TYPE_PSURGE, NULL,
2087 0
2088 },
2089 { "AAPL,7500", "PowerMac 7500",
2090 PMAC_TYPE_PSURGE, NULL,
2091 0
2092 },
2093 { "AAPL,ShinerESB", "Apple Network Server",
2094 PMAC_TYPE_ANS, NULL,
2095 0
2096 },
2097 { "AAPL,e407", "Alchemy",
2098 PMAC_TYPE_ALCHEMY, NULL,
2099 0
2100 },
2101 { "AAPL,e411", "Gazelle",
2102 PMAC_TYPE_GAZELLE, NULL,
2103 0
2104 },
2105 { "AAPL,Gossamer", "PowerMac G3 (Gossamer)",
2106 PMAC_TYPE_GOSSAMER, heathrow_desktop_features,
2107 0
2108 },
2109 { "AAPL,PowerMac G3", "PowerMac G3 (Silk)",
2110 PMAC_TYPE_SILK, heathrow_desktop_features,
2111 0
2112 },
2113 { "PowerMac1,1", "Blue&White G3",
2114 PMAC_TYPE_YOSEMITE, paddington_features,
2115 0
2116 },
2117 { "PowerMac1,2", "PowerMac G4 PCI Graphics",
2118 PMAC_TYPE_YIKES, paddington_features,
2119 0
2120 },
2121 { "PowerMac2,1", "iMac FireWire",
2122 PMAC_TYPE_FW_IMAC, core99_features,
2123 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2124 },
2125 { "PowerMac2,2", "iMac FireWire",
2126 PMAC_TYPE_FW_IMAC, core99_features,
2127 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2128 },
2129 { "PowerMac3,1", "PowerMac G4 AGP Graphics",
2130 PMAC_TYPE_SAWTOOTH, core99_features,
2131 PMAC_MB_OLD_CORE99
2132 },
2133 { "PowerMac3,2", "PowerMac G4 AGP Graphics",
2134 PMAC_TYPE_SAWTOOTH, core99_features,
2135 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2136 },
2137 { "PowerMac3,3", "PowerMac G4 AGP Graphics",
2138 PMAC_TYPE_SAWTOOTH, core99_features,
2139 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2140 },
2141 { "PowerMac3,4", "PowerMac G4 Silver",
2142 PMAC_TYPE_QUICKSILVER, core99_features,
2143 PMAC_MB_MAY_SLEEP
2144 },
2145 { "PowerMac3,5", "PowerMac G4 Silver",
2146 PMAC_TYPE_QUICKSILVER, core99_features,
2147 PMAC_MB_MAY_SLEEP
2148 },
2149 { "PowerMac3,6", "PowerMac G4 Windtunnel",
2150 PMAC_TYPE_WINDTUNNEL, core99_features,
2151 PMAC_MB_MAY_SLEEP,
2152 },
2153 { "PowerMac4,1", "iMac \"Flower Power\"",
2154 PMAC_TYPE_PANGEA_IMAC, pangea_features,
2155 PMAC_MB_MAY_SLEEP
2156 },
2157 { "PowerMac4,2", "Flat panel iMac",
2158 PMAC_TYPE_FLAT_PANEL_IMAC, pangea_features,
2159 PMAC_MB_CAN_SLEEP
2160 },
2161 { "PowerMac4,4", "eMac",
2162 PMAC_TYPE_EMAC, core99_features,
2163 PMAC_MB_MAY_SLEEP
2164 },
2165 { "PowerMac5,1", "PowerMac G4 Cube",
2166 PMAC_TYPE_CUBE, core99_features,
2167 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2168 },
2169 { "PowerMac6,1", "Flat panel iMac",
2170 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2171 PMAC_MB_MAY_SLEEP,
2172 },
2173 { "PowerMac6,3", "Flat panel iMac",
2174 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2175 PMAC_MB_MAY_SLEEP,
2176 },
2177 { "PowerMac6,4", "eMac",
2178 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2179 PMAC_MB_MAY_SLEEP,
2180 },
2181 { "PowerMac10,1", "Mac mini",
2182 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
c8b8b1f2 2183 PMAC_MB_MAY_SLEEP,
14cf11af
PM		 2184 },
2185 { "iMac,1", "iMac (first generation)",
2186 PMAC_TYPE_ORIG_IMAC, paddington_features,
2187 0
2188 },
2189
2190 /*
2191 * Xserve's
2192 */
2193
2194 { "RackMac1,1", "XServe",
2195 PMAC_TYPE_RACKMAC, rackmac_features,
2196 0,
2197 },
2198 { "RackMac1,2", "XServe rev. 2",
2199 PMAC_TYPE_RACKMAC, rackmac_features,
2200 0,
2201 },
2202
2203 /*
2204 * Laptops
2205 */
2206
2207 { "AAPL,3400/2400", "PowerBook 3400",
2208 PMAC_TYPE_HOOPER, ohare_features,
2209 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2210 },
2211 { "AAPL,3500", "PowerBook 3500",
2212 PMAC_TYPE_KANGA, ohare_features,
2213 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2214 },
2215 { "AAPL,PowerBook1998", "PowerBook Wallstreet",
2216 PMAC_TYPE_WALLSTREET, heathrow_laptop_features,
2217 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2218 },
2219 { "PowerBook1,1", "PowerBook 101 (Lombard)",
2220 PMAC_TYPE_101_PBOOK, paddington_features,
2221 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2222 },
2223 { "PowerBook2,1", "iBook (first generation)",
2224 PMAC_TYPE_ORIG_IBOOK, core99_features,
2225 PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2226 },
2227 { "PowerBook2,2", "iBook FireWire",
2228 PMAC_TYPE_FW_IBOOK, core99_features,
2229 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2230 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2231 },
2232 { "PowerBook3,1", "PowerBook Pismo",
2233 PMAC_TYPE_PISMO, core99_features,
2234 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2235 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2236 },
2237 { "PowerBook3,2", "PowerBook Titanium",
2238 PMAC_TYPE_TITANIUM, core99_features,
2239 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2240 },
2241 { "PowerBook3,3", "PowerBook Titanium II",
2242 PMAC_TYPE_TITANIUM2, core99_features,
2243 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2244 },
2245 { "PowerBook3,4", "PowerBook Titanium III",
2246 PMAC_TYPE_TITANIUM3, core99_features,
2247 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2248 },
2249 { "PowerBook3,5", "PowerBook Titanium IV",
2250 PMAC_TYPE_TITANIUM4, core99_features,
2251 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2252 },
2253 { "PowerBook4,1", "iBook 2",
2254 PMAC_TYPE_IBOOK2, pangea_features,
2255 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2256 },
2257 { "PowerBook4,2", "iBook 2",
2258 PMAC_TYPE_IBOOK2, pangea_features,
2259 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2260 },
2261 { "PowerBook4,3", "iBook 2 rev. 2",
2262 PMAC_TYPE_IBOOK2, pangea_features,
2263 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2264 },
2265 { "PowerBook5,1", "PowerBook G4 17\"",
2266 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2267 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2268 },
2269 { "PowerBook5,2", "PowerBook G4 15\"",
2270 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2271 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2272 },
2273 { "PowerBook5,3", "PowerBook G4 17\"",
2274 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2275 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2276 },
2277 { "PowerBook5,4", "PowerBook G4 15\"",
2278 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2279 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2280 },
2281 { "PowerBook5,5", "PowerBook G4 17\"",
2282 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2283 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2284 },
2285 { "PowerBook5,6", "PowerBook G4 15\"",
2286 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2287 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2288 },
2289 { "PowerBook5,7", "PowerBook G4 17\"",
2290 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2291 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2292 },
950fc002
OJ		 2293 { "PowerBook5,8", "PowerBook G4 15\"",
2294 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
c8b8b1f2 2295 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE,
950fc002
OJ		 2296 },
2297 { "PowerBook5,9", "PowerBook G4 17\"",
2298 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
c8b8b1f2 2299 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE,
950fc002 2300 },
14cf11af
PM		 2301 { "PowerBook6,1", "PowerBook G4 12\"",
2302 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2303 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2304 },
2305 { "PowerBook6,2", "PowerBook G4",
2306 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2307 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2308 },
2309 { "PowerBook6,3", "iBook G4",
2310 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2311 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2312 },
2313 { "PowerBook6,4", "PowerBook G4 12\"",
2314 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2315 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2316 },
2317 { "PowerBook6,5", "iBook G4",
2318 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
5629d41d
PM		 2319 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2320 },
2321 { "PowerBook6,7", "iBook G4",
2322 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
14cf11af
PM		 2323 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2324 },
2325 { "PowerBook6,8", "PowerBook G4 12\"",
2326 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2327 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2328 },
2329#else /* CONFIG_POWER4 */
2330 { "PowerMac7,2", "PowerMac G5",
2331 PMAC_TYPE_POWERMAC_G5, g5_features,
2332 0,
2333 },
2334#ifdef CONFIG_PPC64
2335 { "PowerMac7,3", "PowerMac G5",
2336 PMAC_TYPE_POWERMAC_G5, g5_features,
2337 0,
2338 },
2339 { "PowerMac8,1", "iMac G5",
2340 PMAC_TYPE_IMAC_G5, g5_features,
2341 0,
2342 },
2343 { "PowerMac9,1", "PowerMac G5",
2344 PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
2345 0,
2346 },
1beb6a7d
BH		 2347 { "PowerMac11,2", "PowerMac G5 Dual Core",
2348 PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
2349 0,
2350 },
2351 { "PowerMac12,1", "iMac G5 (iSight)",
2352 PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
2353 0,
2354 },
14cf11af
PM		 2355 { "RackMac3,1", "XServe G5",
2356 PMAC_TYPE_XSERVE_G5, g5_features,
2357 0,
2358 },
2359#endif /* CONFIG_PPC64 */
2360#endif /* CONFIG_POWER4 */
2361};
2362
2363/*
2364 * The toplevel feature_call callback
2365 */
2366long pmac_do_feature_call(unsigned int selector, ...)
2367{
2368 struct device_node *node;
2369 long param, value;
2370 int i;
2371 feature_call func = NULL;
2372 va_list args;
2373
2374 if (pmac_mb.features)
2375 for (i=0; pmac_mb.features[i].function; i++)
2376 if (pmac_mb.features[i].selector == selector) {
2377 func = pmac_mb.features[i].function;
2378 break;
2379 }
2380 if (!func)
2381 for (i=0; any_features[i].function; i++)
2382 if (any_features[i].selector == selector) {
2383 func = any_features[i].function;
2384 break;
2385 }
2386 if (!func)
2387 return -ENODEV;
2388
2389 va_start(args, selector);
2390 node = (struct device_node*)va_arg(args, void*);
2391 param = va_arg(args, long);
2392 value = va_arg(args, long);
2393 va_end(args);
2394
2395 return func(node, param, value);
2396}
2397
2398static int __init probe_motherboard(void)
2399{
2400 int i;
2401 struct macio_chip *macio = &macio_chips[0];
2402 const char *model = NULL;
2403 struct device_node *dt;
2404
2405 /* Lookup known motherboard type in device-tree. First try an
2406 * exact match on the "model" property, then try a "compatible"
2407 * match is none is found.
2408 */
2409 dt = find_devices("device-tree");
2410 if (dt != NULL)
018a3d1d 2411 model = get_property(dt, "model", NULL);
14cf11af
PM		 2412 for(i=0; model && i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
2413 if (strcmp(model, pmac_mb_defs[i].model_string) == 0) {
2414 pmac_mb = pmac_mb_defs[i];
2415 goto found;
2416 }
2417 }
2418 for(i=0; i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
2419 if (machine_is_compatible(pmac_mb_defs[i].model_string)) {
2420 pmac_mb = pmac_mb_defs[i];
2421 goto found;
2422 }
2423 }
2424
2425 /* Fallback to selection depending on mac-io chip type */
2426 switch(macio->type) {
2427#ifndef CONFIG_POWER4
2428 case macio_grand_central:
2429 pmac_mb.model_id = PMAC_TYPE_PSURGE;
2430 pmac_mb.model_name = "Unknown PowerSurge";
2431 break;
2432 case macio_ohare:
2433 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE;
2434 pmac_mb.model_name = "Unknown OHare-based";
2435 break;
2436 case macio_heathrow:
2437 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW;
2438 pmac_mb.model_name = "Unknown Heathrow-based";
2439 pmac_mb.features = heathrow_desktop_features;
2440 break;
2441 case macio_paddington:
2442 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON;
2443 pmac_mb.model_name = "Unknown Paddington-based";
2444 pmac_mb.features = paddington_features;
2445 break;
2446 case macio_keylargo:
2447 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99;
2448 pmac_mb.model_name = "Unknown Keylargo-based";
2449 pmac_mb.features = core99_features;
2450 break;
2451 case macio_pangea:
2452 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA;
2453 pmac_mb.model_name = "Unknown Pangea-based";
2454 pmac_mb.features = pangea_features;
2455 break;
2456 case macio_intrepid:
2457 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID;
2458 pmac_mb.model_name = "Unknown Intrepid-based";
2459 pmac_mb.features = intrepid_features;
2460 break;
2461#else /* CONFIG_POWER4 */
2462 case macio_keylargo2:
2463 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2;
2464 pmac_mb.model_name = "Unknown K2-based";
2465 pmac_mb.features = g5_features;
2466 break;
1beb6a7d
BH		 2467 case macio_shasta:
2468 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_SHASTA;
2469 pmac_mb.model_name = "Unknown Shasta-based";
2470 pmac_mb.features = g5_features;
2471 break;
14cf11af
PM		 2472#endif /* CONFIG_POWER4 */
2473 default:
2474 return -ENODEV;
2475 }
2476found:
2477#ifndef CONFIG_POWER4
2478 /* Fixup Hooper vs. Comet */
2479 if (pmac_mb.model_id == PMAC_TYPE_HOOPER) {
2480 u32 __iomem * mach_id_ptr = ioremap(0xf3000034, 4);
2481 if (!mach_id_ptr)
2482 return -ENODEV;
2483 /* Here, I used to disable the media-bay on comet. It
2484 * appears this is wrong, the floppy connector is actually
2485 * a kind of media-bay and works with the current driver.
2486 */
2487 if (__raw_readl(mach_id_ptr) & 0x20000000UL)
2488 pmac_mb.model_id = PMAC_TYPE_COMET;
2489 iounmap(mach_id_ptr);
2490 }
14cf11af 2491
14cf11af
PM		 2492 /* Set default value of powersave_nap on machines that support it.
2493 * It appears that uninorth rev 3 has a problem with it, we don't
2494 * enable it on those. In theory, the flush-on-lock property is
2495 * supposed to be set when not supported, but I'm not very confident
2496 * that all Apple OF revs did it properly, I do it the paranoid way.
2497 */
2498 while (uninorth_base && uninorth_rev > 3) {
2499 struct device_node *np = find_path_device("/cpus");
2500 if (!np || !np->child) {
2501 printk(KERN_WARNING "Can't find CPU(s) in device tree !\n");
2502 break;
2503 }
2504 np = np->child;
2505 /* Nap mode not supported on SMP */
2506 if (np->sibling)
2507 break;
2508 /* Nap mode not supported if flush-on-lock property is present */
2509 if (get_property(np, "flush-on-lock", NULL))
2510 break;
2511 powersave_nap = 1;
4baaf0cf 2512 printk(KERN_DEBUG "Processor NAP mode on idle enabled.\n");
14cf11af
PM		 2513 break;
2514 }
2515
2516 /* On CPUs that support it (750FX), lowspeed by default during
2517 * NAP mode
2518 */
2519 powersave_lowspeed = 1;
c6cb3b5f
BH		 2520
2521#else /* CONFIG_POWER4 */
14cf11af 2522 powersave_nap = 1;
c6cb3b5f
BH		 2523#endif /* CONFIG_POWER4 */
2524
14cf11af
PM		 2525 /* Check for "mobile" machine */
2526 if (model && (strncmp(model, "PowerBook", 9) == 0
2527 || strncmp(model, "iBook", 5) == 0))
2528 pmac_mb.board_flags |= PMAC_MB_MOBILE;
2529
2530
2531 printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name);
2532 return 0;
2533}
2534
2535/* Initialize the Core99 UniNorth host bridge and memory controller
2536 */
2537static void __init probe_uninorth(void)
2538{
018a3d1d 2539 const u32 *addrp;
51d3082f 2540 phys_addr_t address;
14cf11af
PM		 2541 unsigned long actrl;
2542
2543 /* Locate core99 Uni-N */
2544 uninorth_node = of_find_node_by_name(NULL, "uni-n");
2545 /* Locate G5 u3 */
2546 if (uninorth_node == NULL) {
2547 uninorth_node = of_find_node_by_name(NULL, "u3");
1beb6a7d
BH		 2548 uninorth_maj = 3;
2549 }
2550 /* Locate G5 u4 */
2551 if (uninorth_node == NULL) {
2552 uninorth_node = of_find_node_by_name(NULL, "u4");
2553 uninorth_maj = 4;
14cf11af 2554 }
51d3082f 2555 if (uninorth_node == NULL)
14cf11af
PM		 2556 return;
2557
018a3d1d 2558 addrp = get_property(uninorth_node, "reg", NULL);
51d3082f
BH		 2559 if (addrp == NULL)
2560 return;
2561 address = of_translate_address(uninorth_node, addrp);
2562 if (address == 0)
2563 return;
2564 uninorth_base = ioremap(address, 0x40000);
2565 uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
1beb6a7d 2566 if (uninorth_maj == 3 || uninorth_maj == 4)
5b9ca526 2567 u3_ht_base = ioremap(address + U3_HT_CONFIG_BASE, 0x1000);
51d3082f 2568
1beb6a7d
BH		 2569 printk(KERN_INFO "Found %s memory controller & host bridge"
2570 " @ 0x%08x revision: 0x%02x\n", uninorth_maj == 3 ? "U3" :
2571 uninorth_maj == 4 ? "U4" : "UniNorth",
2572 (unsigned int)address, uninorth_rev);
14cf11af
PM		 2573 printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base);
2574
2575 /* Set the arbitrer QAck delay according to what Apple does
2576 */
2577 if (uninorth_rev < 0x11) {
2578 actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK;
2579 actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 :
1beb6a7d
BH		 2580 UNI_N_ARB_CTRL_QACK_DELAY) <<
2581 UNI_N_ARB_CTRL_QACK_DELAY_SHIFT;
14cf11af
PM		 2582 UN_OUT(UNI_N_ARB_CTRL, actrl);
2583 }
2584
2585 /* Some more magic as done by them in recent MacOS X on UniNorth
2586 * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI
2587 * memory timeout
2588 */
1beb6a7d
BH		 2589 if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) ||
2590 uninorth_rev == 0xc0)
14cf11af
PM		 2591 UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff);
2592}
2593
2594static void __init probe_one_macio(const char *name, const char *compat, int type)
2595{
2596 struct device_node* node;
2597 int i;
51d3082f 2598 volatile u32 __iomem *base;
018a3d1d 2599 const u32 *addrp, *revp;
51d3082f
BH		 2600 phys_addr_t addr;
2601 u64 size;
14cf11af 2602
51d3082f
BH		 2603 for (node = NULL; (node = of_find_node_by_name(node, name)) != NULL;) {
2604 if (!compat)
2605 break;
2606 if (device_is_compatible(node, compat))
2607 break;
2608 }
14cf11af
PM		 2609 if (!node)
2610 return;
2611 for(i=0; i<MAX_MACIO_CHIPS; i++) {
2612 if (!macio_chips[i].of_node)
2613 break;
2614 if (macio_chips[i].of_node == node)
2615 return;
2616 }
51d3082f 2617
14cf11af
PM		 2618 if (i >= MAX_MACIO_CHIPS) {
2619 printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n");
2620 printk(KERN_ERR "pmac_feature: %s skipped\n", node->full_name);
2621 return;
2622 }
d2dd482b 2623 addrp = of_get_pci_address(node, 0, &size, NULL);
51d3082f
BH		 2624 if (addrp == NULL) {
2625 printk(KERN_ERR "pmac_feature: %s: can't find base !\n",
2626 node->full_name);
2627 return;
2628 }
2629 addr = of_translate_address(node, addrp);
2630 if (addr == 0) {
2631 printk(KERN_ERR "pmac_feature: %s, can't translate base !\n",
2632 node->full_name);
2633 return;
2634 }
2635 base = ioremap(addr, (unsigned long)size);
14cf11af 2636 if (!base) {
51d3082f
BH		 2637 printk(KERN_ERR "pmac_feature: %s, can't map mac-io chip !\n",
2638 node->full_name);
14cf11af
PM		 2639 return;
2640 }
1beb6a7d 2641 if (type == macio_keylargo || type == macio_keylargo2) {
018a3d1d 2642 const u32 *did = get_property(node, "device-id", NULL);
14cf11af
PM		 2643 if (*did == 0x00000025)
2644 type = macio_pangea;
2645 if (*did == 0x0000003e)
2646 type = macio_intrepid;
1beb6a7d
BH		 2647 if (*did == 0x0000004f)
2648 type = macio_shasta;
14cf11af
PM		 2649 }
2650 macio_chips[i].of_node = node;
2651 macio_chips[i].type = type;
2652 macio_chips[i].base = base;
2653 macio_chips[i].flags = MACIO_FLAG_SCCB_ON | MACIO_FLAG_SCCB_ON;
2654 macio_chips[i].name = macio_names[type];
018a3d1d 2655 revp = get_property(node, "revision-id", NULL);
14cf11af
PM		 2656 if (revp)
2657 macio_chips[i].rev = *revp;
2658 printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n",
2659 macio_names[type], macio_chips[i].rev, macio_chips[i].base);
2660}
2661
2662static int __init
2663probe_macios(void)
2664{
2665 /* Warning, ordering is important */
2666 probe_one_macio("gc", NULL, macio_grand_central);
2667 probe_one_macio("ohare", NULL, macio_ohare);
2668 probe_one_macio("pci106b,7", NULL, macio_ohareII);
2669 probe_one_macio("mac-io", "keylargo", macio_keylargo);
2670 probe_one_macio("mac-io", "paddington", macio_paddington);
2671 probe_one_macio("mac-io", "gatwick", macio_gatwick);
2672 probe_one_macio("mac-io", "heathrow", macio_heathrow);
2673 probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2);
2674
2675 /* Make sure the "main" macio chip appear first */
2676 if (macio_chips[0].type == macio_gatwick
2677 && macio_chips[1].type == macio_heathrow) {
2678 struct macio_chip temp = macio_chips[0];
2679 macio_chips[0] = macio_chips[1];
2680 macio_chips[1] = temp;
2681 }
2682 if (macio_chips[0].type == macio_ohareII
2683 && macio_chips[1].type == macio_ohare) {
2684 struct macio_chip temp = macio_chips[0];
2685 macio_chips[0] = macio_chips[1];
2686 macio_chips[1] = temp;
2687 }
2688 macio_chips[0].lbus.index = 0;
2689 macio_chips[1].lbus.index = 1;
2690
2691 return (macio_chips[0].of_node == NULL) ? -ENODEV : 0;
2692}
2693
2694static void __init
2695initial_serial_shutdown(struct device_node *np)
2696{
2697 int len;
018a3d1d 2698 const struct slot_names_prop {
14cf11af
PM		 2699 int count;
2700 char name[1];
2701 } *slots;
018a3d1d 2702 const char *conn;
14cf11af
PM		 2703 int port_type = PMAC_SCC_ASYNC;
2704 int modem = 0;
2705
018a3d1d 2706 slots = get_property(np, "slot-names", &len);
14cf11af
PM		 2707 conn = get_property(np, "AAPL,connector", &len);
2708 if (conn && (strcmp(conn, "infrared") == 0))
2709 port_type = PMAC_SCC_IRDA;
2710 else if (device_is_compatible(np, "cobalt"))
2711 modem = 1;
2712 else if (slots && slots->count > 0) {
2713 if (strcmp(slots->name, "IrDA") == 0)
2714 port_type = PMAC_SCC_IRDA;
2715 else if (strcmp(slots->name, "Modem") == 0)
2716 modem = 1;
2717 }
2718 if (modem)
2719 pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0);
2720 pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0);
2721}
2722
2723static void __init
2724set_initial_features(void)
2725{
2726 struct device_node *np;
2727
2728 /* That hack appears to be necessary for some StarMax motherboards
2729 * but I'm not too sure it was audited for side-effects on other
2730 * ohare based machines...
2731 * Since I still have difficulties figuring the right way to
2732 * differenciate them all and since that hack was there for a long
2733 * time, I'll keep it around
2734 */
2735 if (macio_chips[0].type == macio_ohare && !find_devices("via-pmu")) {
2736 struct macio_chip *macio = &macio_chips[0];
2737 MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES);
2738 } else if (macio_chips[0].type == macio_ohare) {
2739 struct macio_chip *macio = &macio_chips[0];
2740 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2741 } else if (macio_chips[1].type == macio_ohare) {
2742 struct macio_chip *macio = &macio_chips[1];
2743 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2744 }
2745
2746#ifdef CONFIG_POWER4
1beb6a7d
BH		 2747 if (macio_chips[0].type == macio_keylargo2 ||
2748 macio_chips[0].type == macio_shasta) {
14cf11af
PM		 2749#ifndef CONFIG_SMP
2750 /* On SMP machines running UP, we have the second CPU eating
2751 * bus cycles. We need to take it off the bus. This is done
2752 * from pmac_smp for SMP kernels running on one CPU
2753 */
2754 np = of_find_node_by_type(NULL, "cpu");
2755 if (np != NULL)
2756 np = of_find_node_by_type(np, "cpu");
2757 if (np != NULL) {
2758 g5_phy_disable_cpu1();
2759 of_node_put(np);
2760 }
2761#endif /* CONFIG_SMP */
2762 /* Enable GMAC for now for PCI probing. It will be disabled
2763 * later on after PCI probe
2764 */
2765 np = of_find_node_by_name(NULL, "ethernet");
2766 while(np) {
2767 if (device_is_compatible(np, "K2-GMAC"))
2768 g5_gmac_enable(np, 0, 1);
2769 np = of_find_node_by_name(np, "ethernet");
2770 }
2771
2772 /* Enable FW before PCI probe. Will be disabled later on
2773 * Note: We should have a batter way to check that we are
2774 * dealing with uninorth internal cell and not a PCI cell
2775 * on the external PCI. The code below works though.
2776 */
2777 np = of_find_node_by_name(NULL, "firewire");
2778 while(np) {
2779 if (device_is_compatible(np, "pci106b,5811")) {
2780 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2781 g5_fw_enable(np, 0, 1);
2782 }
2783 np = of_find_node_by_name(np, "firewire");
2784 }
2785 }
2786#else /* CONFIG_POWER4 */
2787
2788 if (macio_chips[0].type == macio_keylargo ||
2789 macio_chips[0].type == macio_pangea ||
2790 macio_chips[0].type == macio_intrepid) {
2791 /* Enable GMAC for now for PCI probing. It will be disabled
2792 * later on after PCI probe
2793 */
2794 np = of_find_node_by_name(NULL, "ethernet");
2795 while(np) {
2796 if (np->parent
2797 && device_is_compatible(np->parent, "uni-north")
2798 && device_is_compatible(np, "gmac"))
2799 core99_gmac_enable(np, 0, 1);
2800 np = of_find_node_by_name(np, "ethernet");
2801 }
2802
2803 /* Enable FW before PCI probe. Will be disabled later on
2804 * Note: We should have a batter way to check that we are
2805 * dealing with uninorth internal cell and not a PCI cell
2806 * on the external PCI. The code below works though.
2807 */
2808 np = of_find_node_by_name(NULL, "firewire");
2809 while(np) {
2810 if (np->parent
2811 && device_is_compatible(np->parent, "uni-north")
2812 && (device_is_compatible(np, "pci106b,18") ||
2813 device_is_compatible(np, "pci106b,30") ||
2814 device_is_compatible(np, "pci11c1,5811"))) {
2815 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2816 core99_firewire_enable(np, 0, 1);
2817 }
2818 np = of_find_node_by_name(np, "firewire");
2819 }
2820
2821 /* Enable ATA-100 before PCI probe. */
2822 np = of_find_node_by_name(NULL, "ata-6");
2823 while(np) {
2824 if (np->parent
2825 && device_is_compatible(np->parent, "uni-north")
2826 && device_is_compatible(np, "kauai-ata")) {
2827 core99_ata100_enable(np, 1);
2828 }
2829 np = of_find_node_by_name(np, "ata-6");
2830 }
2831
2832 /* Switch airport off */
2833 np = find_devices("radio");
2834 while(np) {
2835 if (np && np->parent == macio_chips[0].of_node) {
2836 macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON;
2837 core99_airport_enable(np, 0, 0);
2838 }
2839 np = np->next;
2840 }
2841 }
2842
2843 /* On all machines that support sound PM, switch sound off */
2844 if (macio_chips[0].of_node)
2845 pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE,
2846 macio_chips[0].of_node, 0, 0);
2847
2848 /* While on some desktop G3s, we turn it back on */
2849 if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow
2850 && (pmac_mb.model_id == PMAC_TYPE_GOSSAMER ||
2851 pmac_mb.model_id == PMAC_TYPE_SILK)) {
2852 struct macio_chip *macio = &macio_chips[0];
2853 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
2854 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
2855 }
2856
14cf11af
PM		 2857#endif /* CONFIG_POWER4 */
2858
2859 /* On all machines, switch modem & serial ports off */
2860 np = find_devices("ch-a");
2861 while(np) {
2862 initial_serial_shutdown(np);
2863 np = np->next;
2864 }
2865 np = find_devices("ch-b");
2866 while(np) {
2867 initial_serial_shutdown(np);
2868 np = np->next;
2869 }
2870}
2871
2872void __init
2873pmac_feature_init(void)
2874{
2875 /* Detect the UniNorth memory controller */
2876 probe_uninorth();
2877
2878 /* Probe mac-io controllers */
2879 if (probe_macios()) {
2880 printk(KERN_WARNING "No mac-io chip found\n");
2881 return;
2882 }
2883
14cf11af
PM		 2884 /* Probe machine type */
2885 if (probe_motherboard())
2886 printk(KERN_WARNING "Unknown PowerMac !\n");
2887
2888 /* Set some initial features (turn off some chips that will
2889 * be later turned on)
2890 */
2891 set_initial_features();
2892}
2893
14cf11af
PM		 2894#if 0
2895static void dump_HT_speeds(char *name, u32 cfg, u32 frq)
2896{
2897 int freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 };
2898 int bits[8] = { 8,16,0,32,2,4,0,0 };
2899 int freq = (frq >> 8) & 0xf;
2900
2901 if (freqs[freq] == 0)
2902 printk("%s: Unknown HT link frequency %x\n", name, freq);
2903 else
2904 printk("%s: %d MHz on main link, (%d in / %d out) bits width\n",
2905 name, freqs[freq],
2906 bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]);
2907}
2908
2909void __init pmac_check_ht_link(void)
2910{
14cf11af
PM		 2911 u32 ufreq, freq, ucfg, cfg;
2912 struct device_node *pcix_node;
2913 u8 px_bus, px_devfn;
2914 struct pci_controller *px_hose;
2915
5b9ca526
BH		 2916 (void)in_be32(u3_ht_base + U3_HT_LINK_COMMAND);
2917 ucfg = cfg = in_be32(u3_ht_base + U3_HT_LINK_CONFIG);
2918 ufreq = freq = in_be32(u3_ht_base + U3_HT_LINK_FREQ);
14cf11af
PM		 2919 dump_HT_speeds("U3 HyperTransport", cfg, freq);
2920
2921 pcix_node = of_find_compatible_node(NULL, "pci", "pci-x");
2922 if (pcix_node == NULL) {
2923 printk("No PCI-X bridge found\n");
2924 return;
2925 }
2926 if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) {
2927 printk("PCI-X bridge found but not matched to pci\n");
2928 return;
2929 }
2930 px_hose = pci_find_hose_for_OF_device(pcix_node);
2931 if (px_hose == NULL) {
2932 printk("PCI-X bridge found but not matched to host\n");
2933 return;
2934 }
2935 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg);
2936 early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq);
2937 dump_HT_speeds("PCI-X HT Uplink", cfg, freq);
2938 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg);
2939 early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq);
2940 dump_HT_speeds("PCI-X HT Downlink", cfg, freq);
14cf11af 2941}
35499c01 2942#endif /* 0 */
14cf11af
PM		 2943
2944/*
2945 * Early video resume hook
2946 */
2947
2948static void (*pmac_early_vresume_proc)(void *data);
2949static void *pmac_early_vresume_data;
2950
2951void pmac_set_early_video_resume(void (*proc)(void *data), void *data)
2952{
e8222502 2953 if (!machine_is(powermac))
14cf11af
PM		 2954 return;
2955 preempt_disable();
2956 pmac_early_vresume_proc = proc;
2957 pmac_early_vresume_data = data;
2958 preempt_enable();
2959}
2960EXPORT_SYMBOL(pmac_set_early_video_resume);
2961
2962void pmac_call_early_video_resume(void)
2963{
2964 if (pmac_early_vresume_proc)
2965 pmac_early_vresume_proc(pmac_early_vresume_data);
2966}
2967
2968/*
2969 * AGP related suspend/resume code
2970 */
2971
2972static struct pci_dev *pmac_agp_bridge;
2973static int (*pmac_agp_suspend)(struct pci_dev *bridge);
2974static int (*pmac_agp_resume)(struct pci_dev *bridge);
2975
2976void pmac_register_agp_pm(struct pci_dev *bridge,
2977 int (*suspend)(struct pci_dev *bridge),
2978 int (*resume)(struct pci_dev *bridge))
2979{
2980 if (suspend || resume) {
2981 pmac_agp_bridge = bridge;
2982 pmac_agp_suspend = suspend;
2983 pmac_agp_resume = resume;
2984 return;
2985 }
2986 if (bridge != pmac_agp_bridge)
2987 return;
2988 pmac_agp_suspend = pmac_agp_resume = NULL;
2989 return;
2990}
2991EXPORT_SYMBOL(pmac_register_agp_pm);
2992
2993void pmac_suspend_agp_for_card(struct pci_dev *dev)
2994{
2995 if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL)
2996 return;
2997 if (pmac_agp_bridge->bus != dev->bus)
2998 return;
2999 pmac_agp_suspend(pmac_agp_bridge);
3000}
3001EXPORT_SYMBOL(pmac_suspend_agp_for_card);
3002
3003void pmac_resume_agp_for_card(struct pci_dev *dev)
3004{
3005 if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL)
3006 return;
3007 if (pmac_agp_bridge->bus != dev->bus)
3008 return;
3009 pmac_agp_resume(pmac_agp_bridge);
3010}
3011EXPORT_SYMBOL(pmac_resume_agp_for_card);
Linux 6.x block layer and io_uring tree(s)