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[PATCH] sem2mutex: fs/
[linux-2.6-block.git] / arch / powerpc / platforms / powermac / cpufreq_64.c
CommitLineData
4350147a
BH		 1/*
2 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
3 * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
10 * that is iMac G5 and latest single CPU desktop.
11 */
12
13#include <linux/config.h>
14#include <linux/module.h>
15#include <linux/types.h>
16#include <linux/errno.h>
17#include <linux/kernel.h>
18#include <linux/delay.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/cpufreq.h>
22#include <linux/init.h>
23#include <linux/completion.h>
24#include <asm/prom.h>
25#include <asm/machdep.h>
26#include <asm/irq.h>
27#include <asm/sections.h>
28#include <asm/cputable.h>
29#include <asm/time.h>
30#include <asm/smu.h>
9a699aef 31#include <asm/pmac_pfunc.h>
4350147a
BH		 32
33#undef DEBUG
34
35#ifdef DEBUG
36#define DBG(fmt...) printk(fmt)
37#else
38#define DBG(fmt...)
39#endif
40
41/* see 970FX user manual */
42
43#define SCOM_PCR 0x0aa001 /* PCR scom addr */
44
45#define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
46#define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
47#define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
48#define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
49#define PCR_SPEED_MASK 0x000e0000U /* speed mask */
50#define PCR_SPEED_SHIFT 17
51#define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
52#define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
53#define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
54#define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
55#define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
56#define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
57
58#define SCOM_PSR 0x408001 /* PSR scom addr */
59/* warning: PSR is a 64 bits register */
60#define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
61#define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
62#define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
63#define PSR_CUR_SPEED_SHIFT (56)
64
65/*
66 * The G5 only supports two frequencies (Quarter speed is not supported)
67 */
68#define CPUFREQ_HIGH 0
69#define CPUFREQ_LOW 1
70
71static struct cpufreq_frequency_table g5_cpu_freqs[] = {
72 {CPUFREQ_HIGH, 0},
73 {CPUFREQ_LOW, 0},
74 {0, CPUFREQ_TABLE_END},
75};
76
77static struct freq_attr* g5_cpu_freqs_attr[] = {
78 &cpufreq_freq_attr_scaling_available_freqs,
79 NULL,
80};
81
82/* Power mode data is an array of the 32 bits PCR values to use for
943ffb58 83 * the various frequencies, retrieved from the device-tree
4350147a
BH		 84 */
85static u32 *g5_pmode_data;
86static int g5_pmode_max;
87static int g5_pmode_cur;
88
9a699aef
BH		 89static void (*g5_switch_volt)(int speed_mode);
90static int (*g5_switch_freq)(int speed_mode);
91static int (*g5_query_freq)(void);
92
4350147a
BH		 93static DECLARE_MUTEX(g5_switch_mutex);
94
95
96static struct smu_sdbp_fvt *g5_fvt_table; /* table of op. points */
97static int g5_fvt_count; /* number of op. points */
98static int g5_fvt_cur; /* current op. point */
99
9a699aef
BH		 100/*
101 * SMU based voltage switching for Neo2 platforms
102 */
4350147a 103
9a699aef 104static void g5_smu_switch_volt(int speed_mode)
4350147a
BH		 105{
106 struct smu_simple_cmd cmd;
107
108 DECLARE_COMPLETION(comp);
109 smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
110 &comp, 'V', 'S', 'L', 'E', 'W',
111 0xff, g5_fvt_cur+1, speed_mode);
112 wait_for_completion(&comp);
113}
114
9a699aef
BH		 115/*
116 * Platform function based voltage/vdnap switching for Neo2
117 */
118
119static struct pmf_function *pfunc_set_vdnap0;
120static struct pmf_function *pfunc_vdnap0_complete;
121
122static void g5_vdnap_switch_volt(int speed_mode)
4350147a 123{
9a699aef
BH		 124 struct pmf_args args;
125 u32 slew, done = 0;
126 unsigned long timeout;
4350147a 127
9a699aef
BH		 128 slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
129 args.count = 1;
130 args.u[0].p = &slew;
4350147a 131
9a699aef 132 pmf_call_one(pfunc_set_vdnap0, &args);
4350147a 133
9a699aef
BH		 134 /* It's an irq GPIO so we should be able to just block here,
135 * I'll do that later after I've properly tested the IRQ code for
136 * platform functions
137 */
138 timeout = jiffies + HZ/10;
139 while(!time_after(jiffies, timeout)) {
140 args.count = 1;
141 args.u[0].p = &done;
142 pmf_call_one(pfunc_vdnap0_complete, &args);
143 if (done)
144 break;
145 msleep(1);
146 }
147 if (done == 0)
148 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
149}
4350147a 150
9a699aef
BH		 151
152/*
153 * SCOM based frequency switching for 970FX rev3
154 */
155static int g5_scom_switch_freq(int speed_mode)
156{
157 unsigned long flags;
158 int to;
4350147a
BH		 159
160 /* If frequency is going up, first ramp up the voltage */
161 if (speed_mode < g5_pmode_cur)
162 g5_switch_volt(speed_mode);
163
9a699aef
BH		 164 local_irq_save(flags);
165
4350147a
BH		 166 /* Clear PCR high */
167 scom970_write(SCOM_PCR, 0);
168 /* Clear PCR low */
169 scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
170 /* Set PCR low */
171 scom970_write(SCOM_PCR, PCR_HILO_SELECT |
172 g5_pmode_data[speed_mode]);
173
174 /* Wait for completion */
175 for (to = 0; to < 10; to++) {
176 unsigned long psr = scom970_read(SCOM_PSR);
177
178 if ((psr & PSR_CMD_RECEIVED) == 0 &&
179 (((psr >> PSR_CUR_SPEED_SHIFT) ^
180 (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
181 == 0)
182 break;
183 if (psr & PSR_CMD_COMPLETED)
184 break;
185 udelay(100);
186 }
187
9a699aef
BH		 188 local_irq_restore(flags);
189
4350147a
BH		 190 /* If frequency is going down, last ramp the voltage */
191 if (speed_mode > g5_pmode_cur)
192 g5_switch_volt(speed_mode);
193
194 g5_pmode_cur = speed_mode;
195 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
196
4350147a
BH		 197 return 0;
198}
199
9a699aef 200static int g5_scom_query_freq(void)
4350147a
BH		 201{
202 unsigned long psr = scom970_read(SCOM_PSR);
203 int i;
204
205 for (i = 0; i <= g5_pmode_max; i++)
206 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
207 (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
208 break;
209 return i;
210}
211
9a699aef
BH		 212/*
213 * Platform function based voltage switching for PowerMac7,2 & 7,3
214 */
215
216static struct pmf_function *pfunc_cpu0_volt_high;
217static struct pmf_function *pfunc_cpu0_volt_low;
218static struct pmf_function *pfunc_cpu1_volt_high;
219static struct pmf_function *pfunc_cpu1_volt_low;
220
221static void g5_pfunc_switch_volt(int speed_mode)
222{
223 if (speed_mode == CPUFREQ_HIGH) {
224 if (pfunc_cpu0_volt_high)
225 pmf_call_one(pfunc_cpu0_volt_high, NULL);
226 if (pfunc_cpu1_volt_high)
227 pmf_call_one(pfunc_cpu1_volt_high, NULL);
228 } else {
229 if (pfunc_cpu0_volt_low)
230 pmf_call_one(pfunc_cpu0_volt_low, NULL);
231 if (pfunc_cpu1_volt_low)
232 pmf_call_one(pfunc_cpu1_volt_low, NULL);
233 }
234 msleep(10); /* should be faster , to fix */
235}
236
237/*
238 * Platform function based frequency switching for PowerMac7,2 & 7,3
239 */
240
241static struct pmf_function *pfunc_cpu_setfreq_high;
242static struct pmf_function *pfunc_cpu_setfreq_low;
243static struct pmf_function *pfunc_cpu_getfreq;
244static struct pmf_function *pfunc_slewing_done;;
245
246static int g5_pfunc_switch_freq(int speed_mode)
247{
248 struct pmf_args args;
249 u32 done = 0;
250 unsigned long timeout;
251
252 /* If frequency is going up, first ramp up the voltage */
253 if (speed_mode < g5_pmode_cur)
254 g5_switch_volt(speed_mode);
255
256 /* Do it */
257 if (speed_mode == CPUFREQ_HIGH)
258 pmf_call_one(pfunc_cpu_setfreq_high, NULL);
259 else
260 pmf_call_one(pfunc_cpu_setfreq_low, NULL);
261
262 /* It's an irq GPIO so we should be able to just block here,
263 * I'll do that later after I've properly tested the IRQ code for
264 * platform functions
265 */
266 timeout = jiffies + HZ/10;
267 while(!time_after(jiffies, timeout)) {
268 args.count = 1;
269 args.u[0].p = &done;
270 pmf_call_one(pfunc_slewing_done, &args);
271 if (done)
272 break;
273 msleep(1);
274 }
275 if (done == 0)
276 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
277
278 /* If frequency is going down, last ramp the voltage */
279 if (speed_mode > g5_pmode_cur)
280 g5_switch_volt(speed_mode);
281
282 g5_pmode_cur = speed_mode;
283 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
284
285 return 0;
286}
287
288static int g5_pfunc_query_freq(void)
289{
290 struct pmf_args args;
291 u32 val = 0;
292
293 args.count = 1;
294 args.u[0].p = &val;
295 pmf_call_one(pfunc_cpu_getfreq, &args);
296 return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
297}
298
299/*
300 * Fake voltage switching for platforms with missing support
301 */
302
303static void g5_dummy_switch_volt(int speed_mode)
304{
305}
306
307/*
308 * Common interface to the cpufreq core
309 */
4350147a
BH		 310
311static int g5_cpufreq_verify(struct cpufreq_policy *policy)
312{
313 return cpufreq_frequency_table_verify(policy, g5_cpu_freqs);
314}
315
316static int g5_cpufreq_target(struct cpufreq_policy *policy,
317 unsigned int target_freq, unsigned int relation)
318{
9a699aef
BH		 319 unsigned int newstate = 0;
320 struct cpufreq_freqs freqs;
321 int rc;
4350147a
BH		 322
323 if (cpufreq_frequency_table_target(policy, g5_cpu_freqs,
324 target_freq, relation, &newstate))
325 return -EINVAL;
326
9a699aef
BH		 327 if (g5_pmode_cur == newstate)
328 return 0;
329
330 down(&g5_switch_mutex);
331
332 freqs.old = g5_cpu_freqs[g5_pmode_cur].frequency;
333 freqs.new = g5_cpu_freqs[newstate].frequency;
334 freqs.cpu = 0;
335
336 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
337 rc = g5_switch_freq(newstate);
338 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
339
340 up(&g5_switch_mutex);
341
342 return rc;
4350147a
BH		 343}
344
345static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
346{
347 return g5_cpu_freqs[g5_pmode_cur].frequency;
348}
349
350static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
351{
352 if (policy->cpu != 0)
353 return -ENODEV;
354
355 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
356 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
357 policy->cur = g5_cpu_freqs[g5_query_freq()].frequency;
9a699aef 358 policy->cpus = cpu_possible_map;
4350147a
BH		 359 cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu);
360
361 return cpufreq_frequency_table_cpuinfo(policy,
362 g5_cpu_freqs);
363}
364
365
366static struct cpufreq_driver g5_cpufreq_driver = {
367 .name = "powermac",
368 .owner = THIS_MODULE,
369 .flags = CPUFREQ_CONST_LOOPS,
370 .init = g5_cpufreq_cpu_init,
371 .verify = g5_cpufreq_verify,
372 .target = g5_cpufreq_target,
373 .get = g5_cpufreq_get_speed,
374 .attr = g5_cpu_freqs_attr,
375};
376
377
9a699aef 378static int __init g5_neo2_cpufreq_init(struct device_node *cpus)
4350147a
BH		 379{
380 struct device_node *cpunode;
381 unsigned int psize, ssize;
4350147a 382 unsigned long max_freq;
9a699aef
BH		 383 char *freq_method, *volt_method;
384 u32 *valp, pvr_hi;
385 int use_volts_vdnap = 0;
386 int use_volts_smu = 0;
4350147a
BH		 387 int rc = -ENODEV;
388
9a699aef
BH		 389 /* Check supported platforms */
390 if (machine_is_compatible("PowerMac8,1") ||
391 machine_is_compatible("PowerMac8,2") ||
392 machine_is_compatible("PowerMac9,1"))
393 use_volts_smu = 1;
394 else if (machine_is_compatible("PowerMac11,2"))
395 use_volts_vdnap = 1;
396 else
397 return -ENODEV;
398
399 /* Get first CPU node */
400 for (cpunode = NULL;
401 (cpunode = of_get_next_child(cpus, cpunode)) != NULL;) {
402 u32 *reg =
403 (u32 *)get_property(cpunode, "reg", NULL);
404 if (reg == NULL || (*reg) != 0)
405 continue;
406 if (!strcmp(cpunode->type, "cpu"))
407 break;
408 }
409 if (cpunode == NULL) {
410 printk(KERN_ERR "cpufreq: Can't find any CPU 0 node\n");
4350147a
BH		 411 return -ENODEV;
412 }
413
414 /* Check 970FX for now */
415 valp = (u32 *)get_property(cpunode, "cpu-version", NULL);
416 if (!valp) {
417 DBG("No cpu-version property !\n");
418 goto bail_noprops;
419 }
9a699aef
BH		 420 pvr_hi = (*valp) >> 16;
421 if (pvr_hi != 0x3c && pvr_hi != 0x44) {
422 printk(KERN_ERR "cpufreq: Unsupported CPU version\n");
4350147a
BH		 423 goto bail_noprops;
424 }
425
426 /* Look for the powertune data in the device-tree */
427 g5_pmode_data = (u32 *)get_property(cpunode, "power-mode-data",&psize);
428 if (!g5_pmode_data) {
429 DBG("No power-mode-data !\n");
430 goto bail_noprops;
431 }
432 g5_pmode_max = psize / sizeof(u32) - 1;
433
9a699aef
BH		 434 if (use_volts_smu) {
435 struct smu_sdbp_header *shdr;
436
437 /* Look for the FVT table */
438 shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
439 if (!shdr)
440 goto bail_noprops;
441 g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
442 ssize = (shdr->len * sizeof(u32)) -
443 sizeof(struct smu_sdbp_header);
444 g5_fvt_count = ssize / sizeof(struct smu_sdbp_fvt);
445 g5_fvt_cur = 0;
446
447 /* Sanity checking */
448 if (g5_fvt_count < 1 || g5_pmode_max < 1)
449 goto bail_noprops;
450
451 g5_switch_volt = g5_smu_switch_volt;
452 volt_method = "SMU";
453 } else if (use_volts_vdnap) {
454 struct device_node *root;
455
456 root = of_find_node_by_path("/");
457 if (root == NULL) {
458 printk(KERN_ERR "cpufreq: Can't find root of "
459 "device tree\n");
460 goto bail_noprops;
461 }
462 pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
463 pfunc_vdnap0_complete =
464 pmf_find_function(root, "slewing-done");
465 if (pfunc_set_vdnap0 == NULL ||
466 pfunc_vdnap0_complete == NULL) {
467 printk(KERN_ERR "cpufreq: Can't find required "
468 "platform function\n");
469 goto bail_noprops;
470 }
471
472 g5_switch_volt = g5_vdnap_switch_volt;
473 volt_method = "GPIO";
474 } else {
475 g5_switch_volt = g5_dummy_switch_volt;
476 volt_method = "none";
477 }
4350147a
BH		 478
479 /*
480 * From what I see, clock-frequency is always the maximal frequency.
481 * The current driver can not slew sysclk yet, so we really only deal
482 * with powertune steps for now. We also only implement full freq and
483 * half freq in this version. So far, I haven't yet seen a machine
484 * supporting anything else.
485 */
486 valp = (u32 *)get_property(cpunode, "clock-frequency", NULL);
487 if (!valp)
488 return -ENODEV;
489 max_freq = (*valp)/1000;
490 g5_cpu_freqs[0].frequency = max_freq;
491 g5_cpu_freqs[1].frequency = max_freq/2;
492
9a699aef
BH		 493 /* Set callbacks */
494 g5_switch_freq = g5_scom_switch_freq;
495 g5_query_freq = g5_scom_query_freq;
496 freq_method = "SCOM";
4350147a
BH		 497
498 /* Force apply current frequency to make sure everything is in
499 * sync (voltage is right for example). Firmware may leave us with
500 * a strange setting ...
501 */
9a699aef
BH		 502 g5_switch_volt(CPUFREQ_HIGH);
503 msleep(10);
504 g5_pmode_cur = -1;
505 g5_switch_freq(g5_query_freq());
4350147a
BH		 506
507 printk(KERN_INFO "Registering G5 CPU frequency driver\n");
9a699aef
BH		 508 printk(KERN_INFO "Frequency method: %s, Voltage method: %s\n",
509 freq_method, volt_method);
4350147a
BH		 510 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
511 g5_cpu_freqs[1].frequency/1000,
512 g5_cpu_freqs[0].frequency/1000,
513 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
514
515 rc = cpufreq_register_driver(&g5_cpufreq_driver);
516
517 /* We keep the CPU node on hold... hopefully, Apple G5 don't have
518 * hotplug CPU with a dynamic device-tree ...
519 */
520 return rc;
521
522 bail_noprops:
523 of_node_put(cpunode);
524
525 return rc;
526}
527
9a699aef
BH		 528static int __init g5_pm72_cpufreq_init(struct device_node *cpus)
529{
530 struct device_node *cpuid = NULL, *hwclock = NULL, *cpunode = NULL;
531 u8 *eeprom = NULL;
532 u32 *valp;
533 u64 max_freq, min_freq, ih, il;
534 int has_volt = 1, rc = 0;
535
536 /* Get first CPU node */
537 for (cpunode = NULL;
538 (cpunode = of_get_next_child(cpus, cpunode)) != NULL;) {
539 if (!strcmp(cpunode->type, "cpu"))
540 break;
541 }
542 if (cpunode == NULL) {
543 printk(KERN_ERR "cpufreq: Can't find any CPU node\n");
544 return -ENODEV;
545 }
546
547 /* Lookup the cpuid eeprom node */
548 cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
549 if (cpuid != NULL)
550 eeprom = (u8 *)get_property(cpuid, "cpuid", NULL);
551 if (eeprom == NULL) {
552 printk(KERN_ERR "cpufreq: Can't find cpuid EEPROM !\n");
553 rc = -ENODEV;
554 goto bail;
555 }
556
557 /* Lookup the i2c hwclock */
558 for (hwclock = NULL;
559 (hwclock = of_find_node_by_name(hwclock, "i2c-hwclock")) != NULL;){
560 char *loc = get_property(hwclock, "hwctrl-location", NULL);
561 if (loc == NULL)
562 continue;
563 if (strcmp(loc, "CPU CLOCK"))
564 continue;
565 if (!get_property(hwclock, "platform-get-frequency", NULL))
566 continue;
567 break;
568 }
569 if (hwclock == NULL) {
570 printk(KERN_ERR "cpufreq: Can't find i2c clock chip !\n");
571 rc = -ENODEV;
572 goto bail;
573 }
574
575 DBG("cpufreq: i2c clock chip found: %s\n", hwclock->full_name);
576
577 /* Now get all the platform functions */
578 pfunc_cpu_getfreq =
579 pmf_find_function(hwclock, "get-frequency");
580 pfunc_cpu_setfreq_high =
581 pmf_find_function(hwclock, "set-frequency-high");
582 pfunc_cpu_setfreq_low =
583 pmf_find_function(hwclock, "set-frequency-low");
584 pfunc_slewing_done =
585 pmf_find_function(hwclock, "slewing-done");
586 pfunc_cpu0_volt_high =
587 pmf_find_function(hwclock, "set-voltage-high-0");
588 pfunc_cpu0_volt_low =
589 pmf_find_function(hwclock, "set-voltage-low-0");
590 pfunc_cpu1_volt_high =
591 pmf_find_function(hwclock, "set-voltage-high-1");
592 pfunc_cpu1_volt_low =
593 pmf_find_function(hwclock, "set-voltage-low-1");
594
595 /* Check we have minimum requirements */
596 if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
597 pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
598 printk(KERN_ERR "cpufreq: Can't find platform functions !\n");
599 rc = -ENODEV;
600 goto bail;
601 }
602
603 /* Check that we have complete sets */
604 if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
605 pmf_put_function(pfunc_cpu0_volt_high);
606 pmf_put_function(pfunc_cpu0_volt_low);
607 pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
608 has_volt = 0;
609 }
610 if (!has_volt ||
611 pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
612 pmf_put_function(pfunc_cpu1_volt_high);
613 pmf_put_function(pfunc_cpu1_volt_low);
614 pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
615 }
616
617 /* Note: The device tree also contains a "platform-set-values"
618 * function for which I haven't quite figured out the usage. It
619 * might have to be called on init and/or wakeup, I'm not too sure
620 * but things seem to work fine without it so far ...
621 */
622
623 /* Get max frequency from device-tree */
624 valp = (u32 *)get_property(cpunode, "clock-frequency", NULL);
625 if (!valp) {
626 printk(KERN_ERR "cpufreq: Can't find CPU frequency !\n");
627 rc = -ENODEV;
628 goto bail;
629 }
630
631 max_freq = (*valp)/1000;
632
633 /* Now calculate reduced frequency by using the cpuid input freq
634 * ratio. This requires 64 bits math unless we are willing to lose
635 * some precision
636 */
637 ih = *((u32 *)(eeprom + 0x10));
638 il = *((u32 *)(eeprom + 0x20));
639 min_freq = 0;
640 if (ih != 0 && il != 0)
641 min_freq = (max_freq * il) / ih;
642
643 /* Sanity check */
644 if (min_freq >= max_freq || min_freq < 1000) {
645 printk(KERN_ERR "cpufreq: Can't calculate low frequency !\n");
646 rc = -ENODEV;
647 goto bail;
648 }
649 g5_cpu_freqs[0].frequency = max_freq;
650 g5_cpu_freqs[1].frequency = min_freq;
651
652 /* Set callbacks */
653 g5_switch_volt = g5_pfunc_switch_volt;
654 g5_switch_freq = g5_pfunc_switch_freq;
655 g5_query_freq = g5_pfunc_query_freq;
656
657 /* Force apply current frequency to make sure everything is in
658 * sync (voltage is right for example). Firmware may leave us with
659 * a strange setting ...
660 */
661 g5_switch_volt(CPUFREQ_HIGH);
662 msleep(10);
663 g5_pmode_cur = -1;
664 g5_switch_freq(g5_query_freq());
665
666 printk(KERN_INFO "Registering G5 CPU frequency driver\n");
667 printk(KERN_INFO "Frequency method: i2c/pfunc, "
668 "Voltage method: %s\n", has_volt ? "i2c/pfunc" : "none");
669 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
670 g5_cpu_freqs[1].frequency/1000,
671 g5_cpu_freqs[0].frequency/1000,
672 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
673
674 rc = cpufreq_register_driver(&g5_cpufreq_driver);
675 bail:
676 if (rc != 0) {
677 pmf_put_function(pfunc_cpu_getfreq);
678 pmf_put_function(pfunc_cpu_setfreq_high);
679 pmf_put_function(pfunc_cpu_setfreq_low);
680 pmf_put_function(pfunc_slewing_done);
681 pmf_put_function(pfunc_cpu0_volt_high);
682 pmf_put_function(pfunc_cpu0_volt_low);
683 pmf_put_function(pfunc_cpu1_volt_high);
684 pmf_put_function(pfunc_cpu1_volt_low);
685 }
686 of_node_put(hwclock);
687 of_node_put(cpuid);
688 of_node_put(cpunode);
689
690 return rc;
691}
692
693static int __init g5_rm31_cpufreq_init(struct device_node *cpus)
694{
695 /* NYI */
696 return 0;
697}
698
699static int __init g5_cpufreq_init(void)
700{
701 struct device_node *cpus;
702 int rc;
703
704 cpus = of_find_node_by_path("/cpus");
705 if (cpus == NULL) {
706 DBG("No /cpus node !\n");
707 return -ENODEV;
708 }
709
710 if (machine_is_compatible("PowerMac7,2") ||
711 machine_is_compatible("PowerMac7,3"))
712 rc = g5_pm72_cpufreq_init(cpus);
713 else if (machine_is_compatible("RackMac3,1"))
714 rc = g5_rm31_cpufreq_init(cpus);
715 else
716 rc = g5_neo2_cpufreq_init(cpus);
717
718 of_node_put(cpus);
719 return rc;
720}
721
4350147a
BH		 722module_init(g5_cpufreq_init);
723
724
725MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)