[linux-2.6-block.git] / arch / powerpc / platforms / 82xx / pq2ads-pci-pic.c

/*
 * PQ2 ADS-style PCI interrupt controller
 *
 * Copyright 2007 Freescale Semiconductor, Inc.
 * Author: Scott Wood <scottwood@freescale.com>
 *
 * Loosely based on mpc82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
 * Copyright (c) 2006 MontaVista Software, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/bootmem.h>
#include <linux/slab.h>

#include <asm/io.h>
#include <asm/prom.h>
#include <asm/cpm2.h>

#include "pq2.h"

static DEFINE_RAW_SPINLOCK(pci_pic_lock);

struct pq2ads_pci_pic {
	struct device_node *node;
	struct irq_host *host;

	struct {
		u32 stat;
		u32 mask;
	} __iomem *regs;
};

#define NUM_IRQS 32

static void pq2ads_pci_mask_irq(unsigned int virq)
{
	struct pq2ads_pci_pic *priv = get_irq_chip_data(virq);
	int irq = NUM_IRQS - virq_to_hw(virq) - 1;

	if (irq != -1) {
		unsigned long flags;
		raw_spin_lock_irqsave(&pci_pic_lock, flags);

		setbits32(&priv->regs->mask, 1 << irq);
		mb();

		raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
	}
}

static void pq2ads_pci_unmask_irq(unsigned int virq)
{
	struct pq2ads_pci_pic *priv = get_irq_chip_data(virq);
	int irq = NUM_IRQS - virq_to_hw(virq) - 1;

	if (irq != -1) {
		unsigned long flags;

		raw_spin_lock_irqsave(&pci_pic_lock, flags);
		clrbits32(&priv->regs->mask, 1 << irq);
		raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
	}
}

static struct irq_chip pq2ads_pci_ic = {
	.name = "PQ2 ADS PCI",
	.end = pq2ads_pci_unmask_irq,
	.mask = pq2ads_pci_mask_irq,
	.mask_ack = pq2ads_pci_mask_irq,
	.ack = pq2ads_pci_mask_irq,
	.unmask = pq2ads_pci_unmask_irq,
	.enable = pq2ads_pci_unmask_irq,
	.disable = pq2ads_pci_mask_irq
};

static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
{
	struct pq2ads_pci_pic *priv = desc->handler_data;
	u32 stat, mask, pend;
	int bit;

	for (;;) {
		stat = in_be32(&priv->regs->stat);
		mask = in_be32(&priv->regs->mask);

		pend = stat & ~mask;

		if (!pend)
			break;

		for (bit = 0; pend != 0; ++bit, pend <<= 1) {
			if (pend & 0x80000000) {
				int virq = irq_linear_revmap(priv->host, bit);
				generic_handle_irq(virq);
			}
		}
	}
}

static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
			    irq_hw_number_t hw)
{
	irq_to_desc(virq)->status |= IRQ_LEVEL;
	set_irq_chip_data(virq, h->host_data);
	set_irq_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
	return 0;
}

static void pci_host_unmap(struct irq_host *h, unsigned int virq)
{
	/* remove chip and handler */
	set_irq_chip_data(virq, NULL);
	set_irq_chip(virq, NULL);
}

static struct irq_host_ops pci_pic_host_ops = {
	.map = pci_pic_host_map,
	.unmap = pci_host_unmap,
};

int __init pq2ads_pci_init_irq(void)
{
	struct pq2ads_pci_pic *priv;
	struct irq_host *host;
	struct device_node *np;
	int ret = -ENODEV;
	int irq;

	np = of_find_compatible_node(NULL, NULL, "fsl,pq2ads-pci-pic");
	if (!np) {
		printk(KERN_ERR "No pci pic node in device tree.\n");
		of_node_put(np);
		goto out;
	}

	irq = irq_of_parse_and_map(np, 0);
	if (irq == NO_IRQ) {
		printk(KERN_ERR "No interrupt in pci pic node.\n");
		of_node_put(np);
		goto out;
	}

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		of_node_put(np);
		ret = -ENOMEM;
		goto out_unmap_irq;
	}

	/* PCI interrupt controller registers: status and mask */
	priv->regs = of_iomap(np, 0);
	if (!priv->regs) {
		printk(KERN_ERR "Cannot map PCI PIC registers.\n");
		goto out_free_bootmem;
	}

	/* mask all PCI interrupts */
	out_be32(&priv->regs->mask, ~0);
	mb();

	host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, NUM_IRQS,
	                      &pci_pic_host_ops, NUM_IRQS);
	if (!host) {
		ret = -ENOMEM;
		goto out_unmap_regs;
	}

	host->host_data = priv;

	priv->host = host;
	host->host_data = priv;
	set_irq_data(irq, priv);
	set_irq_chained_handler(irq, pq2ads_pci_irq_demux);

	of_node_put(np);
	return 0;

out_unmap_regs:
	iounmap(priv->regs);
out_free_bootmem:
	free_bootmem((unsigned long)priv,
	             sizeof(struct pq2ads_pci_pic));
	of_node_put(np);
out_unmap_irq:
	irq_dispose_mapping(irq);
out:
	return ret;
}
Commit	Line	Data
e00c5498 SW	1	/*
	2	* PQ2 ADS-style PCI interrupt controller
	3	*
	4	* Copyright 2007 Freescale Semiconductor, Inc.
	5	* Author: Scott Wood <scottwood@freescale.com>
	6	*
	7	* Loosely based on mpc82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
	8	* Copyright (c) 2006 MontaVista Software, Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published
	12	* by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/spinlock.h>
	17	#include <linux/irq.h>
	18	#include <linux/types.h>
	19	#include <linux/bootmem.h>
5a0e3ad6	20	#include <linux/slab.h>
e00c5498 SW	21
	22	#include <asm/io.h>
	23	#include <asm/prom.h>
	24	#include <asm/cpm2.h>
	25
	26	#include "pq2.h"
	27
0e5d359c	28	static DEFINE_RAW_SPINLOCK(pci_pic_lock);
e00c5498 SW	29
	30	struct pq2ads_pci_pic {
	31	struct device_node *node;
	32	struct irq_host *host;
	33
	34	struct {
	35	u32 stat;
	36	u32 mask;
	37	} __iomem *regs;
	38	};
	39
	40	#define NUM_IRQS 32
	41
	42	static void pq2ads_pci_mask_irq(unsigned int virq)
	43	{
	44	struct pq2ads_pci_pic *priv = get_irq_chip_data(virq);
	45	int irq = NUM_IRQS - virq_to_hw(virq) - 1;
	46
	47	if (irq != -1) {
	48	unsigned long flags;
0e5d359c	49	raw_spin_lock_irqsave(&pci_pic_lock, flags);
e00c5498 SW	50
	51	setbits32(&priv->regs->mask, 1 << irq);
	52	mb();
	53
0e5d359c	54	raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
e00c5498 SW	55	}
	56	}
	57
	58	static void pq2ads_pci_unmask_irq(unsigned int virq)
	59	{
	60	struct pq2ads_pci_pic *priv = get_irq_chip_data(virq);
	61	int irq = NUM_IRQS - virq_to_hw(virq) - 1;
	62
	63	if (irq != -1) {
	64	unsigned long flags;
	65
0e5d359c	66	raw_spin_lock_irqsave(&pci_pic_lock, flags);
e00c5498	67	clrbits32(&priv->regs->mask, 1 << irq);
0e5d359c	68	raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
e00c5498 SW	69	}
	70	}
	71
	72	static struct irq_chip pq2ads_pci_ic = {
e00c5498 SW	73	.name = "PQ2 ADS PCI",
	74	.end = pq2ads_pci_unmask_irq,
	75	.mask = pq2ads_pci_mask_irq,
	76	.mask_ack = pq2ads_pci_mask_irq,
	77	.ack = pq2ads_pci_mask_irq,
	78	.unmask = pq2ads_pci_unmask_irq,
	79	.enable = pq2ads_pci_unmask_irq,
	80	.disable = pq2ads_pci_mask_irq
	81	};
	82
	83	static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
	84	{
	85	struct pq2ads_pci_pic *priv = desc->handler_data;
	86	u32 stat, mask, pend;
	87	int bit;
	88
	89	for (;;) {
	90	stat = in_be32(&priv->regs->stat);
	91	mask = in_be32(&priv->regs->mask);
	92
	93	pend = stat & ~mask;
	94
	95	if (!pend)
	96	break;
	97
	98	for (bit = 0; pend != 0; ++bit, pend <<= 1) {
	99	if (pend & 0x80000000) {
	100	int virq = irq_linear_revmap(priv->host, bit);
	101	generic_handle_irq(virq);
	102	}
	103	}
	104	}
	105	}
	106
	107	static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
	108	irq_hw_number_t hw)
	109	{
6cff46f4	110	irq_to_desc(virq)->status \|= IRQ_LEVEL;
e00c5498	111	set_irq_chip_data(virq, h->host_data);
6c116099	112	set_irq_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
e00c5498 SW	113	return 0;
	114	}
	115
	116	static void pci_host_unmap(struct irq_host *h, unsigned int virq)
	117	{
	118	/* remove chip and handler */
	119	set_irq_chip_data(virq, NULL);
	120	set_irq_chip(virq, NULL);
	121	}
	122
	123	static struct irq_host_ops pci_pic_host_ops = {
	124	.map = pci_pic_host_map,
	125	.unmap = pci_host_unmap,
	126	};
	127
	128	int __init pq2ads_pci_init_irq(void)
	129	{
	130	struct pq2ads_pci_pic *priv;
	131	struct irq_host *host;
	132	struct device_node *np;
	133	int ret = -ENODEV;
	134	int irq;
	135
	136	np = of_find_compatible_node(NULL, NULL, "fsl,pq2ads-pci-pic");
	137	if (!np) {
	138	printk(KERN_ERR "No pci pic node in device tree.\n");
	139	of_node_put(np);
	140	goto out;
	141	}
	142
	143	irq = irq_of_parse_and_map(np, 0);
	144	if (irq == NO_IRQ) {
	145	printk(KERN_ERR "No interrupt in pci pic node.\n");
	146	of_node_put(np);
	147	goto out;
	148	}
	149
ea96025a	150	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
e00c5498 SW	151	if (!priv) {
	152	of_node_put(np);
	153	ret = -ENOMEM;
	154	goto out_unmap_irq;
	155	}
	156
	157	/* PCI interrupt controller registers: status and mask */
	158	priv->regs = of_iomap(np, 0);
	159	if (!priv->regs) {
	160	printk(KERN_ERR "Cannot map PCI PIC registers.\n");
	161	goto out_free_bootmem;
	162	}
	163
	164	/* mask all PCI interrupts */
	165	out_be32(&priv->regs->mask, ~0);
	166	mb();
	167
	168	host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, NUM_IRQS,
	169	&pci_pic_host_ops, NUM_IRQS);
	170	if (!host) {
	171	ret = -ENOMEM;
	172	goto out_unmap_regs;
	173	}
	174
	175	host->host_data = priv;
	176
	177	priv->host = host;
	178	host->host_data = priv;
	179	set_irq_data(irq, priv);
	180	set_irq_chained_handler(irq, pq2ads_pci_irq_demux);
	181
	182	of_node_put(np);
	183	return 0;
	184
	185	out_unmap_regs:
	186	iounmap(priv->regs);
	187	out_free_bootmem:
	188	free_bootmem((unsigned long)priv,
08c6e3a5	189	sizeof(struct pq2ads_pci_pic));
e00c5498 SW	190	of_node_put(np);
	191	out_unmap_irq:
	192	irq_dispose_mapping(irq);
	193	out:
	194	return ret;
	195	}