Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 | 23 | |
7f142661 | 24 | #define pr_fmt(fmt) "hash-mmu: " fmt |
1da177e4 LT |
25 | #include <linux/spinlock.h> |
26 | #include <linux/errno.h> | |
589ee628 | 27 | #include <linux/sched/mm.h> |
1da177e4 LT |
28 | #include <linux/proc_fs.h> |
29 | #include <linux/stat.h> | |
30 | #include <linux/sysctl.h> | |
66b15db6 | 31 | #include <linux/export.h> |
1da177e4 LT |
32 | #include <linux/ctype.h> |
33 | #include <linux/cache.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/signal.h> | |
95f72d1e | 36 | #include <linux/memblock.h> |
ba12eede | 37 | #include <linux/context_tracking.h> |
5556ecf5 | 38 | #include <linux/libfdt.h> |
92e3da3c | 39 | #include <linux/pkeys.h> |
1da177e4 | 40 | |
7644d581 | 41 | #include <asm/debugfs.h> |
1da177e4 LT |
42 | #include <asm/processor.h> |
43 | #include <asm/pgtable.h> | |
44 | #include <asm/mmu.h> | |
45 | #include <asm/mmu_context.h> | |
46 | #include <asm/page.h> | |
47 | #include <asm/types.h> | |
7c0f6ba6 | 48 | #include <linux/uaccess.h> |
1da177e4 | 49 | #include <asm/machdep.h> |
d9b2b2a2 | 50 | #include <asm/prom.h> |
1da177e4 LT |
51 | #include <asm/io.h> |
52 | #include <asm/eeh.h> | |
53 | #include <asm/tlb.h> | |
54 | #include <asm/cacheflush.h> | |
55 | #include <asm/cputable.h> | |
1da177e4 | 56 | #include <asm/sections.h> |
be3ebfe8 | 57 | #include <asm/copro.h> |
aa39be09 | 58 | #include <asm/udbg.h> |
b68a70c4 | 59 | #include <asm/code-patching.h> |
3ccc00a7 | 60 | #include <asm/fadump.h> |
f5339277 | 61 | #include <asm/firmware.h> |
bc2a9408 | 62 | #include <asm/tm.h> |
cfcb3d80 | 63 | #include <asm/trace.h> |
166dd7d3 | 64 | #include <asm/ps3.h> |
94171b19 | 65 | #include <asm/pte-walk.h> |
eacbb218 | 66 | #include <asm/asm-prototypes.h> |
1da177e4 LT |
67 | |
68 | #ifdef DEBUG | |
69 | #define DBG(fmt...) udbg_printf(fmt) | |
70 | #else | |
71 | #define DBG(fmt...) | |
72 | #endif | |
73 | ||
3c726f8d BH |
74 | #ifdef DEBUG_LOW |
75 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
76 | #else | |
77 | #define DBG_LOW(fmt...) | |
78 | #endif | |
79 | ||
80 | #define KB (1024) | |
81 | #define MB (1024*KB) | |
658013e9 | 82 | #define GB (1024L*MB) |
3c726f8d | 83 | |
1da177e4 LT |
84 | /* |
85 | * Note: pte --> Linux PTE | |
86 | * HPTE --> PowerPC Hashed Page Table Entry | |
87 | * | |
88 | * Execution context: | |
89 | * htab_initialize is called with the MMU off (of course), but | |
90 | * the kernel has been copied down to zero so it can directly | |
91 | * reference global data. At this point it is very difficult | |
92 | * to print debug info. | |
93 | * | |
94 | */ | |
95 | ||
799d6046 PM |
96 | static unsigned long _SDR1; |
97 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
e1802b06 | 98 | EXPORT_SYMBOL_GPL(mmu_psize_defs); |
799d6046 | 99 | |
0eeede0c PM |
100 | u8 hpte_page_sizes[1 << LP_BITS]; |
101 | EXPORT_SYMBOL_GPL(hpte_page_sizes); | |
102 | ||
8e561e7e | 103 | struct hash_pte *htab_address; |
337a7128 | 104 | unsigned long htab_size_bytes; |
96e28449 | 105 | unsigned long htab_hash_mask; |
4ab79aa8 | 106 | EXPORT_SYMBOL_GPL(htab_hash_mask); |
3c726f8d | 107 | int mmu_linear_psize = MMU_PAGE_4K; |
8ca7a82f | 108 | EXPORT_SYMBOL_GPL(mmu_linear_psize); |
3c726f8d | 109 | int mmu_virtual_psize = MMU_PAGE_4K; |
bf72aeba | 110 | int mmu_vmalloc_psize = MMU_PAGE_4K; |
cec08e7a BH |
111 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
112 | int mmu_vmemmap_psize = MMU_PAGE_4K; | |
113 | #endif | |
bf72aeba | 114 | int mmu_io_psize = MMU_PAGE_4K; |
1189be65 | 115 | int mmu_kernel_ssize = MMU_SEGSIZE_256M; |
8ca7a82f | 116 | EXPORT_SYMBOL_GPL(mmu_kernel_ssize); |
1189be65 | 117 | int mmu_highuser_ssize = MMU_SEGSIZE_256M; |
584f8b71 | 118 | u16 mmu_slb_size = 64; |
4ab79aa8 | 119 | EXPORT_SYMBOL_GPL(mmu_slb_size); |
bf72aeba PM |
120 | #ifdef CONFIG_PPC_64K_PAGES |
121 | int mmu_ci_restrictions; | |
122 | #endif | |
370a908d BH |
123 | #ifdef CONFIG_DEBUG_PAGEALLOC |
124 | static u8 *linear_map_hash_slots; | |
125 | static unsigned long linear_map_hash_count; | |
ed166692 | 126 | static DEFINE_SPINLOCK(linear_map_hash_lock); |
370a908d | 127 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
7025776e BH |
128 | struct mmu_hash_ops mmu_hash_ops; |
129 | EXPORT_SYMBOL(mmu_hash_ops); | |
1da177e4 | 130 | |
3c726f8d BH |
131 | /* There are definitions of page sizes arrays to be used when none |
132 | * is provided by the firmware. | |
133 | */ | |
1da177e4 | 134 | |
471d7ff8 NP |
135 | /* |
136 | * Fallback (4k pages only) | |
3c726f8d | 137 | */ |
471d7ff8 | 138 | static struct mmu_psize_def mmu_psize_defaults[] = { |
3c726f8d BH |
139 | [MMU_PAGE_4K] = { |
140 | .shift = 12, | |
141 | .sllp = 0, | |
b1022fbd | 142 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
143 | .avpnm = 0, |
144 | .tlbiel = 0, | |
145 | }, | |
146 | }; | |
147 | ||
148 | /* POWER4, GPUL, POWER5 | |
149 | * | |
150 | * Support for 16Mb large pages | |
151 | */ | |
09de9ff8 | 152 | static struct mmu_psize_def mmu_psize_defaults_gp[] = { |
3c726f8d BH |
153 | [MMU_PAGE_4K] = { |
154 | .shift = 12, | |
155 | .sllp = 0, | |
b1022fbd | 156 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
157 | .avpnm = 0, |
158 | .tlbiel = 1, | |
159 | }, | |
160 | [MMU_PAGE_16M] = { | |
161 | .shift = 24, | |
162 | .sllp = SLB_VSID_L, | |
b1022fbd AK |
163 | .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0, |
164 | [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 }, | |
3c726f8d BH |
165 | .avpnm = 0x1UL, |
166 | .tlbiel = 0, | |
167 | }, | |
168 | }; | |
169 | ||
dc47c0c1 AK |
170 | /* |
171 | * 'R' and 'C' update notes: | |
172 | * - Under pHyp or KVM, the updatepp path will not set C, thus it *will* | |
173 | * create writeable HPTEs without C set, because the hcall H_PROTECT | |
174 | * that we use in that case will not update C | |
175 | * - The above is however not a problem, because we also don't do that | |
176 | * fancy "no flush" variant of eviction and we use H_REMOVE which will | |
177 | * do the right thing and thus we don't have the race I described earlier | |
178 | * | |
179 | * - Under bare metal, we do have the race, so we need R and C set | |
180 | * - We make sure R is always set and never lost | |
181 | * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping | |
182 | */ | |
c6a3c495 | 183 | unsigned long htab_convert_pte_flags(unsigned long pteflags) |
bc033b63 | 184 | { |
c6a3c495 | 185 | unsigned long rflags = 0; |
bc033b63 BH |
186 | |
187 | /* _PAGE_EXEC -> NOEXEC */ | |
188 | if ((pteflags & _PAGE_EXEC) == 0) | |
189 | rflags |= HPTE_R_N; | |
c6a3c495 | 190 | /* |
e58e87ad | 191 | * PPP bits: |
1ec3f937 | 192 | * Linux uses slb key 0 for kernel and 1 for user. |
e58e87ad AK |
193 | * kernel RW areas are mapped with PPP=0b000 |
194 | * User area is mapped with PPP=0b010 for read/write | |
195 | * or PPP=0b011 for read-only (including writeable but clean pages). | |
bc033b63 | 196 | */ |
e58e87ad AK |
197 | if (pteflags & _PAGE_PRIVILEGED) { |
198 | /* | |
199 | * Kernel read only mapped with ppp bits 0b110 | |
200 | */ | |
984d7a1e AK |
201 | if (!(pteflags & _PAGE_WRITE)) { |
202 | if (mmu_has_feature(MMU_FTR_KERNEL_RO)) | |
203 | rflags |= (HPTE_R_PP0 | 0x2); | |
204 | else | |
205 | rflags |= 0x3; | |
206 | } | |
e58e87ad | 207 | } else { |
c7d54842 AK |
208 | if (pteflags & _PAGE_RWX) |
209 | rflags |= 0x2; | |
210 | if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY))) | |
c6a3c495 AK |
211 | rflags |= 0x1; |
212 | } | |
c8c06f5a | 213 | /* |
dc47c0c1 AK |
214 | * We can't allow hardware to update hpte bits. Hence always |
215 | * set 'R' bit and set 'C' if it is a write fault | |
c8c06f5a | 216 | */ |
e568006b | 217 | rflags |= HPTE_R_R; |
dc47c0c1 AK |
218 | |
219 | if (pteflags & _PAGE_DIRTY) | |
220 | rflags |= HPTE_R_C; | |
40e8550a AK |
221 | /* |
222 | * Add in WIG bits | |
223 | */ | |
30bda41a AK |
224 | |
225 | if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) | |
40e8550a | 226 | rflags |= HPTE_R_I; |
e568006b | 227 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT) |
30bda41a | 228 | rflags |= (HPTE_R_I | HPTE_R_G); |
e568006b AK |
229 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO) |
230 | rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M); | |
231 | else | |
232 | /* | |
233 | * Add memory coherence if cache inhibited is not set | |
234 | */ | |
235 | rflags |= HPTE_R_M; | |
40e8550a | 236 | |
a6590ca5 | 237 | rflags |= pte_to_hpte_pkey_bits(pteflags); |
40e8550a | 238 | return rflags; |
bc033b63 | 239 | } |
3c726f8d BH |
240 | |
241 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
bc033b63 | 242 | unsigned long pstart, unsigned long prot, |
1189be65 | 243 | int psize, int ssize) |
1da177e4 | 244 | { |
3c726f8d BH |
245 | unsigned long vaddr, paddr; |
246 | unsigned int step, shift; | |
3c726f8d | 247 | int ret = 0; |
1da177e4 | 248 | |
3c726f8d BH |
249 | shift = mmu_psize_defs[psize].shift; |
250 | step = 1 << shift; | |
1da177e4 | 251 | |
bc033b63 BH |
252 | prot = htab_convert_pte_flags(prot); |
253 | ||
254 | DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", | |
255 | vstart, vend, pstart, prot, psize, ssize); | |
256 | ||
3c726f8d BH |
257 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
258 | vaddr += step, paddr += step) { | |
370a908d | 259 | unsigned long hash, hpteg; |
1189be65 | 260 | unsigned long vsid = get_kernel_vsid(vaddr, ssize); |
5524a27d | 261 | unsigned long vpn = hpt_vpn(vaddr, vsid, ssize); |
9e88ba4e PM |
262 | unsigned long tprot = prot; |
263 | ||
c60ac569 AK |
264 | /* |
265 | * If we hit a bad address return error. | |
266 | */ | |
267 | if (!vsid) | |
268 | return -1; | |
9e88ba4e | 269 | /* Make kernel text executable */ |
549e8152 | 270 | if (overlaps_kernel_text(vaddr, vaddr + step)) |
9e88ba4e | 271 | tprot &= ~HPTE_R_N; |
1da177e4 | 272 | |
b18db0b8 AG |
273 | /* Make kvm guest trampolines executable */ |
274 | if (overlaps_kvm_tmp(vaddr, vaddr + step)) | |
275 | tprot &= ~HPTE_R_N; | |
276 | ||
429d2e83 MS |
277 | /* |
278 | * If relocatable, check if it overlaps interrupt vectors that | |
279 | * are copied down to real 0. For relocatable kernel | |
280 | * (e.g. kdump case) we copy interrupt vectors down to real | |
281 | * address 0. Mark that region as executable. This is | |
282 | * because on p8 system with relocation on exception feature | |
283 | * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence | |
284 | * in order to execute the interrupt handlers in virtual | |
285 | * mode the vector region need to be marked as executable. | |
286 | */ | |
287 | if ((PHYSICAL_START > MEMORY_START) && | |
288 | overlaps_interrupt_vector_text(vaddr, vaddr + step)) | |
289 | tprot &= ~HPTE_R_N; | |
290 | ||
5524a27d | 291 | hash = hpt_hash(vpn, shift, ssize); |
1da177e4 LT |
292 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
293 | ||
7025776e BH |
294 | BUG_ON(!mmu_hash_ops.hpte_insert); |
295 | ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot, | |
296 | HPTE_V_BOLTED, psize, psize, | |
297 | ssize); | |
c30a4df3 | 298 | |
3c726f8d BH |
299 | if (ret < 0) |
300 | break; | |
e7df0d88 | 301 | |
370a908d | 302 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
303 | if (debug_pagealloc_enabled() && |
304 | (paddr >> PAGE_SHIFT) < linear_map_hash_count) | |
370a908d BH |
305 | linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; |
306 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
3c726f8d BH |
307 | } |
308 | return ret < 0 ? ret : 0; | |
309 | } | |
1da177e4 | 310 | |
ed5694a8 | 311 | int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
f8c8803b BP |
312 | int psize, int ssize) |
313 | { | |
314 | unsigned long vaddr; | |
315 | unsigned int step, shift; | |
27828f98 DG |
316 | int rc; |
317 | int ret = 0; | |
f8c8803b BP |
318 | |
319 | shift = mmu_psize_defs[psize].shift; | |
320 | step = 1 << shift; | |
321 | ||
7025776e | 322 | if (!mmu_hash_ops.hpte_removebolted) |
abd0a0e7 | 323 | return -ENODEV; |
f8c8803b | 324 | |
27828f98 | 325 | for (vaddr = vstart; vaddr < vend; vaddr += step) { |
7025776e | 326 | rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize); |
27828f98 DG |
327 | if (rc == -ENOENT) { |
328 | ret = -ENOENT; | |
329 | continue; | |
330 | } | |
331 | if (rc < 0) | |
332 | return rc; | |
333 | } | |
52db9b44 | 334 | |
27828f98 | 335 | return ret; |
f8c8803b BP |
336 | } |
337 | ||
faf78829 OH |
338 | static bool disable_1tb_segments = false; |
339 | ||
340 | static int __init parse_disable_1tb_segments(char *p) | |
341 | { | |
342 | disable_1tb_segments = true; | |
343 | return 0; | |
344 | } | |
345 | early_param("disable_1tb_segments", parse_disable_1tb_segments); | |
346 | ||
1189be65 PM |
347 | static int __init htab_dt_scan_seg_sizes(unsigned long node, |
348 | const char *uname, int depth, | |
349 | void *data) | |
350 | { | |
9d0c4dfe RH |
351 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
352 | const __be32 *prop; | |
353 | int size = 0; | |
1189be65 PM |
354 | |
355 | /* We are scanning "cpu" nodes only */ | |
356 | if (type == NULL || strcmp(type, "cpu") != 0) | |
357 | return 0; | |
358 | ||
12f04f2b | 359 | prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size); |
1189be65 PM |
360 | if (prop == NULL) |
361 | return 0; | |
362 | for (; size >= 4; size -= 4, ++prop) { | |
12f04f2b | 363 | if (be32_to_cpu(prop[0]) == 40) { |
1189be65 | 364 | DBG("1T segment support detected\n"); |
faf78829 OH |
365 | |
366 | if (disable_1tb_segments) { | |
367 | DBG("1T segments disabled by command line\n"); | |
368 | break; | |
369 | } | |
370 | ||
44ae3ab3 | 371 | cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; |
f5534004 | 372 | return 1; |
1189be65 | 373 | } |
1189be65 | 374 | } |
44ae3ab3 | 375 | cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; |
1189be65 PM |
376 | return 0; |
377 | } | |
378 | ||
b1022fbd AK |
379 | static int __init get_idx_from_shift(unsigned int shift) |
380 | { | |
381 | int idx = -1; | |
382 | ||
383 | switch (shift) { | |
384 | case 0xc: | |
385 | idx = MMU_PAGE_4K; | |
386 | break; | |
387 | case 0x10: | |
388 | idx = MMU_PAGE_64K; | |
389 | break; | |
390 | case 0x14: | |
391 | idx = MMU_PAGE_1M; | |
392 | break; | |
393 | case 0x18: | |
394 | idx = MMU_PAGE_16M; | |
395 | break; | |
396 | case 0x22: | |
397 | idx = MMU_PAGE_16G; | |
398 | break; | |
399 | } | |
400 | return idx; | |
401 | } | |
402 | ||
3c726f8d BH |
403 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
404 | const char *uname, int depth, | |
405 | void *data) | |
406 | { | |
9d0c4dfe RH |
407 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
408 | const __be32 *prop; | |
409 | int size = 0; | |
3c726f8d BH |
410 | |
411 | /* We are scanning "cpu" nodes only */ | |
412 | if (type == NULL || strcmp(type, "cpu") != 0) | |
413 | return 0; | |
414 | ||
12f04f2b | 415 | prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size); |
9e34992a ME |
416 | if (!prop) |
417 | return 0; | |
418 | ||
419 | pr_info("Page sizes from device-tree:\n"); | |
420 | size /= 4; | |
421 | cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); | |
422 | while(size > 0) { | |
423 | unsigned int base_shift = be32_to_cpu(prop[0]); | |
424 | unsigned int slbenc = be32_to_cpu(prop[1]); | |
425 | unsigned int lpnum = be32_to_cpu(prop[2]); | |
426 | struct mmu_psize_def *def; | |
427 | int idx, base_idx; | |
428 | ||
429 | size -= 3; prop += 3; | |
430 | base_idx = get_idx_from_shift(base_shift); | |
431 | if (base_idx < 0) { | |
432 | /* skip the pte encoding also */ | |
433 | prop += lpnum * 2; size -= lpnum * 2; | |
434 | continue; | |
435 | } | |
436 | def = &mmu_psize_defs[base_idx]; | |
437 | if (base_idx == MMU_PAGE_16M) | |
438 | cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; | |
439 | ||
440 | def->shift = base_shift; | |
441 | if (base_shift <= 23) | |
442 | def->avpnm = 0; | |
443 | else | |
444 | def->avpnm = (1 << (base_shift - 23)) - 1; | |
445 | def->sllp = slbenc; | |
446 | /* | |
447 | * We don't know for sure what's up with tlbiel, so | |
448 | * for now we only set it for 4K and 64K pages | |
449 | */ | |
450 | if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) | |
451 | def->tlbiel = 1; | |
452 | else | |
453 | def->tlbiel = 0; | |
454 | ||
455 | while (size > 0 && lpnum) { | |
456 | unsigned int shift = be32_to_cpu(prop[0]); | |
457 | int penc = be32_to_cpu(prop[1]); | |
458 | ||
459 | prop += 2; size -= 2; | |
460 | lpnum--; | |
461 | ||
462 | idx = get_idx_from_shift(shift); | |
463 | if (idx < 0) | |
b1022fbd | 464 | continue; |
9e34992a ME |
465 | |
466 | if (penc == -1) | |
467 | pr_err("Invalid penc for base_shift=%d " | |
468 | "shift=%d\n", base_shift, shift); | |
469 | ||
470 | def->penc[idx] = penc; | |
471 | pr_info("base_shift=%d: shift=%d, sllp=0x%04lx," | |
472 | " avpnm=0x%08lx, tlbiel=%d, penc=%d\n", | |
473 | base_shift, shift, def->sllp, | |
474 | def->avpnm, def->tlbiel, def->penc[idx]); | |
1da177e4 | 475 | } |
3c726f8d | 476 | } |
9e34992a ME |
477 | |
478 | return 1; | |
3c726f8d BH |
479 | } |
480 | ||
e16a9c09 | 481 | #ifdef CONFIG_HUGETLB_PAGE |
658013e9 JT |
482 | /* Scan for 16G memory blocks that have been set aside for huge pages |
483 | * and reserve those blocks for 16G huge pages. | |
484 | */ | |
485 | static int __init htab_dt_scan_hugepage_blocks(unsigned long node, | |
486 | const char *uname, int depth, | |
487 | void *data) { | |
9d0c4dfe RH |
488 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
489 | const __be64 *addr_prop; | |
490 | const __be32 *page_count_prop; | |
658013e9 JT |
491 | unsigned int expected_pages; |
492 | long unsigned int phys_addr; | |
493 | long unsigned int block_size; | |
494 | ||
495 | /* We are scanning "memory" nodes only */ | |
496 | if (type == NULL || strcmp(type, "memory") != 0) | |
497 | return 0; | |
498 | ||
499 | /* This property is the log base 2 of the number of virtual pages that | |
500 | * will represent this memory block. */ | |
501 | page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); | |
502 | if (page_count_prop == NULL) | |
503 | return 0; | |
12f04f2b | 504 | expected_pages = (1 << be32_to_cpu(page_count_prop[0])); |
658013e9 JT |
505 | addr_prop = of_get_flat_dt_prop(node, "reg", NULL); |
506 | if (addr_prop == NULL) | |
507 | return 0; | |
12f04f2b AB |
508 | phys_addr = be64_to_cpu(addr_prop[0]); |
509 | block_size = be64_to_cpu(addr_prop[1]); | |
658013e9 JT |
510 | if (block_size != (16 * GB)) |
511 | return 0; | |
512 | printk(KERN_INFO "Huge page(16GB) memory: " | |
513 | "addr = 0x%lX size = 0x%lX pages = %d\n", | |
514 | phys_addr, block_size, expected_pages); | |
23493c12 | 515 | if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) { |
95f72d1e | 516 | memblock_reserve(phys_addr, block_size * expected_pages); |
79cc38de | 517 | pseries_add_gpage(phys_addr, block_size, expected_pages); |
4792adba | 518 | } |
658013e9 JT |
519 | return 0; |
520 | } | |
e16a9c09 | 521 | #endif /* CONFIG_HUGETLB_PAGE */ |
658013e9 | 522 | |
b1022fbd AK |
523 | static void mmu_psize_set_default_penc(void) |
524 | { | |
525 | int bpsize, apsize; | |
526 | for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) | |
527 | for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++) | |
528 | mmu_psize_defs[bpsize].penc[apsize] = -1; | |
529 | } | |
530 | ||
9048e648 AG |
531 | #ifdef CONFIG_PPC_64K_PAGES |
532 | ||
533 | static bool might_have_hea(void) | |
534 | { | |
535 | /* | |
536 | * The HEA ethernet adapter requires awareness of the | |
537 | * GX bus. Without that awareness we can easily assume | |
538 | * we will never see an HEA ethernet device. | |
539 | */ | |
540 | #ifdef CONFIG_IBMEBUS | |
2b4e3ad8 | 541 | return !cpu_has_feature(CPU_FTR_ARCH_207S) && |
08bf75ba | 542 | firmware_has_feature(FW_FEATURE_SPLPAR); |
9048e648 AG |
543 | #else |
544 | return false; | |
545 | #endif | |
546 | } | |
547 | ||
548 | #endif /* #ifdef CONFIG_PPC_64K_PAGES */ | |
549 | ||
bacf9cf8 | 550 | static void __init htab_scan_page_sizes(void) |
3c726f8d BH |
551 | { |
552 | int rc; | |
553 | ||
b1022fbd AK |
554 | /* se the invalid penc to -1 */ |
555 | mmu_psize_set_default_penc(); | |
556 | ||
3c726f8d | 557 | /* Default to 4K pages only */ |
471d7ff8 NP |
558 | memcpy(mmu_psize_defs, mmu_psize_defaults, |
559 | sizeof(mmu_psize_defaults)); | |
3c726f8d BH |
560 | |
561 | /* | |
562 | * Try to find the available page sizes in the device-tree | |
563 | */ | |
564 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
b8f1b4f8 | 565 | if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) { |
bacf9cf8 ME |
566 | /* |
567 | * Nothing in the device-tree, but the CPU supports 16M pages, | |
568 | * so let's fallback on a known size list for 16M capable CPUs. | |
569 | */ | |
3c726f8d BH |
570 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, |
571 | sizeof(mmu_psize_defaults_gp)); | |
bacf9cf8 ME |
572 | } |
573 | ||
574 | #ifdef CONFIG_HUGETLB_PAGE | |
85975387 HB |
575 | if (!hugetlb_disabled) { |
576 | /* Reserve 16G huge page memory sections for huge pages */ | |
577 | of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); | |
578 | } | |
bacf9cf8 ME |
579 | #endif /* CONFIG_HUGETLB_PAGE */ |
580 | } | |
581 | ||
0eeede0c PM |
582 | /* |
583 | * Fill in the hpte_page_sizes[] array. | |
584 | * We go through the mmu_psize_defs[] array looking for all the | |
585 | * supported base/actual page size combinations. Each combination | |
586 | * has a unique pagesize encoding (penc) value in the low bits of | |
587 | * the LP field of the HPTE. For actual page sizes less than 1MB, | |
588 | * some of the upper LP bits are used for RPN bits, meaning that | |
589 | * we need to fill in several entries in hpte_page_sizes[]. | |
590 | * | |
591 | * In diagrammatic form, with r = RPN bits and z = page size bits: | |
592 | * PTE LP actual page size | |
593 | * rrrr rrrz >=8KB | |
594 | * rrrr rrzz >=16KB | |
595 | * rrrr rzzz >=32KB | |
596 | * rrrr zzzz >=64KB | |
597 | * ... | |
598 | * | |
599 | * The zzzz bits are implementation-specific but are chosen so that | |
600 | * no encoding for a larger page size uses the same value in its | |
601 | * low-order N bits as the encoding for the 2^(12+N) byte page size | |
602 | * (if it exists). | |
603 | */ | |
604 | static void init_hpte_page_sizes(void) | |
605 | { | |
606 | long int ap, bp; | |
607 | long int shift, penc; | |
608 | ||
609 | for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) { | |
610 | if (!mmu_psize_defs[bp].shift) | |
611 | continue; /* not a supported page size */ | |
612 | for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) { | |
613 | penc = mmu_psize_defs[bp].penc[ap]; | |
10527e80 | 614 | if (penc == -1 || !mmu_psize_defs[ap].shift) |
0eeede0c PM |
615 | continue; |
616 | shift = mmu_psize_defs[ap].shift - LP_SHIFT; | |
617 | if (shift <= 0) | |
618 | continue; /* should never happen */ | |
619 | /* | |
620 | * For page sizes less than 1MB, this loop | |
621 | * replicates the entry for all possible values | |
622 | * of the rrrr bits. | |
623 | */ | |
624 | while (penc < (1 << LP_BITS)) { | |
625 | hpte_page_sizes[penc] = (ap << 4) | bp; | |
626 | penc += 1 << shift; | |
627 | } | |
628 | } | |
629 | } | |
630 | } | |
631 | ||
bacf9cf8 ME |
632 | static void __init htab_init_page_sizes(void) |
633 | { | |
0eeede0c PM |
634 | init_hpte_page_sizes(); |
635 | ||
e7df0d88 JK |
636 | if (!debug_pagealloc_enabled()) { |
637 | /* | |
638 | * Pick a size for the linear mapping. Currently, we only | |
639 | * support 16M, 1M and 4K which is the default | |
640 | */ | |
641 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
642 | mmu_linear_psize = MMU_PAGE_16M; | |
643 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
644 | mmu_linear_psize = MMU_PAGE_1M; | |
645 | } | |
3c726f8d | 646 | |
bf72aeba | 647 | #ifdef CONFIG_PPC_64K_PAGES |
3c726f8d BH |
648 | /* |
649 | * Pick a size for the ordinary pages. Default is 4K, we support | |
bf72aeba PM |
650 | * 64K for user mappings and vmalloc if supported by the processor. |
651 | * We only use 64k for ioremap if the processor | |
652 | * (and firmware) support cache-inhibited large pages. | |
653 | * If not, we use 4k and set mmu_ci_restrictions so that | |
654 | * hash_page knows to switch processes that use cache-inhibited | |
655 | * mappings to 4k pages. | |
3c726f8d | 656 | */ |
bf72aeba | 657 | if (mmu_psize_defs[MMU_PAGE_64K].shift) { |
3c726f8d | 658 | mmu_virtual_psize = MMU_PAGE_64K; |
bf72aeba | 659 | mmu_vmalloc_psize = MMU_PAGE_64K; |
370a908d BH |
660 | if (mmu_linear_psize == MMU_PAGE_4K) |
661 | mmu_linear_psize = MMU_PAGE_64K; | |
44ae3ab3 | 662 | if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { |
cfe666b1 | 663 | /* |
9048e648 AG |
664 | * When running on pSeries using 64k pages for ioremap |
665 | * would stop us accessing the HEA ethernet. So if we | |
666 | * have the chance of ever seeing one, stay at 4k. | |
cfe666b1 | 667 | */ |
2b4e3ad8 | 668 | if (!might_have_hea()) |
cfe666b1 PM |
669 | mmu_io_psize = MMU_PAGE_64K; |
670 | } else | |
bf72aeba PM |
671 | mmu_ci_restrictions = 1; |
672 | } | |
370a908d | 673 | #endif /* CONFIG_PPC_64K_PAGES */ |
3c726f8d | 674 | |
cec08e7a BH |
675 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
676 | /* We try to use 16M pages for vmemmap if that is supported | |
677 | * and we have at least 1G of RAM at boot | |
678 | */ | |
679 | if (mmu_psize_defs[MMU_PAGE_16M].shift && | |
95f72d1e | 680 | memblock_phys_mem_size() >= 0x40000000) |
cec08e7a BH |
681 | mmu_vmemmap_psize = MMU_PAGE_16M; |
682 | else if (mmu_psize_defs[MMU_PAGE_64K].shift) | |
683 | mmu_vmemmap_psize = MMU_PAGE_64K; | |
684 | else | |
685 | mmu_vmemmap_psize = MMU_PAGE_4K; | |
686 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
687 | ||
bf72aeba | 688 | printk(KERN_DEBUG "Page orders: linear mapping = %d, " |
cec08e7a BH |
689 | "virtual = %d, io = %d" |
690 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
691 | ", vmemmap = %d" | |
692 | #endif | |
693 | "\n", | |
3c726f8d | 694 | mmu_psize_defs[mmu_linear_psize].shift, |
bf72aeba | 695 | mmu_psize_defs[mmu_virtual_psize].shift, |
cec08e7a BH |
696 | mmu_psize_defs[mmu_io_psize].shift |
697 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
698 | ,mmu_psize_defs[mmu_vmemmap_psize].shift | |
699 | #endif | |
700 | ); | |
3c726f8d BH |
701 | } |
702 | ||
703 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
704 | const char *uname, int depth, | |
705 | void *data) | |
706 | { | |
9d0c4dfe RH |
707 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
708 | const __be32 *prop; | |
3c726f8d BH |
709 | |
710 | /* We are scanning "cpu" nodes only */ | |
711 | if (type == NULL || strcmp(type, "cpu") != 0) | |
712 | return 0; | |
713 | ||
12f04f2b | 714 | prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL); |
3c726f8d BH |
715 | if (prop != NULL) { |
716 | /* pft_size[0] is the NUMA CEC cookie */ | |
12f04f2b | 717 | ppc64_pft_size = be32_to_cpu(prop[1]); |
3c726f8d | 718 | return 1; |
1da177e4 | 719 | } |
3c726f8d | 720 | return 0; |
1da177e4 LT |
721 | } |
722 | ||
5c3c7ede | 723 | unsigned htab_shift_for_mem_size(unsigned long mem_size) |
3eac8c69 | 724 | { |
5c3c7ede DG |
725 | unsigned memshift = __ilog2(mem_size); |
726 | unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift; | |
727 | unsigned pteg_shift; | |
728 | ||
729 | /* round mem_size up to next power of 2 */ | |
730 | if ((1UL << memshift) < mem_size) | |
731 | memshift += 1; | |
3eac8c69 | 732 | |
5c3c7ede DG |
733 | /* aim for 2 pages / pteg */ |
734 | pteg_shift = memshift - (pshift + 1); | |
3eac8c69 | 735 | |
5c3c7ede DG |
736 | /* |
737 | * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab | |
738 | * size permitted by the architecture. | |
739 | */ | |
740 | return max(pteg_shift + 7, 18U); | |
741 | } | |
742 | ||
743 | static unsigned long __init htab_get_table_size(void) | |
744 | { | |
3c726f8d | 745 | /* If hash size isn't already provided by the platform, we try to |
943ffb58 | 746 | * retrieve it from the device-tree. If it's not there neither, we |
3c726f8d | 747 | * calculate it now based on the total RAM size |
3eac8c69 | 748 | */ |
3c726f8d BH |
749 | if (ppc64_pft_size == 0) |
750 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
751 | if (ppc64_pft_size) |
752 | return 1UL << ppc64_pft_size; | |
753 | ||
5c3c7ede | 754 | return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size()); |
3eac8c69 PM |
755 | } |
756 | ||
54b79248 | 757 | #ifdef CONFIG_MEMORY_HOTPLUG |
f172acbf | 758 | int resize_hpt_for_hotplug(unsigned long new_mem_size) |
438cc81a DG |
759 | { |
760 | unsigned target_hpt_shift; | |
761 | ||
762 | if (!mmu_hash_ops.resize_hpt) | |
f172acbf | 763 | return 0; |
438cc81a DG |
764 | |
765 | target_hpt_shift = htab_shift_for_mem_size(new_mem_size); | |
766 | ||
767 | /* | |
768 | * To avoid lots of HPT resizes if memory size is fluctuating | |
769 | * across a boundary, we deliberately have some hysterisis | |
770 | * here: we immediately increase the HPT size if the target | |
771 | * shift exceeds the current shift, but we won't attempt to | |
772 | * reduce unless the target shift is at least 2 below the | |
773 | * current shift | |
774 | */ | |
f172acbf LV |
775 | if (target_hpt_shift > ppc64_pft_size || |
776 | target_hpt_shift < ppc64_pft_size - 1) | |
777 | return mmu_hash_ops.resize_hpt(target_hpt_shift); | |
778 | ||
779 | return 0; | |
438cc81a DG |
780 | } |
781 | ||
29ab6c47 | 782 | int hash__create_section_mapping(unsigned long start, unsigned long end, int nid) |
54b79248 | 783 | { |
e0909392 AK |
784 | int rc; |
785 | ||
786 | if (end >= H_VMALLOC_START) { | |
787 | pr_warn("Outisde the supported range\n"); | |
788 | return -1; | |
789 | } | |
790 | ||
791 | rc = htab_bolt_mapping(start, end, __pa(start), | |
792 | pgprot_val(PAGE_KERNEL), mmu_linear_psize, | |
793 | mmu_kernel_ssize); | |
1dace6c6 DG |
794 | |
795 | if (rc < 0) { | |
796 | int rc2 = htab_remove_mapping(start, end, mmu_linear_psize, | |
797 | mmu_kernel_ssize); | |
798 | BUG_ON(rc2 && (rc2 != -ENOENT)); | |
799 | } | |
800 | return rc; | |
54b79248 | 801 | } |
f8c8803b | 802 | |
32b53c01 | 803 | int hash__remove_section_mapping(unsigned long start, unsigned long end) |
f8c8803b | 804 | { |
abd0a0e7 DG |
805 | int rc = htab_remove_mapping(start, end, mmu_linear_psize, |
806 | mmu_kernel_ssize); | |
807 | WARN_ON(rc < 0); | |
808 | return rc; | |
f8c8803b | 809 | } |
54b79248 MK |
810 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
811 | ||
50de596d | 812 | static void __init hash_init_partition_table(phys_addr_t hash_table, |
4b7a3504 | 813 | unsigned long htab_size) |
50de596d | 814 | { |
9d661958 | 815 | mmu_partition_table_init(); |
50de596d AK |
816 | |
817 | /* | |
9d661958 PM |
818 | * PS field (VRMA page size) is not used for LPID 0, hence set to 0. |
819 | * For now, UPRT is 0 and we have no segment table. | |
50de596d | 820 | */ |
4b7a3504 | 821 | htab_size = __ilog2(htab_size) - 18; |
9d661958 | 822 | mmu_partition_table_set_entry(0, hash_table | htab_size, 0); |
56547411 | 823 | pr_info("Partition table %p\n", partition_tb); |
50de596d AK |
824 | } |
825 | ||
757c74d2 | 826 | static void __init htab_initialize(void) |
1da177e4 | 827 | { |
337a7128 | 828 | unsigned long table; |
1da177e4 | 829 | unsigned long pteg_count; |
9e88ba4e | 830 | unsigned long prot; |
5556ecf5 | 831 | unsigned long base = 0, size = 0; |
28be7072 | 832 | struct memblock_region *reg; |
3c726f8d | 833 | |
1da177e4 LT |
834 | DBG(" -> htab_initialize()\n"); |
835 | ||
44ae3ab3 | 836 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { |
1189be65 PM |
837 | mmu_kernel_ssize = MMU_SEGSIZE_1T; |
838 | mmu_highuser_ssize = MMU_SEGSIZE_1T; | |
839 | printk(KERN_INFO "Using 1TB segments\n"); | |
840 | } | |
841 | ||
1da177e4 LT |
842 | /* |
843 | * Calculate the required size of the htab. We want the number of | |
844 | * PTEGs to equal one half the number of real pages. | |
845 | */ | |
3c726f8d | 846 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
847 | pteg_count = htab_size_bytes >> 7; |
848 | ||
1da177e4 LT |
849 | htab_hash_mask = pteg_count - 1; |
850 | ||
5556ecf5 BH |
851 | if (firmware_has_feature(FW_FEATURE_LPAR) || |
852 | firmware_has_feature(FW_FEATURE_PS3_LV1)) { | |
1da177e4 LT |
853 | /* Using a hypervisor which owns the htab */ |
854 | htab_address = NULL; | |
855 | _SDR1 = 0; | |
dbfcf3cb PM |
856 | /* |
857 | * On POWER9, we need to do a H_REGISTER_PROC_TBL hcall | |
858 | * to inform the hypervisor that we wish to use the HPT. | |
859 | */ | |
860 | if (cpu_has_feature(CPU_FTR_ARCH_300)) | |
861 | register_process_table(0, 0, 0); | |
3ccc00a7 MS |
862 | #ifdef CONFIG_FA_DUMP |
863 | /* | |
864 | * If firmware assisted dump is active firmware preserves | |
865 | * the contents of htab along with entire partition memory. | |
866 | * Clear the htab if firmware assisted dump is active so | |
867 | * that we dont end up using old mappings. | |
868 | */ | |
7025776e BH |
869 | if (is_fadump_active() && mmu_hash_ops.hpte_clear_all) |
870 | mmu_hash_ops.hpte_clear_all(); | |
3ccc00a7 | 871 | #endif |
1da177e4 | 872 | } else { |
5556ecf5 BH |
873 | unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE; |
874 | ||
875 | #ifdef CONFIG_PPC_CELL | |
876 | /* | |
877 | * Cell may require the hash table down low when using the | |
878 | * Axon IOMMU in order to fit the dynamic region over it, see | |
879 | * comments in cell/iommu.c | |
1da177e4 | 880 | */ |
5556ecf5 | 881 | if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) { |
31bf1119 | 882 | limit = 0x80000000; |
5556ecf5 BH |
883 | pr_info("Hash table forced below 2G for Axon IOMMU\n"); |
884 | } | |
885 | #endif /* CONFIG_PPC_CELL */ | |
41d824bf | 886 | |
0ba9e6ed MR |
887 | table = memblock_phys_alloc_range(htab_size_bytes, |
888 | htab_size_bytes, | |
889 | 0, limit); | |
890 | if (!table) | |
891 | panic("ERROR: Failed to allocate %pa bytes below %pa\n", | |
892 | &htab_size_bytes, &limit); | |
1da177e4 LT |
893 | |
894 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
895 | htab_size_bytes); | |
896 | ||
70267a7f | 897 | htab_address = __va(table); |
1da177e4 LT |
898 | |
899 | /* htab absolute addr + encoded htabsize */ | |
4b7a3504 | 900 | _SDR1 = table + __ilog2(htab_size_bytes) - 18; |
1da177e4 LT |
901 | |
902 | /* Initialize the HPT with no entries */ | |
903 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 | 904 | |
50de596d AK |
905 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
906 | /* Set SDR1 */ | |
907 | mtspr(SPRN_SDR1, _SDR1); | |
908 | else | |
4b7a3504 | 909 | hash_init_partition_table(table, htab_size_bytes); |
1da177e4 LT |
910 | } |
911 | ||
f5ea64dc | 912 | prot = pgprot_val(PAGE_KERNEL); |
1da177e4 | 913 | |
370a908d | 914 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
915 | if (debug_pagealloc_enabled()) { |
916 | linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; | |
f806714f MR |
917 | linear_map_hash_slots = memblock_alloc_try_nid( |
918 | linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT, | |
919 | ppc64_rma_size, NUMA_NO_NODE); | |
8a7f97b9 MR |
920 | if (!linear_map_hash_slots) |
921 | panic("%s: Failed to allocate %lu bytes max_addr=%pa\n", | |
922 | __func__, linear_map_hash_count, &ppc64_rma_size); | |
e7df0d88 | 923 | } |
370a908d BH |
924 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
925 | ||
1da177e4 | 926 | /* create bolted the linear mapping in the hash table */ |
28be7072 BH |
927 | for_each_memblock(memory, reg) { |
928 | base = (unsigned long)__va(reg->base); | |
929 | size = reg->size; | |
1da177e4 | 930 | |
5c339919 | 931 | DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", |
9e88ba4e | 932 | base, size, prot); |
1da177e4 | 933 | |
e0909392 AK |
934 | if ((base + size) >= H_VMALLOC_START) { |
935 | pr_warn("Outisde the supported range\n"); | |
936 | continue; | |
937 | } | |
938 | ||
caf80e57 | 939 | BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), |
9e88ba4e | 940 | prot, mmu_linear_psize, mmu_kernel_ssize)); |
e63075a3 BH |
941 | } |
942 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); | |
1da177e4 LT |
943 | |
944 | /* | |
945 | * If we have a memory_limit and we've allocated TCEs then we need to | |
946 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
947 | * case that the TCEs start below memory_limit. | |
948 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
949 | * for either 4K or 16MB pages. | |
950 | */ | |
951 | if (tce_alloc_start) { | |
b5666f70 ME |
952 | tce_alloc_start = (unsigned long)__va(tce_alloc_start); |
953 | tce_alloc_end = (unsigned long)__va(tce_alloc_end); | |
1da177e4 LT |
954 | |
955 | if (base + size >= tce_alloc_start) | |
956 | tce_alloc_start = base + size + 1; | |
957 | ||
caf80e57 | 958 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
bc033b63 | 959 | __pa(tce_alloc_start), prot, |
1189be65 | 960 | mmu_linear_psize, mmu_kernel_ssize)); |
1da177e4 LT |
961 | } |
962 | ||
7d0daae4 | 963 | |
1da177e4 LT |
964 | DBG(" <- htab_initialize()\n"); |
965 | } | |
966 | #undef KB | |
967 | #undef MB | |
1da177e4 | 968 | |
bacf9cf8 ME |
969 | void __init hash__early_init_devtree(void) |
970 | { | |
971 | /* Initialize segment sizes */ | |
972 | of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); | |
973 | ||
974 | /* Initialize page sizes */ | |
975 | htab_scan_page_sizes(); | |
976 | } | |
977 | ||
70110186 | 978 | struct hash_mm_context init_hash_mm_context; |
756d08d1 | 979 | void __init hash__early_init_mmu(void) |
799d6046 | 980 | { |
9d2edb18 | 981 | #ifndef CONFIG_PPC_64K_PAGES |
6aa59f51 | 982 | /* |
9d2edb18 | 983 | * We have code in __hash_page_4K() and elsewhere, which assumes it can |
6aa59f51 AK |
984 | * do the following: |
985 | * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX); | |
986 | * | |
987 | * Where the slot number is between 0-15, and values of 8-15 indicate | |
988 | * the secondary bucket. For that code to work H_PAGE_F_SECOND and | |
989 | * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and | |
990 | * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here | |
991 | * with a BUILD_BUG_ON(). | |
992 | */ | |
993 | BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3))); | |
9d2edb18 | 994 | #endif /* CONFIG_PPC_64K_PAGES */ |
6aa59f51 | 995 | |
bacf9cf8 ME |
996 | htab_init_page_sizes(); |
997 | ||
dd1842a2 AK |
998 | /* |
999 | * initialize page table size | |
1000 | */ | |
5ed7ecd0 AK |
1001 | __pte_frag_nr = H_PTE_FRAG_NR; |
1002 | __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; | |
8a6c697b AK |
1003 | __pmd_frag_nr = H_PMD_FRAG_NR; |
1004 | __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT; | |
5ed7ecd0 | 1005 | |
dd1842a2 AK |
1006 | __pte_index_size = H_PTE_INDEX_SIZE; |
1007 | __pmd_index_size = H_PMD_INDEX_SIZE; | |
1008 | __pud_index_size = H_PUD_INDEX_SIZE; | |
1009 | __pgd_index_size = H_PGD_INDEX_SIZE; | |
fae22116 | 1010 | __pud_cache_index = H_PUD_CACHE_INDEX; |
dd1842a2 AK |
1011 | __pte_table_size = H_PTE_TABLE_SIZE; |
1012 | __pmd_table_size = H_PMD_TABLE_SIZE; | |
1013 | __pud_table_size = H_PUD_TABLE_SIZE; | |
1014 | __pgd_table_size = H_PGD_TABLE_SIZE; | |
a2f41eb9 AK |
1015 | /* |
1016 | * 4k use hugepd format, so for hash set then to | |
1017 | * zero | |
1018 | */ | |
da7ad366 AK |
1019 | __pmd_val_bits = HASH_PMD_VAL_BITS; |
1020 | __pud_val_bits = HASH_PUD_VAL_BITS; | |
1021 | __pgd_val_bits = HASH_PGD_VAL_BITS; | |
d6a9996e AK |
1022 | |
1023 | __kernel_virt_start = H_KERN_VIRT_START; | |
d6a9996e AK |
1024 | __vmalloc_start = H_VMALLOC_START; |
1025 | __vmalloc_end = H_VMALLOC_END; | |
63ee9b2f | 1026 | __kernel_io_start = H_KERN_IO_START; |
a35a3c6f | 1027 | __kernel_io_end = H_KERN_IO_END; |
0034d395 | 1028 | vmemmap = (struct page *)H_VMEMMAP_START; |
d6a9996e AK |
1029 | ioremap_bot = IOREMAP_BASE; |
1030 | ||
bfa37087 DS |
1031 | #ifdef CONFIG_PCI |
1032 | pci_io_base = ISA_IO_BASE; | |
1033 | #endif | |
1034 | ||
166dd7d3 BH |
1035 | /* Select appropriate backend */ |
1036 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) | |
1037 | ps3_early_mm_init(); | |
1038 | else if (firmware_has_feature(FW_FEATURE_LPAR)) | |
6364e84e | 1039 | hpte_init_pseries(); |
fbef66f0 | 1040 | else if (IS_ENABLED(CONFIG_PPC_NATIVE)) |
166dd7d3 BH |
1041 | hpte_init_native(); |
1042 | ||
7353644f ME |
1043 | if (!mmu_hash_ops.hpte_insert) |
1044 | panic("hash__early_init_mmu: No MMU hash ops defined!\n"); | |
1045 | ||
757c74d2 | 1046 | /* Initialize the MMU Hash table and create the linear mapping |
376af594 ME |
1047 | * of memory. Has to be done before SLB initialization as this is |
1048 | * currently where the page size encoding is obtained. | |
757c74d2 BH |
1049 | */ |
1050 | htab_initialize(); | |
1051 | ||
70110186 AK |
1052 | init_mm.context.hash_context = &init_hash_mm_context; |
1053 | init_mm.context.hash_context->slb_addr_limit = DEFAULT_MAP_WINDOW_USER64; | |
67fda38f | 1054 | |
56547411 | 1055 | pr_info("Initializing hash mmu with SLB\n"); |
376af594 | 1056 | /* Initialize SLB management */ |
13b3d13b | 1057 | slb_initialize(); |
d4748276 NP |
1058 | |
1059 | if (cpu_has_feature(CPU_FTR_ARCH_206) | |
1060 | && cpu_has_feature(CPU_FTR_HVMODE)) | |
1061 | tlbiel_all(); | |
757c74d2 BH |
1062 | } |
1063 | ||
1064 | #ifdef CONFIG_SMP | |
756d08d1 | 1065 | void hash__early_init_mmu_secondary(void) |
757c74d2 BH |
1066 | { |
1067 | /* Initialize hash table for that CPU */ | |
b5dcc609 | 1068 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
cac4a185 | 1069 | |
b5dcc609 AK |
1070 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
1071 | mtspr(SPRN_SDR1, _SDR1); | |
1072 | else | |
1073 | mtspr(SPRN_PTCR, | |
1074 | __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); | |
1075 | } | |
376af594 | 1076 | /* Initialize SLB */ |
13b3d13b | 1077 | slb_initialize(); |
d4748276 NP |
1078 | |
1079 | if (cpu_has_feature(CPU_FTR_ARCH_206) | |
1080 | && cpu_has_feature(CPU_FTR_HVMODE)) | |
1081 | tlbiel_all(); | |
799d6046 | 1082 | } |
757c74d2 | 1083 | #endif /* CONFIG_SMP */ |
799d6046 | 1084 | |
1da177e4 LT |
1085 | /* |
1086 | * Called by asm hashtable.S for doing lazy icache flush | |
1087 | */ | |
1088 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
1089 | { | |
1090 | struct page *page; | |
1091 | ||
76c8e25b BH |
1092 | if (!pfn_valid(pte_pfn(pte))) |
1093 | return pp; | |
1094 | ||
1da177e4 LT |
1095 | page = pte_page(pte); |
1096 | ||
1097 | /* page is dirty */ | |
1098 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
1099 | if (trap == 0x400) { | |
0895ecda | 1100 | flush_dcache_icache_page(page); |
1da177e4 LT |
1101 | set_bit(PG_arch_1, &page->flags); |
1102 | } else | |
3c726f8d | 1103 | pp |= HPTE_R_N; |
1da177e4 LT |
1104 | } |
1105 | return pp; | |
1106 | } | |
1107 | ||
3a8247cc | 1108 | #ifdef CONFIG_PPC_MM_SLICES |
54be0b9c | 1109 | static unsigned int get_paca_psize(unsigned long addr) |
3a8247cc | 1110 | { |
15472423 | 1111 | unsigned char *psizes; |
7aa0727f | 1112 | unsigned long index, mask_index; |
3a8247cc PM |
1113 | |
1114 | if (addr < SLICE_LOW_TOP) { | |
54be0b9c | 1115 | psizes = get_paca()->mm_ctx_low_slices_psize; |
3a8247cc | 1116 | index = GET_LOW_SLICE_INDEX(addr); |
15472423 | 1117 | } else { |
54be0b9c | 1118 | psizes = get_paca()->mm_ctx_high_slices_psize; |
15472423 | 1119 | index = GET_HIGH_SLICE_INDEX(addr); |
3a8247cc | 1120 | } |
7aa0727f | 1121 | mask_index = index & 0x1; |
15472423 | 1122 | return (psizes[index >> 1] >> (mask_index * 4)) & 0xF; |
3a8247cc PM |
1123 | } |
1124 | ||
1125 | #else | |
54be0b9c | 1126 | unsigned int get_paca_psize(unsigned long addr) |
3a8247cc | 1127 | { |
54be0b9c | 1128 | return get_paca()->mm_ctx_user_psize; |
3a8247cc PM |
1129 | } |
1130 | #endif | |
1131 | ||
721151d0 PM |
1132 | /* |
1133 | * Demote a segment to using 4k pages. | |
1134 | * For now this makes the whole process use 4k pages. | |
1135 | */ | |
721151d0 | 1136 | #ifdef CONFIG_PPC_64K_PAGES |
fa28237c | 1137 | void demote_segment_4k(struct mm_struct *mm, unsigned long addr) |
16f1c746 | 1138 | { |
54be0b9c | 1139 | if (get_slice_psize(mm, addr) == MMU_PAGE_4K) |
721151d0 | 1140 | return; |
3a8247cc | 1141 | slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); |
be3ebfe8 | 1142 | copro_flush_all_slbs(mm); |
54be0b9c ME |
1143 | if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) { |
1144 | ||
1145 | copy_mm_to_paca(mm); | |
94ee4272 | 1146 | slb_flush_and_restore_bolted(); |
54be0b9c | 1147 | } |
721151d0 | 1148 | } |
16f1c746 | 1149 | #endif /* CONFIG_PPC_64K_PAGES */ |
721151d0 | 1150 | |
fa28237c PM |
1151 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1152 | /* | |
1153 | * This looks up a 2-bit protection code for a 4k subpage of a 64k page. | |
1154 | * Userspace sets the subpage permissions using the subpage_prot system call. | |
1155 | * | |
1156 | * Result is 0: full permissions, _PAGE_RW: read-only, | |
73a1441a | 1157 | * _PAGE_RWX: no access. |
fa28237c | 1158 | */ |
d28513bc | 1159 | static int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c | 1160 | { |
60458fba | 1161 | struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context); |
fa28237c PM |
1162 | u32 spp = 0; |
1163 | u32 **sbpm, *sbpp; | |
1164 | ||
ef629cc5 AK |
1165 | if (!spt) |
1166 | return 0; | |
1167 | ||
fa28237c PM |
1168 | if (ea >= spt->maxaddr) |
1169 | return 0; | |
b0d436c7 | 1170 | if (ea < 0x100000000UL) { |
fa28237c PM |
1171 | /* addresses below 4GB use spt->low_prot */ |
1172 | sbpm = spt->low_prot; | |
1173 | } else { | |
1174 | sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; | |
1175 | if (!sbpm) | |
1176 | return 0; | |
1177 | } | |
1178 | sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; | |
1179 | if (!sbpp) | |
1180 | return 0; | |
1181 | spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; | |
1182 | ||
1183 | /* extract 2-bit bitfield for this 4k subpage */ | |
1184 | spp >>= 30 - 2 * ((ea >> 12) & 0xf); | |
1185 | ||
73a1441a AK |
1186 | /* |
1187 | * 0 -> full premission | |
1188 | * 1 -> Read only | |
1189 | * 2 -> no access. | |
1190 | * We return the flag that need to be cleared. | |
1191 | */ | |
1192 | spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0); | |
fa28237c PM |
1193 | return spp; |
1194 | } | |
1195 | ||
1196 | #else /* CONFIG_PPC_SUBPAGE_PROT */ | |
d28513bc | 1197 | static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c PM |
1198 | { |
1199 | return 0; | |
1200 | } | |
1201 | #endif | |
1202 | ||
4b8692c0 BH |
1203 | void hash_failure_debug(unsigned long ea, unsigned long access, |
1204 | unsigned long vsid, unsigned long trap, | |
d8139ebf | 1205 | int ssize, int psize, int lpsize, unsigned long pte) |
4b8692c0 BH |
1206 | { |
1207 | if (!printk_ratelimit()) | |
1208 | return; | |
1209 | pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", | |
1210 | ea, access, current->comm); | |
d8139ebf AK |
1211 | pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n", |
1212 | trap, vsid, ssize, psize, lpsize, pte); | |
4b8692c0 BH |
1213 | } |
1214 | ||
54be0b9c ME |
1215 | static void check_paca_psize(unsigned long ea, struct mm_struct *mm, |
1216 | int psize, bool user_region) | |
1217 | { | |
1218 | if (user_region) { | |
1219 | if (psize != get_paca_psize(ea)) { | |
1220 | copy_mm_to_paca(mm); | |
94ee4272 | 1221 | slb_flush_and_restore_bolted(); |
54be0b9c ME |
1222 | } |
1223 | } else if (get_paca()->vmalloc_sllp != | |
1224 | mmu_psize_defs[mmu_vmalloc_psize].sllp) { | |
1225 | get_paca()->vmalloc_sllp = | |
1226 | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
1227 | slb_vmalloc_update(); | |
1228 | } | |
1229 | } | |
1230 | ||
1da177e4 LT |
1231 | /* Result code is: |
1232 | * 0 - handled | |
1233 | * 1 - normal page fault | |
1234 | * -1 - critical hash insertion error | |
fa28237c | 1235 | * -2 - access not permitted by subpage protection mechanism |
1da177e4 | 1236 | */ |
aefa5688 AK |
1237 | int hash_page_mm(struct mm_struct *mm, unsigned long ea, |
1238 | unsigned long access, unsigned long trap, | |
1239 | unsigned long flags) | |
1da177e4 | 1240 | { |
891121e6 | 1241 | bool is_thp; |
ba12eede | 1242 | enum ctx_state prev_state = exception_enter(); |
a1128f8f | 1243 | pgd_t *pgdir; |
1da177e4 | 1244 | unsigned long vsid; |
1da177e4 | 1245 | pte_t *ptep; |
a4fe3ce7 | 1246 | unsigned hugeshift; |
aefa5688 | 1247 | int rc, user_region = 0; |
1189be65 | 1248 | int psize, ssize; |
1da177e4 | 1249 | |
3c726f8d BH |
1250 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
1251 | ea, access, trap); | |
cfcb3d80 | 1252 | trace_hash_fault(ea, access, trap); |
1f8d419e | 1253 | |
3c726f8d | 1254 | /* Get region & vsid */ |
0034d395 | 1255 | switch (get_region_id(ea)) { |
1da177e4 LT |
1256 | case USER_REGION_ID: |
1257 | user_region = 1; | |
3c726f8d BH |
1258 | if (! mm) { |
1259 | DBG_LOW(" user region with no mm !\n"); | |
ba12eede LZ |
1260 | rc = 1; |
1261 | goto bail; | |
3c726f8d | 1262 | } |
54be0b9c | 1263 | psize = get_slice_psize(mm, ea); |
1189be65 | 1264 | ssize = user_segment_size(ea); |
f384796c | 1265 | vsid = get_user_vsid(&mm->context, ea, ssize); |
1da177e4 | 1266 | break; |
1da177e4 | 1267 | case VMALLOC_REGION_ID: |
1189be65 | 1268 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); |
0034d395 AK |
1269 | psize = mmu_vmalloc_psize; |
1270 | ssize = mmu_kernel_ssize; | |
1271 | break; | |
1272 | ||
1273 | case IO_REGION_ID: | |
1274 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); | |
1275 | psize = mmu_io_psize; | |
1189be65 | 1276 | ssize = mmu_kernel_ssize; |
1da177e4 | 1277 | break; |
1da177e4 LT |
1278 | default: |
1279 | /* Not a valid range | |
1280 | * Send the problem up to do_page_fault | |
1281 | */ | |
ba12eede LZ |
1282 | rc = 1; |
1283 | goto bail; | |
1da177e4 | 1284 | } |
3c726f8d | 1285 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 1286 | |
c60ac569 AK |
1287 | /* Bad address. */ |
1288 | if (!vsid) { | |
1289 | DBG_LOW("Bad address!\n"); | |
ba12eede LZ |
1290 | rc = 1; |
1291 | goto bail; | |
c60ac569 | 1292 | } |
3c726f8d | 1293 | /* Get pgdir */ |
1da177e4 | 1294 | pgdir = mm->pgd; |
ba12eede LZ |
1295 | if (pgdir == NULL) { |
1296 | rc = 1; | |
1297 | goto bail; | |
1298 | } | |
1da177e4 | 1299 | |
3c726f8d | 1300 | /* Check CPU locality */ |
b426e4bd | 1301 | if (user_region && mm_is_thread_local(mm)) |
aefa5688 | 1302 | flags |= HPTE_LOCAL_UPDATE; |
1da177e4 | 1303 | |
16c2d476 | 1304 | #ifndef CONFIG_PPC_64K_PAGES |
a4fe3ce7 DG |
1305 | /* If we use 4K pages and our psize is not 4K, then we might |
1306 | * be hitting a special driver mapping, and need to align the | |
1307 | * address before we fetch the PTE. | |
1308 | * | |
1309 | * It could also be a hugepage mapping, in which case this is | |
1310 | * not necessary, but it's not harmful, either. | |
16c2d476 BH |
1311 | */ |
1312 | if (psize != MMU_PAGE_4K) | |
1313 | ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
1314 | #endif /* CONFIG_PPC_64K_PAGES */ | |
1315 | ||
3c726f8d | 1316 | /* Get PTE and page size from page tables */ |
94171b19 | 1317 | ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift); |
3c726f8d BH |
1318 | if (ptep == NULL || !pte_present(*ptep)) { |
1319 | DBG_LOW(" no PTE !\n"); | |
ba12eede LZ |
1320 | rc = 1; |
1321 | goto bail; | |
3c726f8d BH |
1322 | } |
1323 | ||
ca91e6c0 BH |
1324 | /* Add _PAGE_PRESENT to the required access perm */ |
1325 | access |= _PAGE_PRESENT; | |
1326 | ||
1327 | /* Pre-check access permissions (will be re-checked atomically | |
1328 | * in __hash_page_XX but this pre-check is a fast path | |
1329 | */ | |
ac29c640 | 1330 | if (!check_pte_access(access, pte_val(*ptep))) { |
ca91e6c0 | 1331 | DBG_LOW(" no access !\n"); |
ba12eede LZ |
1332 | rc = 1; |
1333 | goto bail; | |
ca91e6c0 BH |
1334 | } |
1335 | ||
ba12eede | 1336 | if (hugeshift) { |
891121e6 | 1337 | if (is_thp) |
6d492ecc | 1338 | rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep, |
aefa5688 | 1339 | trap, flags, ssize, psize); |
6d492ecc AK |
1340 | #ifdef CONFIG_HUGETLB_PAGE |
1341 | else | |
1342 | rc = __hash_page_huge(ea, access, vsid, ptep, trap, | |
aefa5688 | 1343 | flags, ssize, hugeshift, psize); |
6d492ecc AK |
1344 | #else |
1345 | else { | |
1346 | /* | |
1347 | * if we have hugeshift, and is not transhuge with | |
1348 | * hugetlb disabled, something is really wrong. | |
1349 | */ | |
1350 | rc = 1; | |
1351 | WARN_ON(1); | |
1352 | } | |
1353 | #endif | |
54be0b9c ME |
1354 | if (current->mm == mm) |
1355 | check_paca_psize(ea, mm, psize, user_region); | |
1356 | ||
ba12eede LZ |
1357 | goto bail; |
1358 | } | |
a4fe3ce7 | 1359 | |
3c726f8d BH |
1360 | #ifndef CONFIG_PPC_64K_PAGES |
1361 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
1362 | #else | |
1363 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
1364 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1365 | #endif | |
3c726f8d | 1366 | /* Do actual hashing */ |
16c2d476 | 1367 | #ifdef CONFIG_PPC_64K_PAGES |
945537df AK |
1368 | /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */ |
1369 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) { | |
721151d0 PM |
1370 | demote_segment_4k(mm, ea); |
1371 | psize = MMU_PAGE_4K; | |
1372 | } | |
1373 | ||
16f1c746 BH |
1374 | /* If this PTE is non-cacheable and we have restrictions on |
1375 | * using non cacheable large pages, then we switch to 4k | |
1376 | */ | |
30bda41a | 1377 | if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) { |
16f1c746 BH |
1378 | if (user_region) { |
1379 | demote_segment_4k(mm, ea); | |
1380 | psize = MMU_PAGE_4K; | |
1381 | } else if (ea < VMALLOC_END) { | |
1382 | /* | |
1383 | * some driver did a non-cacheable mapping | |
1384 | * in vmalloc space, so switch vmalloc | |
1385 | * to 4k pages | |
1386 | */ | |
1387 | printk(KERN_ALERT "Reducing vmalloc segment " | |
1388 | "to 4kB pages because of " | |
1389 | "non-cacheable mapping\n"); | |
1390 | psize = mmu_vmalloc_psize = MMU_PAGE_4K; | |
be3ebfe8 | 1391 | copro_flush_all_slbs(mm); |
bf72aeba | 1392 | } |
16f1c746 | 1393 | } |
09567e7f | 1394 | |
0863d7f2 AK |
1395 | #endif /* CONFIG_PPC_64K_PAGES */ |
1396 | ||
54be0b9c ME |
1397 | if (current->mm == mm) |
1398 | check_paca_psize(ea, mm, psize, user_region); | |
1399 | ||
73b341ef | 1400 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1401 | if (psize == MMU_PAGE_64K) |
aefa5688 AK |
1402 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1403 | flags, ssize); | |
3c726f8d | 1404 | else |
73b341ef | 1405 | #endif /* CONFIG_PPC_64K_PAGES */ |
fa28237c | 1406 | { |
a1128f8f | 1407 | int spp = subpage_protection(mm, ea); |
fa28237c PM |
1408 | if (access & spp) |
1409 | rc = -2; | |
1410 | else | |
1411 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, | |
aefa5688 | 1412 | flags, ssize, spp); |
fa28237c | 1413 | } |
3c726f8d | 1414 | |
4b8692c0 BH |
1415 | /* Dump some info in case of hash insertion failure, they should |
1416 | * never happen so it is really useful to know if/when they do | |
1417 | */ | |
1418 | if (rc == -1) | |
1419 | hash_failure_debug(ea, access, vsid, trap, ssize, psize, | |
d8139ebf | 1420 | psize, pte_val(*ptep)); |
3c726f8d BH |
1421 | #ifndef CONFIG_PPC_64K_PAGES |
1422 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
1423 | #else | |
1424 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
1425 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1426 | #endif | |
1427 | DBG_LOW(" -> rc=%d\n", rc); | |
ba12eede LZ |
1428 | |
1429 | bail: | |
1430 | exception_exit(prev_state); | |
3c726f8d | 1431 | return rc; |
1da177e4 | 1432 | } |
a1dca346 IM |
1433 | EXPORT_SYMBOL_GPL(hash_page_mm); |
1434 | ||
aefa5688 AK |
1435 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap, |
1436 | unsigned long dsisr) | |
a1dca346 | 1437 | { |
aefa5688 | 1438 | unsigned long flags = 0; |
a1dca346 IM |
1439 | struct mm_struct *mm = current->mm; |
1440 | ||
0034d395 AK |
1441 | if ((get_region_id(ea) == VMALLOC_REGION_ID) || |
1442 | (get_region_id(ea) == IO_REGION_ID)) | |
a1dca346 IM |
1443 | mm = &init_mm; |
1444 | ||
aefa5688 AK |
1445 | if (dsisr & DSISR_NOHPTE) |
1446 | flags |= HPTE_NOHPTE_UPDATE; | |
1447 | ||
1448 | return hash_page_mm(mm, ea, access, trap, flags); | |
a1dca346 | 1449 | } |
67207b96 | 1450 | EXPORT_SYMBOL_GPL(hash_page); |
1da177e4 | 1451 | |
106713a1 AK |
1452 | int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap, |
1453 | unsigned long dsisr) | |
1454 | { | |
c7d54842 | 1455 | unsigned long access = _PAGE_PRESENT | _PAGE_READ; |
106713a1 AK |
1456 | unsigned long flags = 0; |
1457 | struct mm_struct *mm = current->mm; | |
0034d395 | 1458 | unsigned int region_id = get_region_id(ea); |
106713a1 | 1459 | |
0034d395 | 1460 | if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID)) |
106713a1 AK |
1461 | mm = &init_mm; |
1462 | ||
1463 | if (dsisr & DSISR_NOHPTE) | |
1464 | flags |= HPTE_NOHPTE_UPDATE; | |
1465 | ||
1466 | if (dsisr & DSISR_ISSTORE) | |
c7d54842 | 1467 | access |= _PAGE_WRITE; |
106713a1 | 1468 | /* |
ac29c640 AK |
1469 | * We set _PAGE_PRIVILEGED only when |
1470 | * kernel mode access kernel space. | |
1471 | * | |
1472 | * _PAGE_PRIVILEGED is NOT set | |
1473 | * 1) when kernel mode access user space | |
1474 | * 2) user space access kernel space. | |
106713a1 | 1475 | */ |
ac29c640 | 1476 | access |= _PAGE_PRIVILEGED; |
0034d395 | 1477 | if ((msr & MSR_PR) || (region_id == USER_REGION_ID)) |
ac29c640 | 1478 | access &= ~_PAGE_PRIVILEGED; |
106713a1 AK |
1479 | |
1480 | if (trap == 0x400) | |
1481 | access |= _PAGE_EXEC; | |
1482 | ||
1483 | return hash_page_mm(mm, ea, access, trap, flags); | |
1484 | } | |
1485 | ||
8bbc9b7b ME |
1486 | #ifdef CONFIG_PPC_MM_SLICES |
1487 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1488 | { | |
54be0b9c | 1489 | int psize = get_slice_psize(mm, ea); |
aac55d75 | 1490 | |
8bbc9b7b | 1491 | /* We only prefault standard pages for now */ |
60458fba | 1492 | if (unlikely(psize != mm_ctx_user_psize(&mm->context))) |
aac55d75 ME |
1493 | return false; |
1494 | ||
1495 | /* | |
1496 | * Don't prefault if subpage protection is enabled for the EA. | |
1497 | */ | |
1498 | if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea))) | |
8bbc9b7b ME |
1499 | return false; |
1500 | ||
1501 | return true; | |
1502 | } | |
1503 | #else | |
1504 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1505 | { | |
1506 | return true; | |
1507 | } | |
1508 | #endif | |
1509 | ||
3c726f8d | 1510 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
34eb138e | 1511 | bool is_exec, unsigned long trap) |
1da177e4 | 1512 | { |
12bc9f6f | 1513 | int hugepage_shift; |
3c726f8d | 1514 | unsigned long vsid; |
0b97fee0 | 1515 | pgd_t *pgdir; |
3c726f8d | 1516 | pte_t *ptep; |
3c726f8d | 1517 | unsigned long flags; |
aefa5688 | 1518 | int rc, ssize, update_flags = 0; |
34eb138e | 1519 | unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0); |
3c726f8d | 1520 | |
0034d395 | 1521 | BUG_ON(get_region_id(ea) != USER_REGION_ID); |
d0f13e3c | 1522 | |
8bbc9b7b | 1523 | if (!should_hash_preload(mm, ea)) |
3c726f8d BH |
1524 | return; |
1525 | ||
1526 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
1527 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 1528 | |
16f1c746 | 1529 | /* Get Linux PTE if available */ |
3c726f8d BH |
1530 | pgdir = mm->pgd; |
1531 | if (pgdir == NULL) | |
1532 | return; | |
0ac52dd7 AK |
1533 | |
1534 | /* Get VSID */ | |
1535 | ssize = user_segment_size(ea); | |
f384796c | 1536 | vsid = get_user_vsid(&mm->context, ea, ssize); |
0ac52dd7 AK |
1537 | if (!vsid) |
1538 | return; | |
1539 | /* | |
1540 | * Hash doesn't like irqs. Walking linux page table with irq disabled | |
1541 | * saves us from holding multiple locks. | |
1542 | */ | |
1543 | local_irq_save(flags); | |
1544 | ||
12bc9f6f AK |
1545 | /* |
1546 | * THP pages use update_mmu_cache_pmd. We don't do | |
1547 | * hash preload there. Hence can ignore THP here | |
1548 | */ | |
94171b19 | 1549 | ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift); |
3c726f8d | 1550 | if (!ptep) |
0ac52dd7 | 1551 | goto out_exit; |
16f1c746 | 1552 | |
12bc9f6f | 1553 | WARN_ON(hugepage_shift); |
16f1c746 | 1554 | #ifdef CONFIG_PPC_64K_PAGES |
945537df | 1555 | /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on |
16f1c746 BH |
1556 | * a 64K kernel), then we don't preload, hash_page() will take |
1557 | * care of it once we actually try to access the page. | |
1558 | * That way we don't have to duplicate all of the logic for segment | |
1559 | * page size demotion here | |
1560 | */ | |
945537df | 1561 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep)) |
0ac52dd7 | 1562 | goto out_exit; |
16f1c746 BH |
1563 | #endif /* CONFIG_PPC_64K_PAGES */ |
1564 | ||
16c2d476 | 1565 | /* Is that local to this CPU ? */ |
b426e4bd | 1566 | if (mm_is_thread_local(mm)) |
aefa5688 | 1567 | update_flags |= HPTE_LOCAL_UPDATE; |
16c2d476 BH |
1568 | |
1569 | /* Hash it in */ | |
73b341ef | 1570 | #ifdef CONFIG_PPC_64K_PAGES |
60458fba | 1571 | if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K) |
aefa5688 AK |
1572 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1573 | update_flags, ssize); | |
1da177e4 | 1574 | else |
73b341ef | 1575 | #endif /* CONFIG_PPC_64K_PAGES */ |
aefa5688 AK |
1576 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags, |
1577 | ssize, subpage_protection(mm, ea)); | |
4b8692c0 BH |
1578 | |
1579 | /* Dump some info in case of hash insertion failure, they should | |
1580 | * never happen so it is really useful to know if/when they do | |
1581 | */ | |
1582 | if (rc == -1) | |
1583 | hash_failure_debug(ea, access, vsid, trap, ssize, | |
60458fba AK |
1584 | mm_ctx_user_psize(&mm->context), |
1585 | mm_ctx_user_psize(&mm->context), | |
d8139ebf | 1586 | pte_val(*ptep)); |
0ac52dd7 | 1587 | out_exit: |
3c726f8d BH |
1588 | local_irq_restore(flags); |
1589 | } | |
1590 | ||
087003e9 RP |
1591 | #ifdef CONFIG_PPC_MEM_KEYS |
1592 | /* | |
1593 | * Return the protection key associated with the given address and the | |
1594 | * mm_struct. | |
1595 | */ | |
1596 | u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address) | |
1597 | { | |
1598 | pte_t *ptep; | |
1599 | u16 pkey = 0; | |
1600 | unsigned long flags; | |
1601 | ||
1602 | if (!mm || !mm->pgd) | |
1603 | return 0; | |
1604 | ||
1605 | local_irq_save(flags); | |
1606 | ptep = find_linux_pte(mm->pgd, address, NULL, NULL); | |
1607 | if (ptep) | |
1608 | pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep))); | |
1609 | local_irq_restore(flags); | |
1610 | ||
1611 | return pkey; | |
1612 | } | |
1613 | #endif /* CONFIG_PPC_MEM_KEYS */ | |
1614 | ||
f1a55ce0 RT |
1615 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1616 | static inline void tm_flush_hash_page(int local) | |
1617 | { | |
1618 | /* | |
1619 | * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a | |
1620 | * page back to a block device w/PIO could pick up transactional data | |
1621 | * (bad!) so we force an abort here. Before the sync the page will be | |
1622 | * made read-only, which will flush_hash_page. BIG ISSUE here: if the | |
1623 | * kernel uses a page from userspace without unmapping it first, it may | |
1624 | * see the speculated version. | |
1625 | */ | |
1626 | if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs && | |
1627 | MSR_TM_ACTIVE(current->thread.regs->msr)) { | |
1628 | tm_enable(); | |
1629 | tm_abort(TM_CAUSE_TLBI); | |
1630 | } | |
1631 | } | |
1632 | #else | |
1633 | static inline void tm_flush_hash_page(int local) | |
1634 | { | |
1635 | } | |
1636 | #endif | |
1637 | ||
318995b4 RP |
1638 | /* |
1639 | * Return the global hash slot, corresponding to the given PTE, which contains | |
1640 | * the HPTE. | |
1641 | */ | |
1642 | unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift, | |
1643 | int ssize, real_pte_t rpte, unsigned int subpg_index) | |
1644 | { | |
1645 | unsigned long hash, gslot, hidx; | |
1646 | ||
1647 | hash = hpt_hash(vpn, shift, ssize); | |
1648 | hidx = __rpte_to_hidx(rpte, subpg_index); | |
1649 | if (hidx & _PTEIDX_SECONDARY) | |
1650 | hash = ~hash; | |
1651 | gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1652 | gslot += hidx & _PTEIDX_GROUP_IX; | |
1653 | return gslot; | |
1654 | } | |
1655 | ||
f6ab0b92 BH |
1656 | /* WARNING: This is called from hash_low_64.S, if you change this prototype, |
1657 | * do not forget to update the assembly call site ! | |
1658 | */ | |
5524a27d | 1659 | void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize, |
aefa5688 | 1660 | unsigned long flags) |
3c726f8d | 1661 | { |
a8548686 | 1662 | unsigned long index, shift, gslot; |
aefa5688 | 1663 | int local = flags & HPTE_LOCAL_UPDATE; |
3c726f8d | 1664 | |
5524a27d AK |
1665 | DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn); |
1666 | pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { | |
a8548686 RP |
1667 | gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index); |
1668 | DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot); | |
db3d8534 AK |
1669 | /* |
1670 | * We use same base page size and actual psize, because we don't | |
1671 | * use these functions for hugepage | |
1672 | */ | |
a8548686 | 1673 | mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize, |
7025776e | 1674 | ssize, local); |
3c726f8d | 1675 | } pte_iterate_hashed_end(); |
bc2a9408 | 1676 | |
f1a55ce0 | 1677 | tm_flush_hash_page(local); |
1da177e4 LT |
1678 | } |
1679 | ||
f1581bf1 AK |
1680 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1681 | void flush_hash_hugepage(unsigned long vsid, unsigned long addr, | |
aefa5688 AK |
1682 | pmd_t *pmdp, unsigned int psize, int ssize, |
1683 | unsigned long flags) | |
f1581bf1 AK |
1684 | { |
1685 | int i, max_hpte_count, valid; | |
1686 | unsigned long s_addr; | |
1687 | unsigned char *hpte_slot_array; | |
1688 | unsigned long hidx, shift, vpn, hash, slot; | |
aefa5688 | 1689 | int local = flags & HPTE_LOCAL_UPDATE; |
f1581bf1 AK |
1690 | |
1691 | s_addr = addr & HPAGE_PMD_MASK; | |
1692 | hpte_slot_array = get_hpte_slot_array(pmdp); | |
1693 | /* | |
1694 | * IF we try to do a HUGE PTE update after a withdraw is done. | |
1695 | * we will find the below NULL. This happens when we do | |
1696 | * split_huge_page_pmd | |
1697 | */ | |
1698 | if (!hpte_slot_array) | |
1699 | return; | |
1700 | ||
7025776e BH |
1701 | if (mmu_hash_ops.hugepage_invalidate) { |
1702 | mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array, | |
1703 | psize, ssize, local); | |
d557b098 AK |
1704 | goto tm_abort; |
1705 | } | |
f1581bf1 AK |
1706 | /* |
1707 | * No bluk hpte removal support, invalidate each entry | |
1708 | */ | |
1709 | shift = mmu_psize_defs[psize].shift; | |
1710 | max_hpte_count = HPAGE_PMD_SIZE >> shift; | |
1711 | for (i = 0; i < max_hpte_count; i++) { | |
1712 | /* | |
1713 | * 8 bits per each hpte entries | |
1714 | * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit] | |
1715 | */ | |
1716 | valid = hpte_valid(hpte_slot_array, i); | |
1717 | if (!valid) | |
1718 | continue; | |
1719 | hidx = hpte_hash_index(hpte_slot_array, i); | |
1720 | ||
1721 | /* get the vpn */ | |
1722 | addr = s_addr + (i * (1ul << shift)); | |
1723 | vpn = hpt_vpn(addr, vsid, ssize); | |
1724 | hash = hpt_hash(vpn, shift, ssize); | |
1725 | if (hidx & _PTEIDX_SECONDARY) | |
1726 | hash = ~hash; | |
1727 | ||
1728 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1729 | slot += hidx & _PTEIDX_GROUP_IX; | |
7025776e BH |
1730 | mmu_hash_ops.hpte_invalidate(slot, vpn, psize, |
1731 | MMU_PAGE_16M, ssize, local); | |
d557b098 AK |
1732 | } |
1733 | tm_abort: | |
f1a55ce0 | 1734 | tm_flush_hash_page(local); |
f1581bf1 AK |
1735 | } |
1736 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1737 | ||
61b1a942 | 1738 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 1739 | { |
7025776e BH |
1740 | if (mmu_hash_ops.flush_hash_range) |
1741 | mmu_hash_ops.flush_hash_range(number, local); | |
3c726f8d | 1742 | else { |
1da177e4 | 1743 | int i; |
61b1a942 | 1744 | struct ppc64_tlb_batch *batch = |
69111bac | 1745 | this_cpu_ptr(&ppc64_tlb_batch); |
1da177e4 LT |
1746 | |
1747 | for (i = 0; i < number; i++) | |
5524a27d | 1748 | flush_hash_page(batch->vpn[i], batch->pte[i], |
1189be65 | 1749 | batch->psize, batch->ssize, local); |
1da177e4 LT |
1750 | } |
1751 | } | |
1752 | ||
1da177e4 LT |
1753 | /* |
1754 | * low_hash_fault is called when we the low level hash code failed | |
1755 | * to instert a PTE due to an hypervisor error | |
1756 | */ | |
fa28237c | 1757 | void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) |
1da177e4 | 1758 | { |
ba12eede LZ |
1759 | enum ctx_state prev_state = exception_enter(); |
1760 | ||
1da177e4 | 1761 | if (user_mode(regs)) { |
fa28237c PM |
1762 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1763 | if (rc == -2) | |
1764 | _exception(SIGSEGV, regs, SEGV_ACCERR, address); | |
1765 | else | |
1766 | #endif | |
1767 | _exception(SIGBUS, regs, BUS_ADRERR, address); | |
1768 | } else | |
1769 | bad_page_fault(regs, address, SIGBUS); | |
ba12eede LZ |
1770 | |
1771 | exception_exit(prev_state); | |
1da177e4 | 1772 | } |
370a908d | 1773 | |
b170bd3d LZ |
1774 | long hpte_insert_repeating(unsigned long hash, unsigned long vpn, |
1775 | unsigned long pa, unsigned long rflags, | |
1776 | unsigned long vflags, int psize, int ssize) | |
1777 | { | |
1778 | unsigned long hpte_group; | |
1779 | long slot; | |
1780 | ||
1781 | repeat: | |
1531cff4 | 1782 | hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP; |
b170bd3d LZ |
1783 | |
1784 | /* Insert into the hash table, primary slot */ | |
7025776e BH |
1785 | slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags, |
1786 | psize, psize, ssize); | |
b170bd3d LZ |
1787 | |
1788 | /* Primary is full, try the secondary */ | |
1789 | if (unlikely(slot == -1)) { | |
1531cff4 | 1790 | hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP; |
7025776e BH |
1791 | slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, |
1792 | vflags | HPTE_V_SECONDARY, | |
1793 | psize, psize, ssize); | |
b170bd3d LZ |
1794 | if (slot == -1) { |
1795 | if (mftb() & 0x1) | |
1531cff4 AK |
1796 | hpte_group = (hash & htab_hash_mask) * |
1797 | HPTES_PER_GROUP; | |
b170bd3d | 1798 | |
7025776e | 1799 | mmu_hash_ops.hpte_remove(hpte_group); |
b170bd3d LZ |
1800 | goto repeat; |
1801 | } | |
1802 | } | |
1803 | ||
1804 | return slot; | |
1805 | } | |
1806 | ||
370a908d BH |
1807 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1808 | static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) | |
1809 | { | |
016af59f | 1810 | unsigned long hash; |
1189be65 | 1811 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); |
5524a27d | 1812 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
09f3f326 | 1813 | unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL)); |
016af59f | 1814 | long ret; |
370a908d | 1815 | |
5524a27d | 1816 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d | 1817 | |
c60ac569 AK |
1818 | /* Don't create HPTE entries for bad address */ |
1819 | if (!vsid) | |
1820 | return; | |
016af59f LZ |
1821 | |
1822 | ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, | |
1823 | HPTE_V_BOLTED, | |
1824 | mmu_linear_psize, mmu_kernel_ssize); | |
1825 | ||
370a908d BH |
1826 | BUG_ON (ret < 0); |
1827 | spin_lock(&linear_map_hash_lock); | |
1828 | BUG_ON(linear_map_hash_slots[lmi] & 0x80); | |
1829 | linear_map_hash_slots[lmi] = ret | 0x80; | |
1830 | spin_unlock(&linear_map_hash_lock); | |
1831 | } | |
1832 | ||
1833 | static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) | |
1834 | { | |
1189be65 PM |
1835 | unsigned long hash, hidx, slot; |
1836 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
5524a27d | 1837 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
370a908d | 1838 | |
5524a27d | 1839 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1840 | spin_lock(&linear_map_hash_lock); |
1841 | BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); | |
1842 | hidx = linear_map_hash_slots[lmi] & 0x7f; | |
1843 | linear_map_hash_slots[lmi] = 0; | |
1844 | spin_unlock(&linear_map_hash_lock); | |
1845 | if (hidx & _PTEIDX_SECONDARY) | |
1846 | hash = ~hash; | |
1847 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1848 | slot += hidx & _PTEIDX_GROUP_IX; | |
7025776e BH |
1849 | mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize, |
1850 | mmu_linear_psize, | |
1851 | mmu_kernel_ssize, 0); | |
370a908d BH |
1852 | } |
1853 | ||
031bc574 | 1854 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
370a908d BH |
1855 | { |
1856 | unsigned long flags, vaddr, lmi; | |
1857 | int i; | |
1858 | ||
1859 | local_irq_save(flags); | |
1860 | for (i = 0; i < numpages; i++, page++) { | |
1861 | vaddr = (unsigned long)page_address(page); | |
1862 | lmi = __pa(vaddr) >> PAGE_SHIFT; | |
1863 | if (lmi >= linear_map_hash_count) | |
1864 | continue; | |
1865 | if (enable) | |
1866 | kernel_map_linear_page(vaddr, lmi); | |
1867 | else | |
1868 | kernel_unmap_linear_page(vaddr, lmi); | |
1869 | } | |
1870 | local_irq_restore(flags); | |
1871 | } | |
1872 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
cd3db0c4 | 1873 | |
756d08d1 | 1874 | void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, |
cd3db0c4 BH |
1875 | phys_addr_t first_memblock_size) |
1876 | { | |
1877 | /* We don't currently support the first MEMBLOCK not mapping 0 | |
1878 | * physical on those processors | |
1879 | */ | |
1880 | BUG_ON(first_memblock_base != 0); | |
1881 | ||
1513c33d NP |
1882 | /* |
1883 | * On virtualized systems the first entry is our RMA region aka VRMA, | |
1884 | * non-virtualized 64-bit hash MMU systems don't have a limitation | |
1885 | * on real mode access. | |
1886 | * | |
c610d65c NP |
1887 | * For guests on platforms before POWER9, we clamp the it limit to 1G |
1888 | * to avoid some funky things such as RTAS bugs etc... | |
cd3db0c4 | 1889 | */ |
1513c33d | 1890 | if (!early_cpu_has_feature(CPU_FTR_HVMODE)) { |
c610d65c NP |
1891 | ppc64_rma_size = first_memblock_size; |
1892 | if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) | |
1893 | ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000); | |
cd3db0c4 | 1894 | |
1513c33d NP |
1895 | /* Finally limit subsequent allocations */ |
1896 | memblock_set_current_limit(ppc64_rma_size); | |
1897 | } else { | |
1898 | ppc64_rma_size = ULONG_MAX; | |
1899 | } | |
cd3db0c4 | 1900 | } |
dbcf929c DG |
1901 | |
1902 | #ifdef CONFIG_DEBUG_FS | |
1903 | ||
1904 | static int hpt_order_get(void *data, u64 *val) | |
1905 | { | |
1906 | *val = ppc64_pft_size; | |
1907 | return 0; | |
1908 | } | |
1909 | ||
1910 | static int hpt_order_set(void *data, u64 val) | |
1911 | { | |
1912 | if (!mmu_hash_ops.resize_hpt) | |
1913 | return -ENODEV; | |
1914 | ||
1915 | return mmu_hash_ops.resize_hpt(val); | |
1916 | } | |
1917 | ||
7cd4774f | 1918 | DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n"); |
dbcf929c DG |
1919 | |
1920 | static int __init hash64_debugfs(void) | |
1921 | { | |
7cd4774f Y |
1922 | if (!debugfs_create_file_unsafe("hpt_order", 0600, powerpc_debugfs_root, |
1923 | NULL, &fops_hpt_order)) { | |
dbcf929c DG |
1924 | pr_err("lpar: unable to create hpt_order debugsfs file\n"); |
1925 | } | |
1926 | ||
1927 | return 0; | |
1928 | } | |
1929 | machine_device_initcall(pseries, hash64_debugfs); | |
dbcf929c | 1930 | #endif /* CONFIG_DEBUG_FS */ |