Commit | Line | Data |
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40ef8cbc PM |
1 | /* |
2 | * | |
3 | * Common boot and setup code. | |
4 | * | |
5 | * Copyright (C) 2001 PPC64 Team, IBM Corp | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
7191b615 | 13 | #define DEBUG |
40ef8cbc | 14 | |
4b16f8e2 | 15 | #include <linux/export.h> |
40ef8cbc PM |
16 | #include <linux/string.h> |
17 | #include <linux/sched.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/reboot.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/initrd.h> | |
40ef8cbc PM |
23 | #include <linux/seq_file.h> |
24 | #include <linux/ioport.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/utsname.h> | |
27 | #include <linux/tty.h> | |
28 | #include <linux/root_dev.h> | |
29 | #include <linux/notifier.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/unistd.h> | |
32 | #include <linux/serial.h> | |
33 | #include <linux/serial_8250.h> | |
7a0268fa | 34 | #include <linux/bootmem.h> |
12d04eef | 35 | #include <linux/pci.h> |
945feb17 | 36 | #include <linux/lockdep.h> |
95f72d1e | 37 | #include <linux/memblock.h> |
a6146888 | 38 | #include <linux/hugetlb.h> |
a5d86257 | 39 | #include <linux/memory.h> |
c54b2bf1 | 40 | #include <linux/nmi.h> |
a6146888 | 41 | |
40ef8cbc | 42 | #include <asm/io.h> |
0cc4746c | 43 | #include <asm/kdump.h> |
40ef8cbc PM |
44 | #include <asm/prom.h> |
45 | #include <asm/processor.h> | |
46 | #include <asm/pgtable.h> | |
40ef8cbc PM |
47 | #include <asm/smp.h> |
48 | #include <asm/elf.h> | |
49 | #include <asm/machdep.h> | |
50 | #include <asm/paca.h> | |
40ef8cbc PM |
51 | #include <asm/time.h> |
52 | #include <asm/cputable.h> | |
53 | #include <asm/sections.h> | |
54 | #include <asm/btext.h> | |
55 | #include <asm/nvram.h> | |
56 | #include <asm/setup.h> | |
40ef8cbc PM |
57 | #include <asm/rtas.h> |
58 | #include <asm/iommu.h> | |
59 | #include <asm/serial.h> | |
60 | #include <asm/cache.h> | |
61 | #include <asm/page.h> | |
62 | #include <asm/mmu.h> | |
40ef8cbc | 63 | #include <asm/firmware.h> |
f78541dc | 64 | #include <asm/xmon.h> |
dcad47fc | 65 | #include <asm/udbg.h> |
593e537b | 66 | #include <asm/kexec.h> |
25d21ad6 | 67 | #include <asm/mmu_context.h> |
d36b4c4f | 68 | #include <asm/code-patching.h> |
aa04b4cc | 69 | #include <asm/kvm_ppc.h> |
a6146888 | 70 | #include <asm/hugetlb.h> |
5d31a96e | 71 | #include <asm/livepatch.h> |
d3cbff1b | 72 | #include <asm/opal.h> |
40ef8cbc PM |
73 | |
74 | #ifdef DEBUG | |
75 | #define DBG(fmt...) udbg_printf(fmt) | |
76 | #else | |
77 | #define DBG(fmt...) | |
78 | #endif | |
79 | ||
8246aca7 | 80 | int spinning_secondaries; |
40ef8cbc PM |
81 | u64 ppc64_pft_size; |
82 | ||
dabcafd3 OJ |
83 | /* Pick defaults since we might want to patch instructions |
84 | * before we've read this from the device tree. | |
85 | */ | |
86 | struct ppc64_caches ppc64_caches = { | |
5a2fe38d OJ |
87 | .dline_size = 0x40, |
88 | .log_dline_size = 6, | |
89 | .iline_size = 0x40, | |
90 | .log_iline_size = 6 | |
dabcafd3 | 91 | }; |
40ef8cbc PM |
92 | EXPORT_SYMBOL_GPL(ppc64_caches); |
93 | ||
94 | /* | |
95 | * These are used in binfmt_elf.c to put aux entries on the stack | |
96 | * for each elf executable being started. | |
97 | */ | |
98 | int dcache_bsize; | |
99 | int icache_bsize; | |
100 | int ucache_bsize; | |
101 | ||
28efc35f SW |
102 | #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) |
103 | static void setup_tlb_core_data(void) | |
104 | { | |
105 | int cpu; | |
106 | ||
82d86de2 SW |
107 | BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); |
108 | ||
28efc35f SW |
109 | for_each_possible_cpu(cpu) { |
110 | int first = cpu_first_thread_sibling(cpu); | |
111 | ||
d9e1831a SW |
112 | /* |
113 | * If we boot via kdump on a non-primary thread, | |
114 | * make sure we point at the thread that actually | |
115 | * set up this TLB. | |
116 | */ | |
117 | if (cpu_first_thread_sibling(boot_cpuid) == first) | |
118 | first = boot_cpuid; | |
119 | ||
28efc35f SW |
120 | paca[cpu].tcd_ptr = &paca[first].tcd; |
121 | ||
122 | /* | |
123 | * If we have threads, we need either tlbsrx. | |
124 | * or e6500 tablewalk mode, or else TLB handlers | |
125 | * will be racy and could produce duplicate entries. | |
126 | */ | |
127 | if (smt_enabled_at_boot >= 2 && | |
128 | !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && | |
129 | book3e_htw_mode != PPC_HTW_E6500) { | |
130 | /* Should we panic instead? */ | |
131 | WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n", | |
132 | __func__); | |
133 | } | |
134 | } | |
135 | } | |
136 | #else | |
137 | static void setup_tlb_core_data(void) | |
138 | { | |
139 | } | |
140 | #endif | |
141 | ||
40ef8cbc PM |
142 | #ifdef CONFIG_SMP |
143 | ||
954e6da5 | 144 | static char *smt_enabled_cmdline; |
40ef8cbc PM |
145 | |
146 | /* Look for ibm,smt-enabled OF option */ | |
147 | static void check_smt_enabled(void) | |
148 | { | |
149 | struct device_node *dn; | |
a7f67bdf | 150 | const char *smt_option; |
40ef8cbc | 151 | |
954e6da5 NF |
152 | /* Default to enabling all threads */ |
153 | smt_enabled_at_boot = threads_per_core; | |
40ef8cbc | 154 | |
954e6da5 NF |
155 | /* Allow the command line to overrule the OF option */ |
156 | if (smt_enabled_cmdline) { | |
157 | if (!strcmp(smt_enabled_cmdline, "on")) | |
158 | smt_enabled_at_boot = threads_per_core; | |
159 | else if (!strcmp(smt_enabled_cmdline, "off")) | |
160 | smt_enabled_at_boot = 0; | |
161 | else { | |
1618bd53 | 162 | int smt; |
954e6da5 NF |
163 | int rc; |
164 | ||
1618bd53 | 165 | rc = kstrtoint(smt_enabled_cmdline, 10, &smt); |
954e6da5 NF |
166 | if (!rc) |
167 | smt_enabled_at_boot = | |
1618bd53 | 168 | min(threads_per_core, smt); |
954e6da5 NF |
169 | } |
170 | } else { | |
171 | dn = of_find_node_by_path("/options"); | |
172 | if (dn) { | |
173 | smt_option = of_get_property(dn, "ibm,smt-enabled", | |
174 | NULL); | |
175 | ||
176 | if (smt_option) { | |
177 | if (!strcmp(smt_option, "on")) | |
178 | smt_enabled_at_boot = threads_per_core; | |
179 | else if (!strcmp(smt_option, "off")) | |
180 | smt_enabled_at_boot = 0; | |
181 | } | |
182 | ||
183 | of_node_put(dn); | |
184 | } | |
185 | } | |
40ef8cbc PM |
186 | } |
187 | ||
188 | /* Look for smt-enabled= cmdline option */ | |
189 | static int __init early_smt_enabled(char *p) | |
190 | { | |
954e6da5 | 191 | smt_enabled_cmdline = p; |
40ef8cbc PM |
192 | return 0; |
193 | } | |
194 | early_param("smt-enabled", early_smt_enabled); | |
195 | ||
5ad57078 PM |
196 | #else |
197 | #define check_smt_enabled() | |
40ef8cbc PM |
198 | #endif /* CONFIG_SMP */ |
199 | ||
25e13814 ME |
200 | /** Fix up paca fields required for the boot cpu */ |
201 | static void fixup_boot_paca(void) | |
202 | { | |
203 | /* The boot cpu is started */ | |
204 | get_paca()->cpu_start = 1; | |
205 | /* Allow percpu accesses to work until we setup percpu data */ | |
206 | get_paca()->data_offset = 0; | |
207 | } | |
208 | ||
d3cbff1b | 209 | static void configure_exceptions(void) |
8f619b54 | 210 | { |
633440f1 | 211 | /* |
d3cbff1b BH |
212 | * Setup the trampolines from the lowmem exception vectors |
213 | * to the kdump kernel when not using a relocatable kernel. | |
633440f1 | 214 | */ |
d3cbff1b BH |
215 | setup_kdump_trampoline(); |
216 | ||
217 | /* Under a PAPR hypervisor, we need hypercalls */ | |
218 | if (firmware_has_feature(FW_FEATURE_SET_MODE)) { | |
219 | /* Enable AIL if possible */ | |
220 | pseries_enable_reloc_on_exc(); | |
221 | ||
222 | /* | |
223 | * Tell the hypervisor that we want our exceptions to | |
224 | * be taken in little endian mode. | |
225 | * | |
226 | * We don't call this for big endian as our calling convention | |
227 | * makes us always enter in BE, and the call may fail under | |
228 | * some circumstances with kdump. | |
229 | */ | |
230 | #ifdef __LITTLE_ENDIAN__ | |
231 | pseries_little_endian_exceptions(); | |
232 | #endif | |
233 | } else { | |
234 | /* Set endian mode using OPAL */ | |
235 | if (firmware_has_feature(FW_FEATURE_OPAL)) | |
236 | opal_configure_cores(); | |
237 | ||
238 | /* Enable AIL if supported, and we are in hypervisor mode */ | |
239 | if (cpu_has_feature(CPU_FTR_HVMODE) && | |
240 | cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
241 | unsigned long lpcr = mfspr(SPRN_LPCR); | |
242 | mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); | |
243 | } | |
8f619b54 BH |
244 | } |
245 | } | |
246 | ||
d3cbff1b BH |
247 | static void cpu_ready_for_interrupts(void) |
248 | { | |
249 | /* Set IR and DR in PACA MSR */ | |
250 | get_paca()->kernel_msr = MSR_KERNEL; | |
251 | } | |
252 | ||
40ef8cbc PM |
253 | /* |
254 | * Early initialization entry point. This is called by head.S | |
255 | * with MMU translation disabled. We rely on the "feature" of | |
256 | * the CPU that ignores the top 2 bits of the address in real | |
257 | * mode so we can access kernel globals normally provided we | |
258 | * only toy with things in the RMO region. From here, we do | |
95f72d1e | 259 | * some early parsing of the device-tree to setup out MEMBLOCK |
40ef8cbc PM |
260 | * data structures, and allocate & initialize the hash table |
261 | * and segment tables so we can start running with translation | |
262 | * enabled. | |
263 | * | |
264 | * It is this function which will call the probe() callback of | |
265 | * the various platform types and copy the matching one to the | |
266 | * global ppc_md structure. Your platform can eventually do | |
267 | * some very early initializations from the probe() routine, but | |
268 | * this is not recommended, be very careful as, for example, the | |
269 | * device-tree is not accessible via normal means at this point. | |
270 | */ | |
271 | ||
272 | void __init early_setup(unsigned long dt_ptr) | |
273 | { | |
6a7e4064 GL |
274 | static __initdata struct paca_struct boot_paca; |
275 | ||
24d96495 BH |
276 | /* -------- printk is _NOT_ safe to use here ! ------- */ |
277 | ||
42c4aaad | 278 | /* Identify CPU type */ |
974a76f5 | 279 | identify_cpu(0, mfspr(SPRN_PVR)); |
42c4aaad | 280 | |
33dbcf72 | 281 | /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ |
1426d5a3 ME |
282 | initialise_paca(&boot_paca, 0); |
283 | setup_paca(&boot_paca); | |
25e13814 | 284 | fixup_boot_paca(); |
33dbcf72 | 285 | |
24d96495 BH |
286 | /* -------- printk is now safe to use ------- */ |
287 | ||
f2fd2513 BH |
288 | /* Enable early debugging if any specified (see udbg.h) */ |
289 | udbg_early_init(); | |
290 | ||
e8222502 | 291 | DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); |
40ef8cbc | 292 | |
40ef8cbc | 293 | /* |
3c607ce2 LV |
294 | * Do early initialization using the flattened device |
295 | * tree, such as retrieving the physical memory map or | |
296 | * calculating/retrieving the hash table size. | |
40ef8cbc PM |
297 | */ |
298 | early_init_devtree(__va(dt_ptr)); | |
299 | ||
4df20460 | 300 | /* Now we know the logical id of our boot cpu, setup the paca. */ |
1426d5a3 | 301 | setup_paca(&paca[boot_cpuid]); |
25e13814 | 302 | fixup_boot_paca(); |
4df20460 | 303 | |
63c254a5 | 304 | /* |
d3cbff1b BH |
305 | * Configure exception handlers. This include setting up trampolines |
306 | * if needed, setting exception endian mode, etc... | |
63c254a5 | 307 | */ |
d3cbff1b | 308 | configure_exceptions(); |
0cc4746c | 309 | |
757c74d2 BH |
310 | /* Initialize the hash table or TLB handling */ |
311 | early_init_mmu(); | |
40ef8cbc | 312 | |
c4bd6cb8 BH |
313 | /* Apply all the dynamic patching */ |
314 | apply_feature_fixups(); | |
315 | ||
a944a9c4 BH |
316 | /* |
317 | * At this point, we can let interrupts switch to virtual mode | |
318 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
8f619b54 | 319 | * have IR and DR set and enable AIL if it exists |
a944a9c4 | 320 | */ |
8f619b54 | 321 | cpu_ready_for_interrupts(); |
a944a9c4 | 322 | |
40ef8cbc | 323 | DBG(" <- early_setup()\n"); |
7191b615 BH |
324 | |
325 | #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX | |
326 | /* | |
327 | * This needs to be done *last* (after the above DBG() even) | |
328 | * | |
329 | * Right after we return from this function, we turn on the MMU | |
330 | * which means the real-mode access trick that btext does will | |
331 | * no longer work, it needs to switch to using a real MMU | |
332 | * mapping. This call will ensure that it does | |
333 | */ | |
334 | btext_map(); | |
335 | #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ | |
40ef8cbc PM |
336 | } |
337 | ||
799d6046 PM |
338 | #ifdef CONFIG_SMP |
339 | void early_setup_secondary(void) | |
340 | { | |
103b7827 | 341 | /* Mark interrupts disabled in PACA */ |
757c74d2 | 342 | get_paca()->soft_enabled = 0; |
799d6046 | 343 | |
757c74d2 BH |
344 | /* Initialize the hash table or TLB handling */ |
345 | early_init_mmu_secondary(); | |
a944a9c4 BH |
346 | |
347 | /* | |
348 | * At this point, we can let interrupts switch to virtual mode | |
349 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
350 | * have IR and DR set. | |
351 | */ | |
8f619b54 | 352 | cpu_ready_for_interrupts(); |
799d6046 PM |
353 | } |
354 | ||
355 | #endif /* CONFIG_SMP */ | |
40ef8cbc | 356 | |
b8f51021 | 357 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
567cf94d SW |
358 | static bool use_spinloop(void) |
359 | { | |
360 | if (!IS_ENABLED(CONFIG_PPC_BOOK3E)) | |
361 | return true; | |
362 | ||
363 | /* | |
364 | * When book3e boots from kexec, the ePAPR spin table does | |
365 | * not get used. | |
366 | */ | |
367 | return of_property_read_bool(of_chosen, "linux,booted-from-kexec"); | |
368 | } | |
369 | ||
b8f51021 ME |
370 | void smp_release_cpus(void) |
371 | { | |
758438a7 | 372 | unsigned long *ptr; |
9d07bc84 | 373 | int i; |
b8f51021 | 374 | |
567cf94d SW |
375 | if (!use_spinloop()) |
376 | return; | |
377 | ||
b8f51021 ME |
378 | DBG(" -> smp_release_cpus()\n"); |
379 | ||
380 | /* All secondary cpus are spinning on a common spinloop, release them | |
381 | * all now so they can start to spin on their individual paca | |
382 | * spinloops. For non SMP kernels, the secondary cpus never get out | |
383 | * of the common spinloop. | |
1f6a93e4 | 384 | */ |
b8f51021 | 385 | |
758438a7 ME |
386 | ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop |
387 | - PHYSICAL_START); | |
2751b628 | 388 | *ptr = ppc_function_entry(generic_secondary_smp_init); |
9d07bc84 BH |
389 | |
390 | /* And wait a bit for them to catch up */ | |
391 | for (i = 0; i < 100000; i++) { | |
392 | mb(); | |
393 | HMT_low(); | |
7ac87abb | 394 | if (spinning_secondaries == 0) |
9d07bc84 BH |
395 | break; |
396 | udelay(1); | |
397 | } | |
7ac87abb | 398 | DBG("spinning_secondaries = %d\n", spinning_secondaries); |
b8f51021 ME |
399 | |
400 | DBG(" <- smp_release_cpus()\n"); | |
401 | } | |
402 | #endif /* CONFIG_SMP || CONFIG_KEXEC */ | |
403 | ||
40ef8cbc | 404 | /* |
799d6046 PM |
405 | * Initialize some remaining members of the ppc64_caches and systemcfg |
406 | * structures | |
40ef8cbc PM |
407 | * (at least until we get rid of them completely). This is mostly some |
408 | * cache informations about the CPU that will be used by cache flush | |
409 | * routines and/or provided to userland | |
410 | */ | |
411 | static void __init initialize_cache_info(void) | |
412 | { | |
413 | struct device_node *np; | |
414 | unsigned long num_cpus = 0; | |
415 | ||
416 | DBG(" -> initialize_cache_info()\n"); | |
417 | ||
94db7c5e | 418 | for_each_node_by_type(np, "cpu") { |
40ef8cbc PM |
419 | num_cpus += 1; |
420 | ||
dfbe93a2 AB |
421 | /* |
422 | * We're assuming *all* of the CPUs have the same | |
40ef8cbc PM |
423 | * d-cache and i-cache sizes... -Peter |
424 | */ | |
dfbe93a2 | 425 | if (num_cpus == 1) { |
7946d5a5 | 426 | const __be32 *sizep, *lsizep; |
40ef8cbc | 427 | u32 size, lsize; |
40ef8cbc PM |
428 | |
429 | size = 0; | |
430 | lsize = cur_cpu_spec->dcache_bsize; | |
e2eb6392 | 431 | sizep = of_get_property(np, "d-cache-size", NULL); |
40ef8cbc | 432 | if (sizep != NULL) |
7946d5a5 | 433 | size = be32_to_cpu(*sizep); |
dfbe93a2 AB |
434 | lsizep = of_get_property(np, "d-cache-block-size", |
435 | NULL); | |
20474abd BH |
436 | /* fallback if block size missing */ |
437 | if (lsizep == NULL) | |
dfbe93a2 AB |
438 | lsizep = of_get_property(np, |
439 | "d-cache-line-size", | |
440 | NULL); | |
40ef8cbc | 441 | if (lsizep != NULL) |
7946d5a5 | 442 | lsize = be32_to_cpu(*lsizep); |
b0d436c7 | 443 | if (sizep == NULL || lsizep == NULL) |
40ef8cbc PM |
444 | DBG("Argh, can't find dcache properties ! " |
445 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
446 | ||
a7f290da BH |
447 | ppc64_caches.dsize = size; |
448 | ppc64_caches.dline_size = lsize; | |
40ef8cbc PM |
449 | ppc64_caches.log_dline_size = __ilog2(lsize); |
450 | ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; | |
451 | ||
452 | size = 0; | |
453 | lsize = cur_cpu_spec->icache_bsize; | |
e2eb6392 | 454 | sizep = of_get_property(np, "i-cache-size", NULL); |
40ef8cbc | 455 | if (sizep != NULL) |
7946d5a5 | 456 | size = be32_to_cpu(*sizep); |
dfbe93a2 AB |
457 | lsizep = of_get_property(np, "i-cache-block-size", |
458 | NULL); | |
20474abd | 459 | if (lsizep == NULL) |
dfbe93a2 AB |
460 | lsizep = of_get_property(np, |
461 | "i-cache-line-size", | |
462 | NULL); | |
40ef8cbc | 463 | if (lsizep != NULL) |
7946d5a5 | 464 | lsize = be32_to_cpu(*lsizep); |
b0d436c7 | 465 | if (sizep == NULL || lsizep == NULL) |
40ef8cbc PM |
466 | DBG("Argh, can't find icache properties ! " |
467 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
468 | ||
a7f290da BH |
469 | ppc64_caches.isize = size; |
470 | ppc64_caches.iline_size = lsize; | |
40ef8cbc PM |
471 | ppc64_caches.log_iline_size = __ilog2(lsize); |
472 | ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; | |
473 | } | |
474 | } | |
475 | ||
9df549af BH |
476 | /* For use by binfmt_elf */ |
477 | dcache_bsize = ppc64_caches.dline_size; | |
478 | icache_bsize = ppc64_caches.iline_size; | |
479 | ||
40ef8cbc PM |
480 | DBG(" <- initialize_cache_info()\n"); |
481 | } | |
482 | ||
bf1b61fb BH |
483 | static __init void print_system_info(void) |
484 | { | |
485 | pr_info("-----------------------------------------------------\n"); | |
486 | pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); | |
487 | pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size()); | |
488 | ||
489 | if (ppc64_caches.dline_size != 0x80) | |
490 | pr_info("dcache_line_size = 0x%x\n", ppc64_caches.dline_size); | |
491 | if (ppc64_caches.iline_size != 0x80) | |
492 | pr_info("icache_line_size = 0x%x\n", ppc64_caches.iline_size); | |
493 | ||
494 | pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec->cpu_features); | |
495 | pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE); | |
496 | pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS); | |
497 | pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features, | |
498 | cur_cpu_spec->cpu_user_features2); | |
499 | pr_info("mmu_features = 0x%08x\n", cur_cpu_spec->mmu_features); | |
500 | pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features); | |
501 | ||
502 | #ifdef CONFIG_PPC_STD_MMU_64 | |
503 | if (htab_address) | |
504 | pr_info("htab_address = 0x%p\n", htab_address); | |
505 | ||
506 | pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask); | |
507 | #endif | |
508 | ||
509 | if (PHYSICAL_START > 0) | |
510 | pr_info("physical_start = 0x%llx\n", | |
511 | (unsigned long long)PHYSICAL_START); | |
512 | pr_info("-----------------------------------------------------\n"); | |
513 | } | |
40ef8cbc | 514 | |
40bd587a BH |
515 | /* This returns the limit below which memory accesses to the linear |
516 | * mapping are guarnateed not to cause a TLB or SLB miss. This is | |
517 | * used to allocate interrupt or emergency stacks for which our | |
518 | * exception entry path doesn't deal with being interrupted. | |
519 | */ | |
520 | static u64 safe_stack_limit(void) | |
095c7965 | 521 | { |
40bd587a BH |
522 | #ifdef CONFIG_PPC_BOOK3E |
523 | /* Freescale BookE bolts the entire linear mapping */ | |
524 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) | |
525 | return linear_map_top; | |
526 | /* Other BookE, we assume the first GB is bolted */ | |
527 | return 1ul << 30; | |
528 | #else | |
529 | /* BookS, the first segment is bolted */ | |
530 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) | |
095c7965 | 531 | return 1UL << SID_SHIFT_1T; |
095c7965 | 532 | return 1UL << SID_SHIFT; |
40bd587a | 533 | #endif |
095c7965 AB |
534 | } |
535 | ||
40ef8cbc PM |
536 | static void __init irqstack_early_init(void) |
537 | { | |
40bd587a | 538 | u64 limit = safe_stack_limit(); |
40ef8cbc PM |
539 | unsigned int i; |
540 | ||
541 | /* | |
8f4da26e AB |
542 | * Interrupt stacks must be in the first segment since we |
543 | * cannot afford to take SLB misses on them. | |
40ef8cbc | 544 | */ |
0e551954 | 545 | for_each_possible_cpu(i) { |
3c726f8d | 546 | softirq_ctx[i] = (struct thread_info *) |
95f72d1e | 547 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 548 | THREAD_SIZE, limit)); |
3c726f8d | 549 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 550 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 551 | THREAD_SIZE, limit)); |
40ef8cbc PM |
552 | } |
553 | } | |
40ef8cbc | 554 | |
2d27cfd3 BH |
555 | #ifdef CONFIG_PPC_BOOK3E |
556 | static void __init exc_lvl_early_init(void) | |
557 | { | |
558 | unsigned int i; | |
160c7324 | 559 | unsigned long sp; |
2d27cfd3 BH |
560 | |
561 | for_each_possible_cpu(i) { | |
160c7324 TC |
562 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); |
563 | critirq_ctx[i] = (struct thread_info *)__va(sp); | |
564 | paca[i].crit_kstack = __va(sp + THREAD_SIZE); | |
565 | ||
566 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
567 | dbgirq_ctx[i] = (struct thread_info *)__va(sp); | |
568 | paca[i].dbg_kstack = __va(sp + THREAD_SIZE); | |
569 | ||
570 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
571 | mcheckirq_ctx[i] = (struct thread_info *)__va(sp); | |
572 | paca[i].mc_kstack = __va(sp + THREAD_SIZE); | |
2d27cfd3 | 573 | } |
d36b4c4f KG |
574 | |
575 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) | |
565c2f24 | 576 | patch_exception(0x040, exc_debug_debug_book3e); |
2d27cfd3 BH |
577 | } |
578 | #else | |
579 | #define exc_lvl_early_init() | |
580 | #endif | |
581 | ||
40ef8cbc PM |
582 | /* |
583 | * Stack space used when we detect a bad kernel stack pointer, and | |
729b0f71 MS |
584 | * early in SMP boots before relocation is enabled. Exclusive emergency |
585 | * stack for machine checks. | |
40ef8cbc PM |
586 | */ |
587 | static void __init emergency_stack_init(void) | |
588 | { | |
095c7965 | 589 | u64 limit; |
40ef8cbc PM |
590 | unsigned int i; |
591 | ||
592 | /* | |
593 | * Emergency stacks must be under 256MB, we cannot afford to take | |
594 | * SLB misses on them. The ABI also requires them to be 128-byte | |
595 | * aligned. | |
596 | * | |
597 | * Since we use these as temporary stacks during secondary CPU | |
598 | * bringup, we need to get at them in real mode. This means they | |
599 | * must also be within the RMO region. | |
600 | */ | |
40bd587a | 601 | limit = min(safe_stack_limit(), ppc64_rma_size); |
40ef8cbc | 602 | |
3243d874 | 603 | for_each_possible_cpu(i) { |
5d31a96e ME |
604 | struct thread_info *ti; |
605 | ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit)); | |
606 | klp_init_thread_info(ti); | |
607 | paca[i].emergency_sp = (void *)ti + THREAD_SIZE; | |
729b0f71 MS |
608 | |
609 | #ifdef CONFIG_PPC_BOOK3S_64 | |
610 | /* emergency stack for machine check exception handling. */ | |
5d31a96e ME |
611 | ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit)); |
612 | klp_init_thread_info(ti); | |
613 | paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE; | |
729b0f71 | 614 | #endif |
3243d874 | 615 | } |
40ef8cbc PM |
616 | } |
617 | ||
40ef8cbc | 618 | /* |
e39f223f | 619 | * Called into from start_kernel this initializes memblock, which is used |
0f6b77ca | 620 | * to manage page allocation until mem_init is called. |
40ef8cbc PM |
621 | */ |
622 | void __init setup_arch(char **cmdline_p) | |
623 | { | |
3e47d147 | 624 | *cmdline_p = boot_command_line; |
40ef8cbc | 625 | |
fa745a12 BH |
626 | /* |
627 | * Unflatten the device-tree passed by prom_init or kexec | |
628 | */ | |
629 | unflatten_device_tree(); | |
630 | ||
631 | /* | |
632 | * Fill the ppc64_caches & systemcfg structures with informations | |
633 | * retrieved from the device-tree. | |
634 | */ | |
635 | initialize_cache_info(); | |
636 | ||
637 | #ifdef CONFIG_PPC_RTAS | |
638 | /* | |
639 | * Initialize RTAS if available | |
640 | */ | |
641 | rtas_initialize(); | |
642 | #endif /* CONFIG_PPC_RTAS */ | |
643 | ||
644 | /* | |
645 | * Check if we have an initrd provided via the device-tree | |
646 | */ | |
647 | check_for_initrd(); | |
648 | ||
649 | /* Probe the machine type */ | |
650 | probe_machine(); | |
651 | ||
f7b9ebb7 BH |
652 | setup_panic(); |
653 | ||
fa745a12 BH |
654 | /* |
655 | * We can discover serial ports now since the above did setup the | |
656 | * hash table management for us, thus ioremap works. We do that early | |
657 | * so that further code can be debugged | |
658 | */ | |
659 | find_legacy_serial_ports(); | |
660 | ||
661 | /* | |
662 | * Register early console | |
663 | */ | |
664 | register_early_udbg_console(); | |
665 | ||
e39afba3 BH |
666 | smp_setup_cpu_maps(); |
667 | ||
fa745a12 BH |
668 | /* |
669 | * Initialize xmon | |
670 | */ | |
671 | xmon_setup(); | |
672 | ||
fa745a12 BH |
673 | check_smt_enabled(); |
674 | setup_tlb_core_data(); | |
675 | ||
676 | /* | |
677 | * Freescale Book3e parts spin in a loop provided by firmware, | |
678 | * so smp_release_cpus() does nothing for them | |
679 | */ | |
680 | #if defined(CONFIG_SMP) | |
681 | /* | |
682 | * Release secondary cpus out of their spinloops at 0x60 now that | |
683 | * we can map physical -> logical CPU ids | |
684 | */ | |
685 | smp_release_cpus(); | |
686 | #endif | |
687 | ||
688 | /* Print various info about the machine that has been gathered so far. */ | |
689 | print_system_info(); | |
690 | ||
de4cf3de BH |
691 | /* Reserve large chunks of memory for use by CMA for KVM */ |
692 | kvm_cma_reserve(); | |
693 | ||
694 | /* | |
695 | * Reserve any gigantic pages requested on the command line. | |
696 | * memblock needs to have been initialized by the time this is | |
697 | * called since this will reserve memory. | |
698 | */ | |
699 | reserve_hugetlb_gpages(); | |
700 | ||
5d31a96e ME |
701 | klp_init_thread_info(&init_thread_info); |
702 | ||
4846c5de | 703 | init_mm.start_code = (unsigned long)_stext; |
40ef8cbc PM |
704 | init_mm.end_code = (unsigned long) _etext; |
705 | init_mm.end_data = (unsigned long) _edata; | |
706 | init_mm.brk = klimit; | |
5c1f6ee9 AK |
707 | #ifdef CONFIG_PPC_64K_PAGES |
708 | init_mm.context.pte_frag = NULL; | |
15b244a8 AK |
709 | #endif |
710 | #ifdef CONFIG_SPAPR_TCE_IOMMU | |
711 | mm_iommu_init(&init_mm.context); | |
5c1f6ee9 | 712 | #endif |
40ef8cbc | 713 | irqstack_early_init(); |
2d27cfd3 | 714 | exc_lvl_early_init(); |
40ef8cbc PM |
715 | emergency_stack_init(); |
716 | ||
10239733 | 717 | initmem_init(); |
40ef8cbc | 718 | |
0458060c PM |
719 | #ifdef CONFIG_DUMMY_CONSOLE |
720 | conswitchp = &dummy_con; | |
721 | #endif | |
38db7e74 GL |
722 | if (ppc_md.setup_arch) |
723 | ppc_md.setup_arch(); | |
40ef8cbc | 724 | |
40ef8cbc | 725 | paging_init(); |
6f0ef0f5 BH |
726 | |
727 | /* Initialize the MMU context management stuff */ | |
728 | mmu_context_init(); | |
729 | ||
61e2390e MN |
730 | /* Interrupt code needs to be 64K-aligned */ |
731 | if ((unsigned long)_stext & 0xffff) | |
732 | panic("Kernelbase not 64K-aligned (0x%lx)!\n", | |
733 | (unsigned long)_stext); | |
40ef8cbc PM |
734 | } |
735 | ||
7a0268fa | 736 | #ifdef CONFIG_SMP |
c2a7e818 TH |
737 | #define PCPU_DYN_SIZE () |
738 | ||
739 | static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) | |
7a0268fa | 740 | { |
c2a7e818 TH |
741 | return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, |
742 | __pa(MAX_DMA_ADDRESS)); | |
743 | } | |
7a0268fa | 744 | |
c2a7e818 TH |
745 | static void __init pcpu_fc_free(void *ptr, size_t size) |
746 | { | |
747 | free_bootmem(__pa(ptr), size); | |
748 | } | |
7a0268fa | 749 | |
c2a7e818 TH |
750 | static int pcpu_cpu_distance(unsigned int from, unsigned int to) |
751 | { | |
752 | if (cpu_to_node(from) == cpu_to_node(to)) | |
753 | return LOCAL_DISTANCE; | |
754 | else | |
755 | return REMOTE_DISTANCE; | |
756 | } | |
757 | ||
ae01f84b AB |
758 | unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; |
759 | EXPORT_SYMBOL(__per_cpu_offset); | |
760 | ||
c2a7e818 TH |
761 | void __init setup_per_cpu_areas(void) |
762 | { | |
763 | const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; | |
764 | size_t atom_size; | |
765 | unsigned long delta; | |
766 | unsigned int cpu; | |
767 | int rc; | |
768 | ||
769 | /* | |
770 | * Linear mapping is one of 4K, 1M and 16M. For 4K, no need | |
771 | * to group units. For larger mappings, use 1M atom which | |
772 | * should be large enough to contain a number of units. | |
773 | */ | |
774 | if (mmu_linear_psize == MMU_PAGE_4K) | |
775 | atom_size = PAGE_SIZE; | |
776 | else | |
777 | atom_size = 1 << 20; | |
778 | ||
779 | rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, | |
780 | pcpu_fc_alloc, pcpu_fc_free); | |
781 | if (rc < 0) | |
782 | panic("cannot initialize percpu area (err=%d)", rc); | |
783 | ||
784 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; | |
ae01f84b AB |
785 | for_each_possible_cpu(cpu) { |
786 | __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; | |
787 | paca[cpu].data_offset = __per_cpu_offset[cpu]; | |
788 | } | |
7a0268fa AB |
789 | } |
790 | #endif | |
4cb3cee0 | 791 | |
a5d86257 AB |
792 | #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE |
793 | unsigned long memory_block_size_bytes(void) | |
794 | { | |
795 | if (ppc_md.memory_block_size) | |
796 | return ppc_md.memory_block_size(); | |
797 | ||
798 | return MIN_MEMORY_BLOCK_SIZE; | |
799 | } | |
800 | #endif | |
4cb3cee0 | 801 | |
ecd73cc5 | 802 | #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) |
4cb3cee0 BH |
803 | struct ppc_pci_io ppc_pci_io; |
804 | EXPORT_SYMBOL(ppc_pci_io); | |
ecd73cc5 | 805 | #endif |
c54b2bf1 AB |
806 | |
807 | #ifdef CONFIG_HARDLOCKUP_DETECTOR | |
808 | u64 hw_nmi_get_sample_period(int watchdog_thresh) | |
809 | { | |
810 | return ppc_proc_freq * watchdog_thresh; | |
811 | } | |
812 | ||
813 | /* | |
814 | * The hardlockup detector breaks PMU event based branches and is likely | |
815 | * to get false positives in KVM guests, so disable it by default. | |
816 | */ | |
817 | static int __init disable_hardlockup_detector(void) | |
818 | { | |
d19d5efd | 819 | hardlockup_detector_disable(); |
c54b2bf1 AB |
820 | |
821 | return 0; | |
822 | } | |
823 | early_initcall(disable_hardlockup_detector); | |
824 | #endif |