Commit | Line | Data |
---|---|---|
40ef8cbc PM |
1 | /* |
2 | * | |
3 | * Common boot and setup code. | |
4 | * | |
5 | * Copyright (C) 2001 PPC64 Team, IBM Corp | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
7191b615 | 13 | #define DEBUG |
40ef8cbc | 14 | |
4b16f8e2 | 15 | #include <linux/export.h> |
40ef8cbc PM |
16 | #include <linux/string.h> |
17 | #include <linux/sched.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/reboot.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/initrd.h> | |
40ef8cbc PM |
23 | #include <linux/seq_file.h> |
24 | #include <linux/ioport.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/utsname.h> | |
27 | #include <linux/tty.h> | |
28 | #include <linux/root_dev.h> | |
29 | #include <linux/notifier.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/unistd.h> | |
32 | #include <linux/serial.h> | |
33 | #include <linux/serial_8250.h> | |
7a0268fa | 34 | #include <linux/bootmem.h> |
12d04eef | 35 | #include <linux/pci.h> |
945feb17 | 36 | #include <linux/lockdep.h> |
95f72d1e | 37 | #include <linux/memblock.h> |
a6146888 | 38 | #include <linux/hugetlb.h> |
a5d86257 | 39 | #include <linux/memory.h> |
c54b2bf1 | 40 | #include <linux/nmi.h> |
a6146888 | 41 | |
40ef8cbc | 42 | #include <asm/io.h> |
0cc4746c | 43 | #include <asm/kdump.h> |
40ef8cbc PM |
44 | #include <asm/prom.h> |
45 | #include <asm/processor.h> | |
46 | #include <asm/pgtable.h> | |
40ef8cbc PM |
47 | #include <asm/smp.h> |
48 | #include <asm/elf.h> | |
49 | #include <asm/machdep.h> | |
50 | #include <asm/paca.h> | |
40ef8cbc PM |
51 | #include <asm/time.h> |
52 | #include <asm/cputable.h> | |
53 | #include <asm/sections.h> | |
54 | #include <asm/btext.h> | |
55 | #include <asm/nvram.h> | |
56 | #include <asm/setup.h> | |
40ef8cbc PM |
57 | #include <asm/rtas.h> |
58 | #include <asm/iommu.h> | |
59 | #include <asm/serial.h> | |
60 | #include <asm/cache.h> | |
61 | #include <asm/page.h> | |
62 | #include <asm/mmu.h> | |
40ef8cbc | 63 | #include <asm/firmware.h> |
f78541dc | 64 | #include <asm/xmon.h> |
dcad47fc | 65 | #include <asm/udbg.h> |
593e537b | 66 | #include <asm/kexec.h> |
25d21ad6 | 67 | #include <asm/mmu_context.h> |
d36b4c4f | 68 | #include <asm/code-patching.h> |
aa04b4cc | 69 | #include <asm/kvm_ppc.h> |
a6146888 | 70 | #include <asm/hugetlb.h> |
4e21b94c | 71 | #include <asm/epapr_hcalls.h> |
40ef8cbc PM |
72 | |
73 | #ifdef DEBUG | |
74 | #define DBG(fmt...) udbg_printf(fmt) | |
75 | #else | |
76 | #define DBG(fmt...) | |
77 | #endif | |
78 | ||
8246aca7 | 79 | int spinning_secondaries; |
40ef8cbc PM |
80 | u64 ppc64_pft_size; |
81 | ||
dabcafd3 OJ |
82 | /* Pick defaults since we might want to patch instructions |
83 | * before we've read this from the device tree. | |
84 | */ | |
85 | struct ppc64_caches ppc64_caches = { | |
5a2fe38d OJ |
86 | .dline_size = 0x40, |
87 | .log_dline_size = 6, | |
88 | .iline_size = 0x40, | |
89 | .log_iline_size = 6 | |
dabcafd3 | 90 | }; |
40ef8cbc PM |
91 | EXPORT_SYMBOL_GPL(ppc64_caches); |
92 | ||
93 | /* | |
94 | * These are used in binfmt_elf.c to put aux entries on the stack | |
95 | * for each elf executable being started. | |
96 | */ | |
97 | int dcache_bsize; | |
98 | int icache_bsize; | |
99 | int ucache_bsize; | |
100 | ||
28efc35f SW |
101 | #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) |
102 | static void setup_tlb_core_data(void) | |
103 | { | |
104 | int cpu; | |
105 | ||
82d86de2 SW |
106 | BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); |
107 | ||
28efc35f SW |
108 | for_each_possible_cpu(cpu) { |
109 | int first = cpu_first_thread_sibling(cpu); | |
110 | ||
d9e1831a SW |
111 | /* |
112 | * If we boot via kdump on a non-primary thread, | |
113 | * make sure we point at the thread that actually | |
114 | * set up this TLB. | |
115 | */ | |
116 | if (cpu_first_thread_sibling(boot_cpuid) == first) | |
117 | first = boot_cpuid; | |
118 | ||
28efc35f SW |
119 | paca[cpu].tcd_ptr = &paca[first].tcd; |
120 | ||
121 | /* | |
122 | * If we have threads, we need either tlbsrx. | |
123 | * or e6500 tablewalk mode, or else TLB handlers | |
124 | * will be racy and could produce duplicate entries. | |
125 | */ | |
126 | if (smt_enabled_at_boot >= 2 && | |
127 | !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && | |
128 | book3e_htw_mode != PPC_HTW_E6500) { | |
129 | /* Should we panic instead? */ | |
130 | WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n", | |
131 | __func__); | |
132 | } | |
133 | } | |
134 | } | |
135 | #else | |
136 | static void setup_tlb_core_data(void) | |
137 | { | |
138 | } | |
139 | #endif | |
140 | ||
40ef8cbc PM |
141 | #ifdef CONFIG_SMP |
142 | ||
954e6da5 | 143 | static char *smt_enabled_cmdline; |
40ef8cbc PM |
144 | |
145 | /* Look for ibm,smt-enabled OF option */ | |
146 | static void check_smt_enabled(void) | |
147 | { | |
148 | struct device_node *dn; | |
a7f67bdf | 149 | const char *smt_option; |
40ef8cbc | 150 | |
954e6da5 NF |
151 | /* Default to enabling all threads */ |
152 | smt_enabled_at_boot = threads_per_core; | |
40ef8cbc | 153 | |
954e6da5 NF |
154 | /* Allow the command line to overrule the OF option */ |
155 | if (smt_enabled_cmdline) { | |
156 | if (!strcmp(smt_enabled_cmdline, "on")) | |
157 | smt_enabled_at_boot = threads_per_core; | |
158 | else if (!strcmp(smt_enabled_cmdline, "off")) | |
159 | smt_enabled_at_boot = 0; | |
160 | else { | |
1618bd53 | 161 | int smt; |
954e6da5 NF |
162 | int rc; |
163 | ||
1618bd53 | 164 | rc = kstrtoint(smt_enabled_cmdline, 10, &smt); |
954e6da5 NF |
165 | if (!rc) |
166 | smt_enabled_at_boot = | |
1618bd53 | 167 | min(threads_per_core, smt); |
954e6da5 NF |
168 | } |
169 | } else { | |
170 | dn = of_find_node_by_path("/options"); | |
171 | if (dn) { | |
172 | smt_option = of_get_property(dn, "ibm,smt-enabled", | |
173 | NULL); | |
174 | ||
175 | if (smt_option) { | |
176 | if (!strcmp(smt_option, "on")) | |
177 | smt_enabled_at_boot = threads_per_core; | |
178 | else if (!strcmp(smt_option, "off")) | |
179 | smt_enabled_at_boot = 0; | |
180 | } | |
181 | ||
182 | of_node_put(dn); | |
183 | } | |
184 | } | |
40ef8cbc PM |
185 | } |
186 | ||
187 | /* Look for smt-enabled= cmdline option */ | |
188 | static int __init early_smt_enabled(char *p) | |
189 | { | |
954e6da5 | 190 | smt_enabled_cmdline = p; |
40ef8cbc PM |
191 | return 0; |
192 | } | |
193 | early_param("smt-enabled", early_smt_enabled); | |
194 | ||
5ad57078 PM |
195 | #else |
196 | #define check_smt_enabled() | |
40ef8cbc PM |
197 | #endif /* CONFIG_SMP */ |
198 | ||
25e13814 ME |
199 | /** Fix up paca fields required for the boot cpu */ |
200 | static void fixup_boot_paca(void) | |
201 | { | |
202 | /* The boot cpu is started */ | |
203 | get_paca()->cpu_start = 1; | |
204 | /* Allow percpu accesses to work until we setup percpu data */ | |
205 | get_paca()->data_offset = 0; | |
206 | } | |
207 | ||
8f619b54 BH |
208 | static void cpu_ready_for_interrupts(void) |
209 | { | |
210 | /* Set IR and DR in PACA MSR */ | |
211 | get_paca()->kernel_msr = MSR_KERNEL; | |
212 | ||
633440f1 ME |
213 | /* |
214 | * Enable AIL if supported, and we are in hypervisor mode. If we are | |
215 | * not in hypervisor mode, we enable relocation-on interrupts later | |
216 | * in pSeries_setup_arch() using the H_SET_MODE hcall. | |
217 | */ | |
18aa0da3 PM |
218 | if (cpu_has_feature(CPU_FTR_HVMODE) && |
219 | cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
8f619b54 BH |
220 | unsigned long lpcr = mfspr(SPRN_LPCR); |
221 | mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); | |
222 | } | |
223 | } | |
224 | ||
40ef8cbc PM |
225 | /* |
226 | * Early initialization entry point. This is called by head.S | |
227 | * with MMU translation disabled. We rely on the "feature" of | |
228 | * the CPU that ignores the top 2 bits of the address in real | |
229 | * mode so we can access kernel globals normally provided we | |
230 | * only toy with things in the RMO region. From here, we do | |
95f72d1e | 231 | * some early parsing of the device-tree to setup out MEMBLOCK |
40ef8cbc PM |
232 | * data structures, and allocate & initialize the hash table |
233 | * and segment tables so we can start running with translation | |
234 | * enabled. | |
235 | * | |
236 | * It is this function which will call the probe() callback of | |
237 | * the various platform types and copy the matching one to the | |
238 | * global ppc_md structure. Your platform can eventually do | |
239 | * some very early initializations from the probe() routine, but | |
240 | * this is not recommended, be very careful as, for example, the | |
241 | * device-tree is not accessible via normal means at this point. | |
242 | */ | |
243 | ||
244 | void __init early_setup(unsigned long dt_ptr) | |
245 | { | |
6a7e4064 GL |
246 | static __initdata struct paca_struct boot_paca; |
247 | ||
24d96495 BH |
248 | /* -------- printk is _NOT_ safe to use here ! ------- */ |
249 | ||
42c4aaad | 250 | /* Identify CPU type */ |
974a76f5 | 251 | identify_cpu(0, mfspr(SPRN_PVR)); |
42c4aaad | 252 | |
33dbcf72 | 253 | /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ |
1426d5a3 ME |
254 | initialise_paca(&boot_paca, 0); |
255 | setup_paca(&boot_paca); | |
25e13814 | 256 | fixup_boot_paca(); |
33dbcf72 | 257 | |
945feb17 BH |
258 | /* Initialize lockdep early or else spinlocks will blow */ |
259 | lockdep_init(); | |
260 | ||
24d96495 BH |
261 | /* -------- printk is now safe to use ------- */ |
262 | ||
f2fd2513 BH |
263 | /* Enable early debugging if any specified (see udbg.h) */ |
264 | udbg_early_init(); | |
265 | ||
e8222502 | 266 | DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); |
40ef8cbc | 267 | |
40ef8cbc | 268 | /* |
3c607ce2 LV |
269 | * Do early initialization using the flattened device |
270 | * tree, such as retrieving the physical memory map or | |
271 | * calculating/retrieving the hash table size. | |
40ef8cbc PM |
272 | */ |
273 | early_init_devtree(__va(dt_ptr)); | |
274 | ||
4e21b94c LT |
275 | epapr_paravirt_early_init(); |
276 | ||
4df20460 | 277 | /* Now we know the logical id of our boot cpu, setup the paca. */ |
1426d5a3 | 278 | setup_paca(&paca[boot_cpuid]); |
25e13814 | 279 | fixup_boot_paca(); |
4df20460 | 280 | |
e8222502 BH |
281 | /* Probe the machine type */ |
282 | probe_machine(); | |
40ef8cbc | 283 | |
47310413 | 284 | setup_kdump_trampoline(); |
0cc4746c | 285 | |
40ef8cbc PM |
286 | DBG("Found, Initializing memory management...\n"); |
287 | ||
757c74d2 BH |
288 | /* Initialize the hash table or TLB handling */ |
289 | early_init_mmu(); | |
40ef8cbc | 290 | |
a944a9c4 BH |
291 | /* |
292 | * At this point, we can let interrupts switch to virtual mode | |
293 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
8f619b54 | 294 | * have IR and DR set and enable AIL if it exists |
a944a9c4 | 295 | */ |
8f619b54 | 296 | cpu_ready_for_interrupts(); |
a944a9c4 BH |
297 | |
298 | /* Reserve large chunks of memory for use by CMA for KVM */ | |
fa61a4e3 AK |
299 | kvm_cma_reserve(); |
300 | ||
a6146888 BB |
301 | /* |
302 | * Reserve any gigantic pages requested on the command line. | |
303 | * memblock needs to have been initialized by the time this is | |
304 | * called since this will reserve memory. | |
305 | */ | |
306 | reserve_hugetlb_gpages(); | |
307 | ||
40ef8cbc | 308 | DBG(" <- early_setup()\n"); |
7191b615 BH |
309 | |
310 | #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX | |
311 | /* | |
312 | * This needs to be done *last* (after the above DBG() even) | |
313 | * | |
314 | * Right after we return from this function, we turn on the MMU | |
315 | * which means the real-mode access trick that btext does will | |
316 | * no longer work, it needs to switch to using a real MMU | |
317 | * mapping. This call will ensure that it does | |
318 | */ | |
319 | btext_map(); | |
320 | #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ | |
40ef8cbc PM |
321 | } |
322 | ||
799d6046 PM |
323 | #ifdef CONFIG_SMP |
324 | void early_setup_secondary(void) | |
325 | { | |
d04c56f7 | 326 | /* Mark interrupts enabled in PACA */ |
757c74d2 | 327 | get_paca()->soft_enabled = 0; |
799d6046 | 328 | |
757c74d2 BH |
329 | /* Initialize the hash table or TLB handling */ |
330 | early_init_mmu_secondary(); | |
a944a9c4 BH |
331 | |
332 | /* | |
333 | * At this point, we can let interrupts switch to virtual mode | |
334 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
335 | * have IR and DR set. | |
336 | */ | |
8f619b54 | 337 | cpu_ready_for_interrupts(); |
799d6046 PM |
338 | } |
339 | ||
340 | #endif /* CONFIG_SMP */ | |
40ef8cbc | 341 | |
b8f51021 | 342 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
567cf94d SW |
343 | static bool use_spinloop(void) |
344 | { | |
345 | if (!IS_ENABLED(CONFIG_PPC_BOOK3E)) | |
346 | return true; | |
347 | ||
348 | /* | |
349 | * When book3e boots from kexec, the ePAPR spin table does | |
350 | * not get used. | |
351 | */ | |
352 | return of_property_read_bool(of_chosen, "linux,booted-from-kexec"); | |
353 | } | |
354 | ||
b8f51021 ME |
355 | void smp_release_cpus(void) |
356 | { | |
758438a7 | 357 | unsigned long *ptr; |
9d07bc84 | 358 | int i; |
b8f51021 | 359 | |
567cf94d SW |
360 | if (!use_spinloop()) |
361 | return; | |
362 | ||
b8f51021 ME |
363 | DBG(" -> smp_release_cpus()\n"); |
364 | ||
365 | /* All secondary cpus are spinning on a common spinloop, release them | |
366 | * all now so they can start to spin on their individual paca | |
367 | * spinloops. For non SMP kernels, the secondary cpus never get out | |
368 | * of the common spinloop. | |
1f6a93e4 | 369 | */ |
b8f51021 | 370 | |
758438a7 ME |
371 | ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop |
372 | - PHYSICAL_START); | |
2751b628 | 373 | *ptr = ppc_function_entry(generic_secondary_smp_init); |
9d07bc84 BH |
374 | |
375 | /* And wait a bit for them to catch up */ | |
376 | for (i = 0; i < 100000; i++) { | |
377 | mb(); | |
378 | HMT_low(); | |
7ac87abb | 379 | if (spinning_secondaries == 0) |
9d07bc84 BH |
380 | break; |
381 | udelay(1); | |
382 | } | |
7ac87abb | 383 | DBG("spinning_secondaries = %d\n", spinning_secondaries); |
b8f51021 ME |
384 | |
385 | DBG(" <- smp_release_cpus()\n"); | |
386 | } | |
387 | #endif /* CONFIG_SMP || CONFIG_KEXEC */ | |
388 | ||
40ef8cbc | 389 | /* |
799d6046 PM |
390 | * Initialize some remaining members of the ppc64_caches and systemcfg |
391 | * structures | |
40ef8cbc PM |
392 | * (at least until we get rid of them completely). This is mostly some |
393 | * cache informations about the CPU that will be used by cache flush | |
394 | * routines and/or provided to userland | |
395 | */ | |
396 | static void __init initialize_cache_info(void) | |
397 | { | |
398 | struct device_node *np; | |
399 | unsigned long num_cpus = 0; | |
400 | ||
401 | DBG(" -> initialize_cache_info()\n"); | |
402 | ||
94db7c5e | 403 | for_each_node_by_type(np, "cpu") { |
40ef8cbc PM |
404 | num_cpus += 1; |
405 | ||
dfbe93a2 AB |
406 | /* |
407 | * We're assuming *all* of the CPUs have the same | |
40ef8cbc PM |
408 | * d-cache and i-cache sizes... -Peter |
409 | */ | |
dfbe93a2 | 410 | if (num_cpus == 1) { |
7946d5a5 | 411 | const __be32 *sizep, *lsizep; |
40ef8cbc | 412 | u32 size, lsize; |
40ef8cbc PM |
413 | |
414 | size = 0; | |
415 | lsize = cur_cpu_spec->dcache_bsize; | |
e2eb6392 | 416 | sizep = of_get_property(np, "d-cache-size", NULL); |
40ef8cbc | 417 | if (sizep != NULL) |
7946d5a5 | 418 | size = be32_to_cpu(*sizep); |
dfbe93a2 AB |
419 | lsizep = of_get_property(np, "d-cache-block-size", |
420 | NULL); | |
20474abd BH |
421 | /* fallback if block size missing */ |
422 | if (lsizep == NULL) | |
dfbe93a2 AB |
423 | lsizep = of_get_property(np, |
424 | "d-cache-line-size", | |
425 | NULL); | |
40ef8cbc | 426 | if (lsizep != NULL) |
7946d5a5 | 427 | lsize = be32_to_cpu(*lsizep); |
b0d436c7 | 428 | if (sizep == NULL || lsizep == NULL) |
40ef8cbc PM |
429 | DBG("Argh, can't find dcache properties ! " |
430 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
431 | ||
a7f290da BH |
432 | ppc64_caches.dsize = size; |
433 | ppc64_caches.dline_size = lsize; | |
40ef8cbc PM |
434 | ppc64_caches.log_dline_size = __ilog2(lsize); |
435 | ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; | |
436 | ||
437 | size = 0; | |
438 | lsize = cur_cpu_spec->icache_bsize; | |
e2eb6392 | 439 | sizep = of_get_property(np, "i-cache-size", NULL); |
40ef8cbc | 440 | if (sizep != NULL) |
7946d5a5 | 441 | size = be32_to_cpu(*sizep); |
dfbe93a2 AB |
442 | lsizep = of_get_property(np, "i-cache-block-size", |
443 | NULL); | |
20474abd | 444 | if (lsizep == NULL) |
dfbe93a2 AB |
445 | lsizep = of_get_property(np, |
446 | "i-cache-line-size", | |
447 | NULL); | |
40ef8cbc | 448 | if (lsizep != NULL) |
7946d5a5 | 449 | lsize = be32_to_cpu(*lsizep); |
b0d436c7 | 450 | if (sizep == NULL || lsizep == NULL) |
40ef8cbc PM |
451 | DBG("Argh, can't find icache properties ! " |
452 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
453 | ||
a7f290da BH |
454 | ppc64_caches.isize = size; |
455 | ppc64_caches.iline_size = lsize; | |
40ef8cbc PM |
456 | ppc64_caches.log_iline_size = __ilog2(lsize); |
457 | ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; | |
458 | } | |
459 | } | |
460 | ||
40ef8cbc PM |
461 | DBG(" <- initialize_cache_info()\n"); |
462 | } | |
463 | ||
40ef8cbc PM |
464 | |
465 | /* | |
466 | * Do some initial setup of the system. The parameters are those which | |
467 | * were passed in from the bootloader. | |
468 | */ | |
469 | void __init setup_system(void) | |
470 | { | |
471 | DBG(" -> setup_system()\n"); | |
472 | ||
826ea8f2 TB |
473 | /* Apply the CPUs-specific and firmware specific fixups to kernel |
474 | * text (nop out sections not relevant to this CPU or this firmware) | |
42c4aaad | 475 | */ |
0909c8c2 | 476 | do_feature_fixups(cur_cpu_spec->cpu_features, |
42c4aaad | 477 | &__start___ftr_fixup, &__stop___ftr_fixup); |
7c03d653 BH |
478 | do_feature_fixups(cur_cpu_spec->mmu_features, |
479 | &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); | |
826ea8f2 TB |
480 | do_feature_fixups(powerpc_firmware_features, |
481 | &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); | |
2d1b2027 KG |
482 | do_lwsync_fixups(cur_cpu_spec->cpu_features, |
483 | &__start___lwsync_fixup, &__stop___lwsync_fixup); | |
d715e433 | 484 | do_final_fixups(); |
42c4aaad | 485 | |
40ef8cbc PM |
486 | /* |
487 | * Unflatten the device-tree passed by prom_init or kexec | |
488 | */ | |
489 | unflatten_device_tree(); | |
490 | ||
491 | /* | |
492 | * Fill the ppc64_caches & systemcfg structures with informations | |
0ebfff14 | 493 | * retrieved from the device-tree. |
40ef8cbc PM |
494 | */ |
495 | initialize_cache_info(); | |
496 | ||
497 | #ifdef CONFIG_PPC_RTAS | |
498 | /* | |
499 | * Initialize RTAS if available | |
500 | */ | |
501 | rtas_initialize(); | |
502 | #endif /* CONFIG_PPC_RTAS */ | |
40ef8cbc PM |
503 | |
504 | /* | |
505 | * Check if we have an initrd provided via the device-tree | |
506 | */ | |
507 | check_for_initrd(); | |
40ef8cbc PM |
508 | |
509 | /* | |
510 | * Do some platform specific early initializations, that includes | |
511 | * setting up the hash table pointers. It also sets up some interrupt-mapping | |
512 | * related options that will be used by finish_device_tree() | |
513 | */ | |
57744ea9 GL |
514 | if (ppc_md.init_early) |
515 | ppc_md.init_early(); | |
40ef8cbc | 516 | |
463ce0e1 BH |
517 | /* |
518 | * We can discover serial ports now since the above did setup the | |
519 | * hash table management for us, thus ioremap works. We do that early | |
520 | * so that further code can be debugged | |
521 | */ | |
463ce0e1 | 522 | find_legacy_serial_ports(); |
463ce0e1 | 523 | |
40ef8cbc PM |
524 | /* |
525 | * Register early console | |
526 | */ | |
527 | register_early_udbg_console(); | |
40ef8cbc | 528 | |
47679283 ME |
529 | /* |
530 | * Initialize xmon | |
531 | */ | |
532 | xmon_setup(); | |
480f6f35 | 533 | |
5ad57078 | 534 | smp_setup_cpu_maps(); |
954e6da5 | 535 | check_smt_enabled(); |
28efc35f | 536 | setup_tlb_core_data(); |
40ef8cbc | 537 | |
e16c8765 AF |
538 | /* |
539 | * Freescale Book3e parts spin in a loop provided by firmware, | |
540 | * so smp_release_cpus() does nothing for them | |
541 | */ | |
567cf94d | 542 | #if defined(CONFIG_SMP) |
40ef8cbc PM |
543 | /* Release secondary cpus out of their spinloops at 0x60 now that |
544 | * we can map physical -> logical CPU ids | |
545 | */ | |
546 | smp_release_cpus(); | |
f018b36f | 547 | #endif |
40ef8cbc | 548 | |
5c0aebf6 ME |
549 | pr_info("Starting Linux %s %s\n", init_utsname()->machine, |
550 | init_utsname()->version); | |
40ef8cbc | 551 | |
2c186e05 AB |
552 | pr_info("-----------------------------------------------------\n"); |
553 | pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); | |
554 | pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size()); | |
bdce97e9 | 555 | |
9697add0 | 556 | if (ppc64_caches.dline_size != 0x80) |
2c186e05 | 557 | pr_info("dcache_line_size = 0x%x\n", ppc64_caches.dline_size); |
9697add0 | 558 | if (ppc64_caches.iline_size != 0x80) |
2c186e05 | 559 | pr_info("icache_line_size = 0x%x\n", ppc64_caches.iline_size); |
bdce97e9 | 560 | |
2c186e05 AB |
561 | pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec->cpu_features); |
562 | pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE); | |
563 | pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS); | |
564 | pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features, | |
87d99c0e | 565 | cur_cpu_spec->cpu_user_features2); |
2c186e05 AB |
566 | pr_info("mmu_features = 0x%08x\n", cur_cpu_spec->mmu_features); |
567 | pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features); | |
87d99c0e | 568 | |
94491685 | 569 | #ifdef CONFIG_PPC_STD_MMU_64 |
9697add0 | 570 | if (htab_address) |
2c186e05 | 571 | pr_info("htab_address = 0x%p\n", htab_address); |
bdce97e9 | 572 | |
2c186e05 | 573 | pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask); |
bdce97e9 ME |
574 | #endif |
575 | ||
b160544c | 576 | if (PHYSICAL_START > 0) |
2c186e05 | 577 | pr_info("physical_start = 0x%llx\n", |
e468455e | 578 | (unsigned long long)PHYSICAL_START); |
2c186e05 | 579 | pr_info("-----------------------------------------------------\n"); |
40ef8cbc | 580 | |
40ef8cbc PM |
581 | DBG(" <- setup_system()\n"); |
582 | } | |
583 | ||
40bd587a BH |
584 | /* This returns the limit below which memory accesses to the linear |
585 | * mapping are guarnateed not to cause a TLB or SLB miss. This is | |
586 | * used to allocate interrupt or emergency stacks for which our | |
587 | * exception entry path doesn't deal with being interrupted. | |
588 | */ | |
589 | static u64 safe_stack_limit(void) | |
095c7965 | 590 | { |
40bd587a BH |
591 | #ifdef CONFIG_PPC_BOOK3E |
592 | /* Freescale BookE bolts the entire linear mapping */ | |
593 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) | |
594 | return linear_map_top; | |
595 | /* Other BookE, we assume the first GB is bolted */ | |
596 | return 1ul << 30; | |
597 | #else | |
598 | /* BookS, the first segment is bolted */ | |
599 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) | |
095c7965 | 600 | return 1UL << SID_SHIFT_1T; |
095c7965 | 601 | return 1UL << SID_SHIFT; |
40bd587a | 602 | #endif |
095c7965 AB |
603 | } |
604 | ||
40ef8cbc PM |
605 | static void __init irqstack_early_init(void) |
606 | { | |
40bd587a | 607 | u64 limit = safe_stack_limit(); |
40ef8cbc PM |
608 | unsigned int i; |
609 | ||
610 | /* | |
8f4da26e AB |
611 | * Interrupt stacks must be in the first segment since we |
612 | * cannot afford to take SLB misses on them. | |
40ef8cbc | 613 | */ |
0e551954 | 614 | for_each_possible_cpu(i) { |
3c726f8d | 615 | softirq_ctx[i] = (struct thread_info *) |
95f72d1e | 616 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 617 | THREAD_SIZE, limit)); |
3c726f8d | 618 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 619 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 620 | THREAD_SIZE, limit)); |
40ef8cbc PM |
621 | } |
622 | } | |
40ef8cbc | 623 | |
2d27cfd3 BH |
624 | #ifdef CONFIG_PPC_BOOK3E |
625 | static void __init exc_lvl_early_init(void) | |
626 | { | |
627 | unsigned int i; | |
160c7324 | 628 | unsigned long sp; |
2d27cfd3 BH |
629 | |
630 | for_each_possible_cpu(i) { | |
160c7324 TC |
631 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); |
632 | critirq_ctx[i] = (struct thread_info *)__va(sp); | |
633 | paca[i].crit_kstack = __va(sp + THREAD_SIZE); | |
634 | ||
635 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
636 | dbgirq_ctx[i] = (struct thread_info *)__va(sp); | |
637 | paca[i].dbg_kstack = __va(sp + THREAD_SIZE); | |
638 | ||
639 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
640 | mcheckirq_ctx[i] = (struct thread_info *)__va(sp); | |
641 | paca[i].mc_kstack = __va(sp + THREAD_SIZE); | |
2d27cfd3 | 642 | } |
d36b4c4f KG |
643 | |
644 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) | |
565c2f24 | 645 | patch_exception(0x040, exc_debug_debug_book3e); |
2d27cfd3 BH |
646 | } |
647 | #else | |
648 | #define exc_lvl_early_init() | |
649 | #endif | |
650 | ||
40ef8cbc PM |
651 | /* |
652 | * Stack space used when we detect a bad kernel stack pointer, and | |
729b0f71 MS |
653 | * early in SMP boots before relocation is enabled. Exclusive emergency |
654 | * stack for machine checks. | |
40ef8cbc PM |
655 | */ |
656 | static void __init emergency_stack_init(void) | |
657 | { | |
095c7965 | 658 | u64 limit; |
40ef8cbc PM |
659 | unsigned int i; |
660 | ||
661 | /* | |
662 | * Emergency stacks must be under 256MB, we cannot afford to take | |
663 | * SLB misses on them. The ABI also requires them to be 128-byte | |
664 | * aligned. | |
665 | * | |
666 | * Since we use these as temporary stacks during secondary CPU | |
667 | * bringup, we need to get at them in real mode. This means they | |
668 | * must also be within the RMO region. | |
669 | */ | |
40bd587a | 670 | limit = min(safe_stack_limit(), ppc64_rma_size); |
40ef8cbc | 671 | |
3243d874 ME |
672 | for_each_possible_cpu(i) { |
673 | unsigned long sp; | |
95f72d1e | 674 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); |
3243d874 ME |
675 | sp += THREAD_SIZE; |
676 | paca[i].emergency_sp = __va(sp); | |
729b0f71 MS |
677 | |
678 | #ifdef CONFIG_PPC_BOOK3S_64 | |
679 | /* emergency stack for machine check exception handling. */ | |
680 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); | |
681 | sp += THREAD_SIZE; | |
682 | paca[i].mc_emergency_sp = __va(sp); | |
683 | #endif | |
3243d874 | 684 | } |
40ef8cbc PM |
685 | } |
686 | ||
40ef8cbc | 687 | /* |
e39f223f | 688 | * Called into from start_kernel this initializes memblock, which is used |
0f6b77ca | 689 | * to manage page allocation until mem_init is called. |
40ef8cbc PM |
690 | */ |
691 | void __init setup_arch(char **cmdline_p) | |
692 | { | |
3e47d147 | 693 | *cmdline_p = boot_command_line; |
40ef8cbc PM |
694 | |
695 | /* | |
696 | * Set cache line size based on type of cpu as a default. | |
697 | * Systems with OF can look in the properties on the cpu node(s) | |
698 | * for a possibly more accurate value. | |
699 | */ | |
700 | dcache_bsize = ppc64_caches.dline_size; | |
701 | icache_bsize = ppc64_caches.iline_size; | |
702 | ||
40ef8cbc | 703 | if (ppc_md.panic) |
7e990266 | 704 | setup_panic(); |
40ef8cbc | 705 | |
4846c5de | 706 | init_mm.start_code = (unsigned long)_stext; |
40ef8cbc PM |
707 | init_mm.end_code = (unsigned long) _etext; |
708 | init_mm.end_data = (unsigned long) _edata; | |
709 | init_mm.brk = klimit; | |
5c1f6ee9 AK |
710 | #ifdef CONFIG_PPC_64K_PAGES |
711 | init_mm.context.pte_frag = NULL; | |
15b244a8 AK |
712 | #endif |
713 | #ifdef CONFIG_SPAPR_TCE_IOMMU | |
714 | mm_iommu_init(&init_mm.context); | |
5c1f6ee9 | 715 | #endif |
40ef8cbc | 716 | irqstack_early_init(); |
2d27cfd3 | 717 | exc_lvl_early_init(); |
40ef8cbc PM |
718 | emergency_stack_init(); |
719 | ||
10239733 | 720 | initmem_init(); |
40ef8cbc | 721 | |
0458060c PM |
722 | #ifdef CONFIG_DUMMY_CONSOLE |
723 | conswitchp = &dummy_con; | |
724 | #endif | |
725 | ||
38db7e74 GL |
726 | if (ppc_md.setup_arch) |
727 | ppc_md.setup_arch(); | |
40ef8cbc | 728 | |
40ef8cbc | 729 | paging_init(); |
6f0ef0f5 BH |
730 | |
731 | /* Initialize the MMU context management stuff */ | |
732 | mmu_context_init(); | |
733 | ||
61e2390e MN |
734 | /* Interrupt code needs to be 64K-aligned */ |
735 | if ((unsigned long)_stext & 0xffff) | |
736 | panic("Kernelbase not 64K-aligned (0x%lx)!\n", | |
737 | (unsigned long)_stext); | |
40ef8cbc PM |
738 | } |
739 | ||
7a0268fa | 740 | #ifdef CONFIG_SMP |
c2a7e818 TH |
741 | #define PCPU_DYN_SIZE () |
742 | ||
743 | static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) | |
7a0268fa | 744 | { |
c2a7e818 TH |
745 | return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, |
746 | __pa(MAX_DMA_ADDRESS)); | |
747 | } | |
7a0268fa | 748 | |
c2a7e818 TH |
749 | static void __init pcpu_fc_free(void *ptr, size_t size) |
750 | { | |
751 | free_bootmem(__pa(ptr), size); | |
752 | } | |
7a0268fa | 753 | |
c2a7e818 TH |
754 | static int pcpu_cpu_distance(unsigned int from, unsigned int to) |
755 | { | |
756 | if (cpu_to_node(from) == cpu_to_node(to)) | |
757 | return LOCAL_DISTANCE; | |
758 | else | |
759 | return REMOTE_DISTANCE; | |
760 | } | |
761 | ||
ae01f84b AB |
762 | unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; |
763 | EXPORT_SYMBOL(__per_cpu_offset); | |
764 | ||
c2a7e818 TH |
765 | void __init setup_per_cpu_areas(void) |
766 | { | |
767 | const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; | |
768 | size_t atom_size; | |
769 | unsigned long delta; | |
770 | unsigned int cpu; | |
771 | int rc; | |
772 | ||
773 | /* | |
774 | * Linear mapping is one of 4K, 1M and 16M. For 4K, no need | |
775 | * to group units. For larger mappings, use 1M atom which | |
776 | * should be large enough to contain a number of units. | |
777 | */ | |
778 | if (mmu_linear_psize == MMU_PAGE_4K) | |
779 | atom_size = PAGE_SIZE; | |
780 | else | |
781 | atom_size = 1 << 20; | |
782 | ||
783 | rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, | |
784 | pcpu_fc_alloc, pcpu_fc_free); | |
785 | if (rc < 0) | |
786 | panic("cannot initialize percpu area (err=%d)", rc); | |
787 | ||
788 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; | |
ae01f84b AB |
789 | for_each_possible_cpu(cpu) { |
790 | __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; | |
791 | paca[cpu].data_offset = __per_cpu_offset[cpu]; | |
792 | } | |
7a0268fa AB |
793 | } |
794 | #endif | |
4cb3cee0 | 795 | |
a5d86257 AB |
796 | #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE |
797 | unsigned long memory_block_size_bytes(void) | |
798 | { | |
799 | if (ppc_md.memory_block_size) | |
800 | return ppc_md.memory_block_size(); | |
801 | ||
802 | return MIN_MEMORY_BLOCK_SIZE; | |
803 | } | |
804 | #endif | |
4cb3cee0 | 805 | |
ecd73cc5 | 806 | #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) |
4cb3cee0 BH |
807 | struct ppc_pci_io ppc_pci_io; |
808 | EXPORT_SYMBOL(ppc_pci_io); | |
ecd73cc5 | 809 | #endif |
c54b2bf1 AB |
810 | |
811 | #ifdef CONFIG_HARDLOCKUP_DETECTOR | |
812 | u64 hw_nmi_get_sample_period(int watchdog_thresh) | |
813 | { | |
814 | return ppc_proc_freq * watchdog_thresh; | |
815 | } | |
816 | ||
817 | /* | |
818 | * The hardlockup detector breaks PMU event based branches and is likely | |
819 | * to get false positives in KVM guests, so disable it by default. | |
820 | */ | |
821 | static int __init disable_hardlockup_detector(void) | |
822 | { | |
d19d5efd | 823 | hardlockup_detector_disable(); |
c54b2bf1 AB |
824 | |
825 | return 0; | |
826 | } | |
827 | early_initcall(disable_hardlockup_detector); | |
828 | #endif |