Commit | Line | Data |
---|---|---|
40ef8cbc PM |
1 | /* |
2 | * | |
3 | * Common boot and setup code. | |
4 | * | |
5 | * Copyright (C) 2001 PPC64 Team, IBM Corp | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #undef DEBUG | |
14 | ||
4b16f8e2 | 15 | #include <linux/export.h> |
40ef8cbc PM |
16 | #include <linux/string.h> |
17 | #include <linux/sched.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/reboot.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/initrd.h> | |
40ef8cbc PM |
23 | #include <linux/seq_file.h> |
24 | #include <linux/ioport.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/utsname.h> | |
27 | #include <linux/tty.h> | |
28 | #include <linux/root_dev.h> | |
29 | #include <linux/notifier.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/unistd.h> | |
32 | #include <linux/serial.h> | |
33 | #include <linux/serial_8250.h> | |
7a0268fa | 34 | #include <linux/bootmem.h> |
12d04eef | 35 | #include <linux/pci.h> |
945feb17 | 36 | #include <linux/lockdep.h> |
95f72d1e | 37 | #include <linux/memblock.h> |
40ef8cbc | 38 | #include <asm/io.h> |
0cc4746c | 39 | #include <asm/kdump.h> |
40ef8cbc PM |
40 | #include <asm/prom.h> |
41 | #include <asm/processor.h> | |
42 | #include <asm/pgtable.h> | |
40ef8cbc PM |
43 | #include <asm/smp.h> |
44 | #include <asm/elf.h> | |
45 | #include <asm/machdep.h> | |
46 | #include <asm/paca.h> | |
40ef8cbc PM |
47 | #include <asm/time.h> |
48 | #include <asm/cputable.h> | |
49 | #include <asm/sections.h> | |
50 | #include <asm/btext.h> | |
51 | #include <asm/nvram.h> | |
52 | #include <asm/setup.h> | |
53 | #include <asm/system.h> | |
54 | #include <asm/rtas.h> | |
55 | #include <asm/iommu.h> | |
56 | #include <asm/serial.h> | |
57 | #include <asm/cache.h> | |
58 | #include <asm/page.h> | |
59 | #include <asm/mmu.h> | |
40ef8cbc | 60 | #include <asm/firmware.h> |
f78541dc | 61 | #include <asm/xmon.h> |
dcad47fc | 62 | #include <asm/udbg.h> |
593e537b | 63 | #include <asm/kexec.h> |
25d21ad6 | 64 | #include <asm/mmu_context.h> |
d36b4c4f | 65 | #include <asm/code-patching.h> |
aa04b4cc | 66 | #include <asm/kvm_ppc.h> |
40ef8cbc | 67 | |
66ba135c SR |
68 | #include "setup.h" |
69 | ||
40ef8cbc PM |
70 | #ifdef DEBUG |
71 | #define DBG(fmt...) udbg_printf(fmt) | |
72 | #else | |
73 | #define DBG(fmt...) | |
74 | #endif | |
75 | ||
40ef8cbc | 76 | int boot_cpuid = 0; |
7ac87abb | 77 | int __initdata spinning_secondaries; |
40ef8cbc PM |
78 | u64 ppc64_pft_size; |
79 | ||
dabcafd3 OJ |
80 | /* Pick defaults since we might want to patch instructions |
81 | * before we've read this from the device tree. | |
82 | */ | |
83 | struct ppc64_caches ppc64_caches = { | |
5a2fe38d OJ |
84 | .dline_size = 0x40, |
85 | .log_dline_size = 6, | |
86 | .iline_size = 0x40, | |
87 | .log_iline_size = 6 | |
dabcafd3 | 88 | }; |
40ef8cbc PM |
89 | EXPORT_SYMBOL_GPL(ppc64_caches); |
90 | ||
91 | /* | |
92 | * These are used in binfmt_elf.c to put aux entries on the stack | |
93 | * for each elf executable being started. | |
94 | */ | |
95 | int dcache_bsize; | |
96 | int icache_bsize; | |
97 | int ucache_bsize; | |
98 | ||
40ef8cbc PM |
99 | #ifdef CONFIG_SMP |
100 | ||
954e6da5 | 101 | static char *smt_enabled_cmdline; |
40ef8cbc PM |
102 | |
103 | /* Look for ibm,smt-enabled OF option */ | |
104 | static void check_smt_enabled(void) | |
105 | { | |
106 | struct device_node *dn; | |
a7f67bdf | 107 | const char *smt_option; |
40ef8cbc | 108 | |
954e6da5 NF |
109 | /* Default to enabling all threads */ |
110 | smt_enabled_at_boot = threads_per_core; | |
40ef8cbc | 111 | |
954e6da5 NF |
112 | /* Allow the command line to overrule the OF option */ |
113 | if (smt_enabled_cmdline) { | |
114 | if (!strcmp(smt_enabled_cmdline, "on")) | |
115 | smt_enabled_at_boot = threads_per_core; | |
116 | else if (!strcmp(smt_enabled_cmdline, "off")) | |
117 | smt_enabled_at_boot = 0; | |
118 | else { | |
119 | long smt; | |
120 | int rc; | |
121 | ||
122 | rc = strict_strtol(smt_enabled_cmdline, 10, &smt); | |
123 | if (!rc) | |
124 | smt_enabled_at_boot = | |
125 | min(threads_per_core, (int)smt); | |
126 | } | |
127 | } else { | |
128 | dn = of_find_node_by_path("/options"); | |
129 | if (dn) { | |
130 | smt_option = of_get_property(dn, "ibm,smt-enabled", | |
131 | NULL); | |
132 | ||
133 | if (smt_option) { | |
134 | if (!strcmp(smt_option, "on")) | |
135 | smt_enabled_at_boot = threads_per_core; | |
136 | else if (!strcmp(smt_option, "off")) | |
137 | smt_enabled_at_boot = 0; | |
138 | } | |
139 | ||
140 | of_node_put(dn); | |
141 | } | |
142 | } | |
40ef8cbc PM |
143 | } |
144 | ||
145 | /* Look for smt-enabled= cmdline option */ | |
146 | static int __init early_smt_enabled(char *p) | |
147 | { | |
954e6da5 | 148 | smt_enabled_cmdline = p; |
40ef8cbc PM |
149 | return 0; |
150 | } | |
151 | early_param("smt-enabled", early_smt_enabled); | |
152 | ||
5ad57078 PM |
153 | #else |
154 | #define check_smt_enabled() | |
40ef8cbc PM |
155 | #endif /* CONFIG_SMP */ |
156 | ||
40ef8cbc PM |
157 | /* |
158 | * Early initialization entry point. This is called by head.S | |
159 | * with MMU translation disabled. We rely on the "feature" of | |
160 | * the CPU that ignores the top 2 bits of the address in real | |
161 | * mode so we can access kernel globals normally provided we | |
162 | * only toy with things in the RMO region. From here, we do | |
95f72d1e | 163 | * some early parsing of the device-tree to setup out MEMBLOCK |
40ef8cbc PM |
164 | * data structures, and allocate & initialize the hash table |
165 | * and segment tables so we can start running with translation | |
166 | * enabled. | |
167 | * | |
168 | * It is this function which will call the probe() callback of | |
169 | * the various platform types and copy the matching one to the | |
170 | * global ppc_md structure. Your platform can eventually do | |
171 | * some very early initializations from the probe() routine, but | |
172 | * this is not recommended, be very careful as, for example, the | |
173 | * device-tree is not accessible via normal means at this point. | |
174 | */ | |
175 | ||
176 | void __init early_setup(unsigned long dt_ptr) | |
177 | { | |
24d96495 BH |
178 | /* -------- printk is _NOT_ safe to use here ! ------- */ |
179 | ||
42c4aaad | 180 | /* Identify CPU type */ |
974a76f5 | 181 | identify_cpu(0, mfspr(SPRN_PVR)); |
42c4aaad | 182 | |
33dbcf72 | 183 | /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ |
1426d5a3 ME |
184 | initialise_paca(&boot_paca, 0); |
185 | setup_paca(&boot_paca); | |
33dbcf72 | 186 | |
945feb17 BH |
187 | /* Initialize lockdep early or else spinlocks will blow */ |
188 | lockdep_init(); | |
189 | ||
24d96495 BH |
190 | /* -------- printk is now safe to use ------- */ |
191 | ||
f2fd2513 BH |
192 | /* Enable early debugging if any specified (see udbg.h) */ |
193 | udbg_early_init(); | |
194 | ||
e8222502 | 195 | DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); |
40ef8cbc | 196 | |
40ef8cbc | 197 | /* |
3c607ce2 LV |
198 | * Do early initialization using the flattened device |
199 | * tree, such as retrieving the physical memory map or | |
200 | * calculating/retrieving the hash table size. | |
40ef8cbc PM |
201 | */ |
202 | early_init_devtree(__va(dt_ptr)); | |
203 | ||
4df20460 | 204 | /* Now we know the logical id of our boot cpu, setup the paca. */ |
1426d5a3 | 205 | setup_paca(&paca[boot_cpuid]); |
4df20460 AB |
206 | |
207 | /* Fix up paca fields required for the boot cpu */ | |
208 | get_paca()->cpu_start = 1; | |
4df20460 | 209 | |
e8222502 BH |
210 | /* Probe the machine type */ |
211 | probe_machine(); | |
40ef8cbc | 212 | |
47310413 | 213 | setup_kdump_trampoline(); |
0cc4746c | 214 | |
40ef8cbc PM |
215 | DBG("Found, Initializing memory management...\n"); |
216 | ||
757c74d2 BH |
217 | /* Initialize the hash table or TLB handling */ |
218 | early_init_mmu(); | |
40ef8cbc PM |
219 | |
220 | DBG(" <- early_setup()\n"); | |
221 | } | |
222 | ||
799d6046 PM |
223 | #ifdef CONFIG_SMP |
224 | void early_setup_secondary(void) | |
225 | { | |
d04c56f7 | 226 | /* Mark interrupts enabled in PACA */ |
757c74d2 | 227 | get_paca()->soft_enabled = 0; |
799d6046 | 228 | |
757c74d2 BH |
229 | /* Initialize the hash table or TLB handling */ |
230 | early_init_mmu_secondary(); | |
799d6046 PM |
231 | } |
232 | ||
233 | #endif /* CONFIG_SMP */ | |
40ef8cbc | 234 | |
b8f51021 ME |
235 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
236 | void smp_release_cpus(void) | |
237 | { | |
758438a7 | 238 | unsigned long *ptr; |
9d07bc84 | 239 | int i; |
b8f51021 ME |
240 | |
241 | DBG(" -> smp_release_cpus()\n"); | |
242 | ||
243 | /* All secondary cpus are spinning on a common spinloop, release them | |
244 | * all now so they can start to spin on their individual paca | |
245 | * spinloops. For non SMP kernels, the secondary cpus never get out | |
246 | * of the common spinloop. | |
1f6a93e4 | 247 | */ |
b8f51021 | 248 | |
758438a7 ME |
249 | ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop |
250 | - PHYSICAL_START); | |
1f6a93e4 | 251 | *ptr = __pa(generic_secondary_smp_init); |
9d07bc84 BH |
252 | |
253 | /* And wait a bit for them to catch up */ | |
254 | for (i = 0; i < 100000; i++) { | |
255 | mb(); | |
256 | HMT_low(); | |
7ac87abb | 257 | if (spinning_secondaries == 0) |
9d07bc84 BH |
258 | break; |
259 | udelay(1); | |
260 | } | |
7ac87abb | 261 | DBG("spinning_secondaries = %d\n", spinning_secondaries); |
b8f51021 ME |
262 | |
263 | DBG(" <- smp_release_cpus()\n"); | |
264 | } | |
265 | #endif /* CONFIG_SMP || CONFIG_KEXEC */ | |
266 | ||
40ef8cbc | 267 | /* |
799d6046 PM |
268 | * Initialize some remaining members of the ppc64_caches and systemcfg |
269 | * structures | |
40ef8cbc PM |
270 | * (at least until we get rid of them completely). This is mostly some |
271 | * cache informations about the CPU that will be used by cache flush | |
272 | * routines and/or provided to userland | |
273 | */ | |
274 | static void __init initialize_cache_info(void) | |
275 | { | |
276 | struct device_node *np; | |
277 | unsigned long num_cpus = 0; | |
278 | ||
279 | DBG(" -> initialize_cache_info()\n"); | |
280 | ||
94db7c5e | 281 | for_each_node_by_type(np, "cpu") { |
40ef8cbc PM |
282 | num_cpus += 1; |
283 | ||
dfbe93a2 AB |
284 | /* |
285 | * We're assuming *all* of the CPUs have the same | |
40ef8cbc PM |
286 | * d-cache and i-cache sizes... -Peter |
287 | */ | |
dfbe93a2 | 288 | if (num_cpus == 1) { |
a7f67bdf | 289 | const u32 *sizep, *lsizep; |
40ef8cbc | 290 | u32 size, lsize; |
40ef8cbc PM |
291 | |
292 | size = 0; | |
293 | lsize = cur_cpu_spec->dcache_bsize; | |
e2eb6392 | 294 | sizep = of_get_property(np, "d-cache-size", NULL); |
40ef8cbc PM |
295 | if (sizep != NULL) |
296 | size = *sizep; | |
dfbe93a2 AB |
297 | lsizep = of_get_property(np, "d-cache-block-size", |
298 | NULL); | |
20474abd BH |
299 | /* fallback if block size missing */ |
300 | if (lsizep == NULL) | |
dfbe93a2 AB |
301 | lsizep = of_get_property(np, |
302 | "d-cache-line-size", | |
303 | NULL); | |
40ef8cbc PM |
304 | if (lsizep != NULL) |
305 | lsize = *lsizep; | |
306 | if (sizep == 0 || lsizep == 0) | |
307 | DBG("Argh, can't find dcache properties ! " | |
308 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
309 | ||
a7f290da BH |
310 | ppc64_caches.dsize = size; |
311 | ppc64_caches.dline_size = lsize; | |
40ef8cbc PM |
312 | ppc64_caches.log_dline_size = __ilog2(lsize); |
313 | ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; | |
314 | ||
315 | size = 0; | |
316 | lsize = cur_cpu_spec->icache_bsize; | |
e2eb6392 | 317 | sizep = of_get_property(np, "i-cache-size", NULL); |
40ef8cbc PM |
318 | if (sizep != NULL) |
319 | size = *sizep; | |
dfbe93a2 AB |
320 | lsizep = of_get_property(np, "i-cache-block-size", |
321 | NULL); | |
20474abd | 322 | if (lsizep == NULL) |
dfbe93a2 AB |
323 | lsizep = of_get_property(np, |
324 | "i-cache-line-size", | |
325 | NULL); | |
40ef8cbc PM |
326 | if (lsizep != NULL) |
327 | lsize = *lsizep; | |
328 | if (sizep == 0 || lsizep == 0) | |
329 | DBG("Argh, can't find icache properties ! " | |
330 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
331 | ||
a7f290da BH |
332 | ppc64_caches.isize = size; |
333 | ppc64_caches.iline_size = lsize; | |
40ef8cbc PM |
334 | ppc64_caches.log_iline_size = __ilog2(lsize); |
335 | ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; | |
336 | } | |
337 | } | |
338 | ||
40ef8cbc PM |
339 | DBG(" <- initialize_cache_info()\n"); |
340 | } | |
341 | ||
40ef8cbc PM |
342 | |
343 | /* | |
344 | * Do some initial setup of the system. The parameters are those which | |
345 | * were passed in from the bootloader. | |
346 | */ | |
347 | void __init setup_system(void) | |
348 | { | |
349 | DBG(" -> setup_system()\n"); | |
350 | ||
826ea8f2 TB |
351 | /* Apply the CPUs-specific and firmware specific fixups to kernel |
352 | * text (nop out sections not relevant to this CPU or this firmware) | |
42c4aaad | 353 | */ |
0909c8c2 | 354 | do_feature_fixups(cur_cpu_spec->cpu_features, |
42c4aaad | 355 | &__start___ftr_fixup, &__stop___ftr_fixup); |
7c03d653 BH |
356 | do_feature_fixups(cur_cpu_spec->mmu_features, |
357 | &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); | |
826ea8f2 TB |
358 | do_feature_fixups(powerpc_firmware_features, |
359 | &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); | |
2d1b2027 KG |
360 | do_lwsync_fixups(cur_cpu_spec->cpu_features, |
361 | &__start___lwsync_fixup, &__stop___lwsync_fixup); | |
d715e433 | 362 | do_final_fixups(); |
42c4aaad | 363 | |
40ef8cbc PM |
364 | /* |
365 | * Unflatten the device-tree passed by prom_init or kexec | |
366 | */ | |
367 | unflatten_device_tree(); | |
368 | ||
369 | /* | |
370 | * Fill the ppc64_caches & systemcfg structures with informations | |
0ebfff14 | 371 | * retrieved from the device-tree. |
40ef8cbc PM |
372 | */ |
373 | initialize_cache_info(); | |
374 | ||
375 | #ifdef CONFIG_PPC_RTAS | |
376 | /* | |
377 | * Initialize RTAS if available | |
378 | */ | |
379 | rtas_initialize(); | |
380 | #endif /* CONFIG_PPC_RTAS */ | |
40ef8cbc PM |
381 | |
382 | /* | |
383 | * Check if we have an initrd provided via the device-tree | |
384 | */ | |
385 | check_for_initrd(); | |
40ef8cbc PM |
386 | |
387 | /* | |
388 | * Do some platform specific early initializations, that includes | |
389 | * setting up the hash table pointers. It also sets up some interrupt-mapping | |
390 | * related options that will be used by finish_device_tree() | |
391 | */ | |
57744ea9 GL |
392 | if (ppc_md.init_early) |
393 | ppc_md.init_early(); | |
40ef8cbc | 394 | |
463ce0e1 BH |
395 | /* |
396 | * We can discover serial ports now since the above did setup the | |
397 | * hash table management for us, thus ioremap works. We do that early | |
398 | * so that further code can be debugged | |
399 | */ | |
463ce0e1 | 400 | find_legacy_serial_ports(); |
463ce0e1 | 401 | |
40ef8cbc PM |
402 | /* |
403 | * Register early console | |
404 | */ | |
405 | register_early_udbg_console(); | |
40ef8cbc | 406 | |
47679283 ME |
407 | /* |
408 | * Initialize xmon | |
409 | */ | |
410 | xmon_setup(); | |
480f6f35 | 411 | |
5ad57078 | 412 | smp_setup_cpu_maps(); |
954e6da5 | 413 | check_smt_enabled(); |
40ef8cbc | 414 | |
f018b36f | 415 | #ifdef CONFIG_SMP |
40ef8cbc PM |
416 | /* Release secondary cpus out of their spinloops at 0x60 now that |
417 | * we can map physical -> logical CPU ids | |
418 | */ | |
419 | smp_release_cpus(); | |
f018b36f | 420 | #endif |
40ef8cbc | 421 | |
96b644bd | 422 | printk("Starting Linux PPC64 %s\n", init_utsname()->version); |
40ef8cbc PM |
423 | |
424 | printk("-----------------------------------------------------\n"); | |
fe333321 | 425 | printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); |
95f72d1e | 426 | printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size()); |
9697add0 AB |
427 | if (ppc64_caches.dline_size != 0x80) |
428 | printk("ppc64_caches.dcache_line_size = 0x%x\n", | |
429 | ppc64_caches.dline_size); | |
430 | if (ppc64_caches.iline_size != 0x80) | |
431 | printk("ppc64_caches.icache_line_size = 0x%x\n", | |
432 | ppc64_caches.iline_size); | |
94491685 | 433 | #ifdef CONFIG_PPC_STD_MMU_64 |
9697add0 AB |
434 | if (htab_address) |
435 | printk("htab_address = 0x%p\n", htab_address); | |
40ef8cbc | 436 | printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); |
94491685 | 437 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
b160544c | 438 | if (PHYSICAL_START > 0) |
e468455e ME |
439 | printk("physical_start = 0x%llx\n", |
440 | (unsigned long long)PHYSICAL_START); | |
40ef8cbc | 441 | printk("-----------------------------------------------------\n"); |
40ef8cbc | 442 | |
40ef8cbc PM |
443 | DBG(" <- setup_system()\n"); |
444 | } | |
445 | ||
40bd587a BH |
446 | /* This returns the limit below which memory accesses to the linear |
447 | * mapping are guarnateed not to cause a TLB or SLB miss. This is | |
448 | * used to allocate interrupt or emergency stacks for which our | |
449 | * exception entry path doesn't deal with being interrupted. | |
450 | */ | |
451 | static u64 safe_stack_limit(void) | |
095c7965 | 452 | { |
40bd587a BH |
453 | #ifdef CONFIG_PPC_BOOK3E |
454 | /* Freescale BookE bolts the entire linear mapping */ | |
455 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) | |
456 | return linear_map_top; | |
457 | /* Other BookE, we assume the first GB is bolted */ | |
458 | return 1ul << 30; | |
459 | #else | |
460 | /* BookS, the first segment is bolted */ | |
461 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) | |
095c7965 | 462 | return 1UL << SID_SHIFT_1T; |
095c7965 | 463 | return 1UL << SID_SHIFT; |
40bd587a | 464 | #endif |
095c7965 AB |
465 | } |
466 | ||
40ef8cbc PM |
467 | static void __init irqstack_early_init(void) |
468 | { | |
40bd587a | 469 | u64 limit = safe_stack_limit(); |
40ef8cbc PM |
470 | unsigned int i; |
471 | ||
472 | /* | |
8f4da26e AB |
473 | * Interrupt stacks must be in the first segment since we |
474 | * cannot afford to take SLB misses on them. | |
40ef8cbc | 475 | */ |
0e551954 | 476 | for_each_possible_cpu(i) { |
3c726f8d | 477 | softirq_ctx[i] = (struct thread_info *) |
95f72d1e | 478 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 479 | THREAD_SIZE, limit)); |
3c726f8d | 480 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 481 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 482 | THREAD_SIZE, limit)); |
40ef8cbc PM |
483 | } |
484 | } | |
40ef8cbc | 485 | |
2d27cfd3 BH |
486 | #ifdef CONFIG_PPC_BOOK3E |
487 | static void __init exc_lvl_early_init(void) | |
488 | { | |
d36b4c4f KG |
489 | extern unsigned int interrupt_base_book3e; |
490 | extern unsigned int exc_debug_debug_book3e; | |
491 | ||
2d27cfd3 BH |
492 | unsigned int i; |
493 | ||
494 | for_each_possible_cpu(i) { | |
495 | critirq_ctx[i] = (struct thread_info *) | |
95f72d1e | 496 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
2d27cfd3 | 497 | dbgirq_ctx[i] = (struct thread_info *) |
95f72d1e | 498 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
2d27cfd3 | 499 | mcheckirq_ctx[i] = (struct thread_info *) |
95f72d1e | 500 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
2d27cfd3 | 501 | } |
d36b4c4f KG |
502 | |
503 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) | |
504 | patch_branch(&interrupt_base_book3e + (0x040 / 4) + 1, | |
505 | (unsigned long)&exc_debug_debug_book3e, 0); | |
2d27cfd3 BH |
506 | } |
507 | #else | |
508 | #define exc_lvl_early_init() | |
509 | #endif | |
510 | ||
40ef8cbc PM |
511 | /* |
512 | * Stack space used when we detect a bad kernel stack pointer, and | |
513 | * early in SMP boots before relocation is enabled. | |
514 | */ | |
515 | static void __init emergency_stack_init(void) | |
516 | { | |
095c7965 | 517 | u64 limit; |
40ef8cbc PM |
518 | unsigned int i; |
519 | ||
520 | /* | |
521 | * Emergency stacks must be under 256MB, we cannot afford to take | |
522 | * SLB misses on them. The ABI also requires them to be 128-byte | |
523 | * aligned. | |
524 | * | |
525 | * Since we use these as temporary stacks during secondary CPU | |
526 | * bringup, we need to get at them in real mode. This means they | |
527 | * must also be within the RMO region. | |
528 | */ | |
40bd587a | 529 | limit = min(safe_stack_limit(), ppc64_rma_size); |
40ef8cbc | 530 | |
3243d874 ME |
531 | for_each_possible_cpu(i) { |
532 | unsigned long sp; | |
95f72d1e | 533 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); |
3243d874 ME |
534 | sp += THREAD_SIZE; |
535 | paca[i].emergency_sp = __va(sp); | |
536 | } | |
40ef8cbc PM |
537 | } |
538 | ||
40ef8cbc | 539 | /* |
0f6b77ca AIB |
540 | * Called into from start_kernel this initializes bootmem, which is used |
541 | * to manage page allocation until mem_init is called. | |
40ef8cbc PM |
542 | */ |
543 | void __init setup_arch(char **cmdline_p) | |
544 | { | |
40ef8cbc PM |
545 | ppc64_boot_msg(0x12, "Setup Arch"); |
546 | ||
547 | *cmdline_p = cmd_line; | |
548 | ||
549 | /* | |
550 | * Set cache line size based on type of cpu as a default. | |
551 | * Systems with OF can look in the properties on the cpu node(s) | |
552 | * for a possibly more accurate value. | |
553 | */ | |
554 | dcache_bsize = ppc64_caches.dline_size; | |
555 | icache_bsize = ppc64_caches.iline_size; | |
556 | ||
557 | /* reboot on panic */ | |
558 | panic_timeout = 180; | |
40ef8cbc PM |
559 | |
560 | if (ppc_md.panic) | |
7e990266 | 561 | setup_panic(); |
40ef8cbc | 562 | |
4846c5de | 563 | init_mm.start_code = (unsigned long)_stext; |
40ef8cbc PM |
564 | init_mm.end_code = (unsigned long) _etext; |
565 | init_mm.end_data = (unsigned long) _edata; | |
566 | init_mm.brk = klimit; | |
567 | ||
568 | irqstack_early_init(); | |
2d27cfd3 | 569 | exc_lvl_early_init(); |
40ef8cbc PM |
570 | emergency_stack_init(); |
571 | ||
94491685 | 572 | #ifdef CONFIG_PPC_STD_MMU_64 |
40ef8cbc | 573 | stabs_alloc(); |
94491685 | 574 | #endif |
40ef8cbc PM |
575 | /* set up the bootmem stuff with available memory */ |
576 | do_init_bootmem(); | |
577 | sparse_init(); | |
578 | ||
0458060c PM |
579 | #ifdef CONFIG_DUMMY_CONSOLE |
580 | conswitchp = &dummy_con; | |
581 | #endif | |
582 | ||
38db7e74 GL |
583 | if (ppc_md.setup_arch) |
584 | ppc_md.setup_arch(); | |
40ef8cbc | 585 | |
40ef8cbc | 586 | paging_init(); |
6f0ef0f5 BH |
587 | |
588 | /* Initialize the MMU context management stuff */ | |
589 | mmu_context_init(); | |
590 | ||
aa04b4cc PM |
591 | kvm_rma_init(); |
592 | ||
40ef8cbc PM |
593 | ppc64_boot_msg(0x15, "Setup Done"); |
594 | } | |
595 | ||
596 | ||
597 | /* ToDo: do something useful if ppc_md is not yet setup. */ | |
598 | #define PPC64_LINUX_FUNCTION 0x0f000000 | |
599 | #define PPC64_IPL_MESSAGE 0xc0000000 | |
600 | #define PPC64_TERM_MESSAGE 0xb0000000 | |
601 | ||
602 | static void ppc64_do_msg(unsigned int src, const char *msg) | |
603 | { | |
604 | if (ppc_md.progress) { | |
605 | char buf[128]; | |
606 | ||
607 | sprintf(buf, "%08X\n", src); | |
608 | ppc_md.progress(buf, 0); | |
609 | snprintf(buf, 128, "%s", msg); | |
610 | ppc_md.progress(buf, 0); | |
611 | } | |
612 | } | |
613 | ||
614 | /* Print a boot progress message. */ | |
615 | void ppc64_boot_msg(unsigned int src, const char *msg) | |
616 | { | |
617 | ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg); | |
618 | printk("[boot]%04x %s\n", src, msg); | |
619 | } | |
620 | ||
7a0268fa | 621 | #ifdef CONFIG_SMP |
c2a7e818 TH |
622 | #define PCPU_DYN_SIZE () |
623 | ||
624 | static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) | |
7a0268fa | 625 | { |
c2a7e818 TH |
626 | return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, |
627 | __pa(MAX_DMA_ADDRESS)); | |
628 | } | |
7a0268fa | 629 | |
c2a7e818 TH |
630 | static void __init pcpu_fc_free(void *ptr, size_t size) |
631 | { | |
632 | free_bootmem(__pa(ptr), size); | |
633 | } | |
7a0268fa | 634 | |
c2a7e818 TH |
635 | static int pcpu_cpu_distance(unsigned int from, unsigned int to) |
636 | { | |
637 | if (cpu_to_node(from) == cpu_to_node(to)) | |
638 | return LOCAL_DISTANCE; | |
639 | else | |
640 | return REMOTE_DISTANCE; | |
641 | } | |
642 | ||
ae01f84b AB |
643 | unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; |
644 | EXPORT_SYMBOL(__per_cpu_offset); | |
645 | ||
c2a7e818 TH |
646 | void __init setup_per_cpu_areas(void) |
647 | { | |
648 | const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; | |
649 | size_t atom_size; | |
650 | unsigned long delta; | |
651 | unsigned int cpu; | |
652 | int rc; | |
653 | ||
654 | /* | |
655 | * Linear mapping is one of 4K, 1M and 16M. For 4K, no need | |
656 | * to group units. For larger mappings, use 1M atom which | |
657 | * should be large enough to contain a number of units. | |
658 | */ | |
659 | if (mmu_linear_psize == MMU_PAGE_4K) | |
660 | atom_size = PAGE_SIZE; | |
661 | else | |
662 | atom_size = 1 << 20; | |
663 | ||
664 | rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, | |
665 | pcpu_fc_alloc, pcpu_fc_free); | |
666 | if (rc < 0) | |
667 | panic("cannot initialize percpu area (err=%d)", rc); | |
668 | ||
669 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; | |
ae01f84b AB |
670 | for_each_possible_cpu(cpu) { |
671 | __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; | |
672 | paca[cpu].data_offset = __per_cpu_offset[cpu]; | |
673 | } | |
7a0268fa AB |
674 | } |
675 | #endif | |
4cb3cee0 BH |
676 | |
677 | ||
678 | #ifdef CONFIG_PPC_INDIRECT_IO | |
679 | struct ppc_pci_io ppc_pci_io; | |
680 | EXPORT_SYMBOL(ppc_pci_io); | |
681 | #endif /* CONFIG_PPC_INDIRECT_IO */ | |
682 |