[linux-2.6-block.git] / arch / powerpc / kernel / iommu.c

/*
 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
 * 
 * Rewrite, cleanup, new allocation schemes, virtual merging: 
 * Copyright (C) 2004 Olof Johansson, IBM Corporation
 *               and  Ben. Herrenschmidt, IBM Corporation
 *
 * Dynamic DMA mapping support, bus-independent parts.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 * 
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */


#include <linux/init.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/spinlock.h>
#include <linux/string.h>
#include <linux/dma-mapping.h>
#include <linux/bitops.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/iommu.h>
#include <asm/pci-bridge.h>
#include <asm/machdep.h>
#include <asm/kdump.h>

#define DBG(...)

#ifdef CONFIG_IOMMU_VMERGE
static int novmerge = 0;
#else
static int novmerge = 1;
#endif

static int protect4gb = 1;

static inline unsigned long iommu_num_pages(unsigned long vaddr,
					    unsigned long slen)
{
	unsigned long npages;

	npages = IOMMU_PAGE_ALIGN(vaddr + slen) - (vaddr & IOMMU_PAGE_MASK);
	npages >>= IOMMU_PAGE_SHIFT;

	return npages;
}

static int __init setup_protect4gb(char *str)
{
	if (strcmp(str, "on") == 0)
		protect4gb = 1;
	else if (strcmp(str, "off") == 0)
		protect4gb = 0;

	return 1;
}

static int __init setup_iommu(char *str)
{
	if (!strcmp(str, "novmerge"))
		novmerge = 1;
	else if (!strcmp(str, "vmerge"))
		novmerge = 0;
	return 1;
}

__setup("protect4gb=", setup_protect4gb);
__setup("iommu=", setup_iommu);

static unsigned long iommu_range_alloc(struct iommu_table *tbl,
                                       unsigned long npages,
                                       unsigned long *handle,
                                       unsigned long mask,
                                       unsigned int align_order)
{ 
	unsigned long n, end, i, start;
	unsigned long limit;
	int largealloc = npages > 15;
	int pass = 0;
	unsigned long align_mask;

	align_mask = 0xffffffffffffffffl >> (64 - align_order);

	/* This allocator was derived from x86_64's bit string search */

	/* Sanity check */
	if (unlikely(npages == 0)) {
		if (printk_ratelimit())
			WARN_ON(1);
		return DMA_ERROR_CODE;
	}

	if (handle && *handle)
		start = *handle;
	else
		start = largealloc ? tbl->it_largehint : tbl->it_hint;

	/* Use only half of the table for small allocs (15 pages or less) */
	limit = largealloc ? tbl->it_size : tbl->it_halfpoint;

	if (largealloc && start < tbl->it_halfpoint)
		start = tbl->it_halfpoint;

	/* The case below can happen if we have a small segment appended
	 * to a large, or when the previous alloc was at the very end of
	 * the available space. If so, go back to the initial start.
	 */
	if (start >= limit)
		start = largealloc ? tbl->it_largehint : tbl->it_hint;

 again:

	if (limit + tbl->it_offset > mask) {
		limit = mask - tbl->it_offset + 1;
		/* If we're constrained on address range, first try
		 * at the masked hint to avoid O(n) search complexity,
		 * but on second pass, start at 0.
		 */
		if ((start & mask) >= limit || pass > 0)
			start = 0;
		else
			start &= mask;
	}

	n = find_next_zero_bit(tbl->it_map, limit, start);

	/* Align allocation */
	n = (n + align_mask) & ~align_mask;

	end = n + npages;

	if (unlikely(end >= limit)) {
		if (likely(pass < 2)) {
			/* First failure, just rescan the half of the table.
			 * Second failure, rescan the other half of the table.
			 */
			start = (largealloc ^ pass) ? tbl->it_halfpoint : 0;
			limit = pass ? tbl->it_size : limit;
			pass++;
			goto again;
		} else {
			/* Third failure, give up */
			return DMA_ERROR_CODE;
		}
	}

	for (i = n; i < end; i++)
		if (test_bit(i, tbl->it_map)) {
			start = i+1;
			goto again;
		}

	for (i = n; i < end; i++)
		__set_bit(i, tbl->it_map);

	/* Bump the hint to a new block for small allocs. */
	if (largealloc) {
		/* Don't bump to new block to avoid fragmentation */
		tbl->it_largehint = end;
	} else {
		/* Overflow will be taken care of at the next allocation */
		tbl->it_hint = (end + tbl->it_blocksize - 1) &
		                ~(tbl->it_blocksize - 1);
	}

	/* Update handle for SG allocations */
	if (handle)
		*handle = end;

	return n;
}

static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *page,
		       unsigned int npages, enum dma_data_direction direction,
		       unsigned long mask, unsigned int align_order)
{
	unsigned long entry, flags;
	dma_addr_t ret = DMA_ERROR_CODE;

	spin_lock_irqsave(&(tbl->it_lock), flags);

	entry = iommu_range_alloc(tbl, npages, NULL, mask, align_order);

	if (unlikely(entry == DMA_ERROR_CODE)) {
		spin_unlock_irqrestore(&(tbl->it_lock), flags);
		return DMA_ERROR_CODE;
	}

	entry += tbl->it_offset;	/* Offset into real TCE table */
	ret = entry << IOMMU_PAGE_SHIFT;	/* Set the return dma address */

	/* Put the TCEs in the HW table */
	ppc_md.tce_build(tbl, entry, npages, (unsigned long)page & IOMMU_PAGE_MASK,
			 direction);


	/* Flush/invalidate TLB caches if necessary */
	if (ppc_md.tce_flush)
		ppc_md.tce_flush(tbl);

	spin_unlock_irqrestore(&(tbl->it_lock), flags);

	/* Make sure updates are seen by hardware */
	mb();

	return ret;
}

static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, 
			 unsigned int npages)
{
	unsigned long entry, free_entry;
	unsigned long i;

	entry = dma_addr >> IOMMU_PAGE_SHIFT;
	free_entry = entry - tbl->it_offset;

	if (((free_entry + npages) > tbl->it_size) ||
	    (entry < tbl->it_offset)) {
		if (printk_ratelimit()) {
			printk(KERN_INFO "iommu_free: invalid entry\n");
			printk(KERN_INFO "\tentry     = 0x%lx\n", entry); 
			printk(KERN_INFO "\tdma_addr  = 0x%lx\n", (u64)dma_addr);
			printk(KERN_INFO "\tTable     = 0x%lx\n", (u64)tbl);
			printk(KERN_INFO "\tbus#      = 0x%lx\n", (u64)tbl->it_busno);
			printk(KERN_INFO "\tsize      = 0x%lx\n", (u64)tbl->it_size);
			printk(KERN_INFO "\tstartOff  = 0x%lx\n", (u64)tbl->it_offset);
			printk(KERN_INFO "\tindex     = 0x%lx\n", (u64)tbl->it_index);
			WARN_ON(1);
		}
		return;
	}

	ppc_md.tce_free(tbl, entry, npages);
	
	for (i = 0; i < npages; i++)
		__clear_bit(free_entry+i, tbl->it_map);
}

static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
		unsigned int npages)
{
	unsigned long flags;

	spin_lock_irqsave(&(tbl->it_lock), flags);

	__iommu_free(tbl, dma_addr, npages);

	/* Make sure TLB cache is flushed if the HW needs it. We do
	 * not do an mb() here on purpose, it is not needed on any of
	 * the current platforms.
	 */
	if (ppc_md.tce_flush)
		ppc_md.tce_flush(tbl);

	spin_unlock_irqrestore(&(tbl->it_lock), flags);
}

int iommu_map_sg(struct iommu_table *tbl, struct scatterlist *sglist,
		 int nelems, unsigned long mask,
		 enum dma_data_direction direction)
{
	dma_addr_t dma_next = 0, dma_addr;
	unsigned long flags;
	struct scatterlist *s, *outs, *segstart;
	int outcount, incount, i;
	unsigned int align;
	unsigned long handle;

	BUG_ON(direction == DMA_NONE);

	if ((nelems == 0) || !tbl)
		return 0;

	outs = s = segstart = &sglist[0];
	outcount = 1;
	incount = nelems;
	handle = 0;

	/* Init first segment length for backout at failure */
	outs->dma_length = 0;

	DBG("sg mapping %d elements:\n", nelems);

	spin_lock_irqsave(&(tbl->it_lock), flags);

	for_each_sg(sglist, s, nelems, i) {
		unsigned long vaddr, npages, entry, slen;

		slen = s->length;
		/* Sanity check */
		if (slen == 0) {
			dma_next = 0;
			continue;
		}
		/* Allocate iommu entries for that segment */
		vaddr = (unsigned long) sg_virt(s);
		npages = iommu_num_pages(vaddr, slen);
		align = 0;
		if (IOMMU_PAGE_SHIFT < PAGE_SHIFT && slen >= PAGE_SIZE &&
		    (vaddr & ~PAGE_MASK) == 0)
			align = PAGE_SHIFT - IOMMU_PAGE_SHIFT;
		entry = iommu_range_alloc(tbl, npages, &handle,
					  mask >> IOMMU_PAGE_SHIFT, align);

		DBG("  - vaddr: %lx, size: %lx\n", vaddr, slen);

		/* Handle failure */
		if (unlikely(entry == DMA_ERROR_CODE)) {
			if (printk_ratelimit())
				printk(KERN_INFO "iommu_alloc failed, tbl %p vaddr %lx"
				       " npages %lx\n", tbl, vaddr, npages);
			goto failure;
		}

		/* Convert entry to a dma_addr_t */
		entry += tbl->it_offset;
		dma_addr = entry << IOMMU_PAGE_SHIFT;
		dma_addr |= (s->offset & ~IOMMU_PAGE_MASK);

		DBG("  - %lu pages, entry: %lx, dma_addr: %lx\n",
			    npages, entry, dma_addr);

		/* Insert into HW table */
		ppc_md.tce_build(tbl, entry, npages, vaddr & IOMMU_PAGE_MASK, direction);

		/* If we are in an open segment, try merging */
		if (segstart != s) {
			DBG("  - trying merge...\n");
			/* We cannot merge if:
			 * - allocated dma_addr isn't contiguous to previous allocation
			 */
			if (novmerge || (dma_addr != dma_next)) {
				/* Can't merge: create a new segment */
				segstart = s;
				outcount++;
				outs = sg_next(outs);
				DBG("    can't merge, new segment.\n");
			} else {
				outs->dma_length += s->length;
				DBG("    merged, new len: %ux\n", outs->dma_length);
			}
		}

		if (segstart == s) {
			/* This is a new segment, fill entries */
			DBG("  - filling new segment.\n");
			outs->dma_address = dma_addr;
			outs->dma_length = slen;
		}

		/* Calculate next page pointer for contiguous check */
		dma_next = dma_addr + slen;

		DBG("  - dma next is: %lx\n", dma_next);
	}

	/* Flush/invalidate TLB caches if necessary */
	if (ppc_md.tce_flush)
		ppc_md.tce_flush(tbl);

	spin_unlock_irqrestore(&(tbl->it_lock), flags);

	DBG("mapped %d elements:\n", outcount);

	/* For the sake of iommu_unmap_sg, we clear out the length in the
	 * next entry of the sglist if we didn't fill the list completely
	 */
	if (outcount < incount) {
		outs = sg_next(outs);
		outs->dma_address = DMA_ERROR_CODE;
		outs->dma_length = 0;
	}

	/* Make sure updates are seen by hardware */
	mb();

	return outcount;

 failure:
	for_each_sg(sglist, s, nelems, i) {
		if (s->dma_length != 0) {
			unsigned long vaddr, npages;

			vaddr = s->dma_address & IOMMU_PAGE_MASK;
			npages = iommu_num_pages(s->dma_address, s->dma_length);
			__iommu_free(tbl, vaddr, npages);
			s->dma_address = DMA_ERROR_CODE;
			s->dma_length = 0;
		}
		if (s == outs)
			break;
	}
	spin_unlock_irqrestore(&(tbl->it_lock), flags);
	return 0;
}


void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
		int nelems, enum dma_data_direction direction)
{
	struct scatterlist *sg;
	unsigned long flags;

	BUG_ON(direction == DMA_NONE);

	if (!tbl)
		return;

	spin_lock_irqsave(&(tbl->it_lock), flags);

	sg = sglist;
	while (nelems--) {
		unsigned int npages;
		dma_addr_t dma_handle = sg->dma_address;

		if (sg->dma_length == 0)
			break;
		npages = iommu_num_pages(dma_handle, sg->dma_length);
		__iommu_free(tbl, dma_handle, npages);
		sg = sg_next(sg);
	}

	/* Flush/invalidate TLBs if necessary. As for iommu_free(), we
	 * do not do an mb() here, the affected platforms do not need it
	 * when freeing.
	 */
	if (ppc_md.tce_flush)
		ppc_md.tce_flush(tbl);

	spin_unlock_irqrestore(&(tbl->it_lock), flags);
}

/*
 * Build a iommu_table structure.  This contains a bit map which
 * is used to manage allocation of the tce space.
 */
struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid)
{
	unsigned long sz;
	unsigned long start_index, end_index;
	unsigned long entries_per_4g;
	unsigned long index;
	static int welcomed = 0;
	struct page *page;

	/* Set aside 1/4 of the table for large allocations. */
	tbl->it_halfpoint = tbl->it_size * 3 / 4;

	/* number of bytes needed for the bitmap */
	sz = (tbl->it_size + 7) >> 3;

	page = alloc_pages_node(nid, GFP_ATOMIC, get_order(sz));
	if (!page)
		panic("iommu_init_table: Can't allocate %ld bytes\n", sz);
	tbl->it_map = page_address(page);
	memset(tbl->it_map, 0, sz);

	tbl->it_hint = 0;
	tbl->it_largehint = tbl->it_halfpoint;
	spin_lock_init(&tbl->it_lock);

#ifdef CONFIG_CRASH_DUMP
	if (ppc_md.tce_get) {
		unsigned long tceval;
		unsigned long tcecount = 0;

		/*
		 * Reserve the existing mappings left by the first kernel.
		 */
		for (index = 0; index < tbl->it_size; index++) {
			tceval = ppc_md.tce_get(tbl, index + tbl->it_offset);
			/*
			 * Freed TCE entry contains 0x7fffffffffffffff on JS20
			 */
			if (tceval && (tceval != 0x7fffffffffffffffUL)) {
				__set_bit(index, tbl->it_map);
				tcecount++;
			}
		}
		if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) {
			printk(KERN_WARNING "TCE table is full; ");
			printk(KERN_WARNING "freeing %d entries for the kdump boot\n",
				KDUMP_MIN_TCE_ENTRIES);
			for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES;
				index < tbl->it_size; index++)
				__clear_bit(index, tbl->it_map);
		}
	}
#else
	/* Clear the hardware table in case firmware left allocations in it */
	ppc_md.tce_free(tbl, tbl->it_offset, tbl->it_size);
#endif

	/*
	 * DMA cannot cross 4 GB boundary.  Mark last entry of each 4
	 * GB chunk as reserved.
	 */
	if (protect4gb) {
		entries_per_4g = 0x100000000l >> IOMMU_PAGE_SHIFT;

		/* Mark the last bit before a 4GB boundary as used */
		start_index = tbl->it_offset | (entries_per_4g - 1);
		start_index -= tbl->it_offset;

		end_index = tbl->it_size;

		for (index = start_index; index < end_index - 1; index += entries_per_4g)
			__set_bit(index, tbl->it_map);
	}

	if (!welcomed) {
		printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n",
		       novmerge ? "disabled" : "enabled");
		welcomed = 1;
	}

	return tbl;
}

void iommu_free_table(struct iommu_table *tbl, const char *node_name)
{
	unsigned long bitmap_sz, i;
	unsigned int order;

	if (!tbl || !tbl->it_map) {
		printk(KERN_ERR "%s: expected TCE map for %s\n", __FUNCTION__,
				node_name);
		return;
	}

	/* verify that table contains no entries */
	/* it_size is in entries, and we're examining 64 at a time */
	for (i = 0; i < (tbl->it_size/64); i++) {
		if (tbl->it_map[i] != 0) {
			printk(KERN_WARNING "%s: Unexpected TCEs for %s\n",
				__FUNCTION__, node_name);
			break;
		}
	}

	/* calculate bitmap size in bytes */
	bitmap_sz = (tbl->it_size + 7) / 8;

	/* free bitmap */
	order = get_order(bitmap_sz);
	free_pages((unsigned long) tbl->it_map, order);

	/* free table */
	kfree(tbl);
}

/* Creates TCEs for a user provided buffer.  The user buffer must be
 * contiguous real kernel storage (not vmalloc).  The address of the buffer
 * passed here is the kernel (virtual) address of the buffer.  The buffer
 * need not be page aligned, the dma_addr_t returned will point to the same
 * byte within the page as vaddr.
 */
dma_addr_t iommu_map_single(struct iommu_table *tbl, void *vaddr,
		size_t size, unsigned long mask,
		enum dma_data_direction direction)
{
	dma_addr_t dma_handle = DMA_ERROR_CODE;
	unsigned long uaddr;
	unsigned int npages, align;

	BUG_ON(direction == DMA_NONE);

	uaddr = (unsigned long)vaddr;
	npages = iommu_num_pages(uaddr, size);

	if (tbl) {
		align = 0;
		if (IOMMU_PAGE_SHIFT < PAGE_SHIFT && size >= PAGE_SIZE &&
		    ((unsigned long)vaddr & ~PAGE_MASK) == 0)
			align = PAGE_SHIFT - IOMMU_PAGE_SHIFT;

		dma_handle = iommu_alloc(tbl, vaddr, npages, direction,
					 mask >> IOMMU_PAGE_SHIFT, align);
		if (dma_handle == DMA_ERROR_CODE) {
			if (printk_ratelimit())  {
				printk(KERN_INFO "iommu_alloc failed, "
						"tbl %p vaddr %p npages %d\n",
						tbl, vaddr, npages);
			}
		} else
			dma_handle |= (uaddr & ~IOMMU_PAGE_MASK);
	}

	return dma_handle;
}

void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
		size_t size, enum dma_data_direction direction)
{
	unsigned int npages;

	BUG_ON(direction == DMA_NONE);

	if (tbl) {
		npages = iommu_num_pages(dma_handle, size);
		iommu_free(tbl, dma_handle, npages);
	}
}

/* Allocates a contiguous real buffer and creates mappings over it.
 * Returns the virtual address of the buffer and sets dma_handle
 * to the dma address (mapping) of the first page.
 */
void *iommu_alloc_coherent(struct iommu_table *tbl, size_t size,
		dma_addr_t *dma_handle, unsigned long mask, gfp_t flag, int node)
{
	void *ret = NULL;
	dma_addr_t mapping;
	unsigned int order;
	unsigned int nio_pages, io_order;
	struct page *page;

	size = PAGE_ALIGN(size);
	order = get_order(size);

 	/*
	 * Client asked for way too much space.  This is checked later
	 * anyway.  It is easier to debug here for the drivers than in
	 * the tce tables.
	 */
	if (order >= IOMAP_MAX_ORDER) {
		printk("iommu_alloc_consistent size too large: 0x%lx\n", size);
		return NULL;
	}

	if (!tbl)
		return NULL;

	/* Alloc enough pages (and possibly more) */
	page = alloc_pages_node(node, flag, order);
	if (!page)
		return NULL;
	ret = page_address(page);
	memset(ret, 0, size);

	/* Set up tces to cover the allocated range */
	nio_pages = size >> IOMMU_PAGE_SHIFT;
	io_order = get_iommu_order(size);
	mapping = iommu_alloc(tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
			      mask >> IOMMU_PAGE_SHIFT, io_order);
	if (mapping == DMA_ERROR_CODE) {
		free_pages((unsigned long)ret, order);
		return NULL;
	}
	*dma_handle = mapping;
	return ret;
}

void iommu_free_coherent(struct iommu_table *tbl, size_t size,
			 void *vaddr, dma_addr_t dma_handle)
{
	if (tbl) {
		unsigned int nio_pages;

		size = PAGE_ALIGN(size);
		nio_pages = size >> IOMMU_PAGE_SHIFT;
		iommu_free(tbl, dma_handle, nio_pages);
		size = PAGE_ALIGN(size);
		free_pages((unsigned long)vaddr, get_order(size));
	}
}
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
	3	*
	4	* Rewrite, cleanup, new allocation schemes, virtual merging:
	5	* Copyright (C) 2004 Olof Johansson, IBM Corporation
	6	* and Ben. Herrenschmidt, IBM Corporation
	7	*
	8	* Dynamic DMA mapping support, bus-independent parts.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*/
	24
	25
1da177e4 LT	26	#include <linux/init.h>
	27	#include <linux/types.h>
	28	#include <linux/slab.h>
	29	#include <linux/mm.h>
	30	#include <linux/spinlock.h>
	31	#include <linux/string.h>
	32	#include <linux/dma-mapping.h>
1da177e4 LT	33	#include <linux/bitops.h>
	34	#include <asm/io.h>
	35	#include <asm/prom.h>
	36	#include <asm/iommu.h>
	37	#include <asm/pci-bridge.h>
	38	#include <asm/machdep.h>
5f50867b	39	#include <asm/kdump.h>
1da177e4 LT	40
	41	#define DBG(...)
	42
	43	#ifdef CONFIG_IOMMU_VMERGE
	44	static int novmerge = 0;
	45	#else
	46	static int novmerge = 1;
	47	#endif
	48
56997559 JM	49	static int protect4gb = 1;
56997559 JM	50
5d2efba6 LV	51	static inline unsigned long iommu_num_pages(unsigned long vaddr,
	52	unsigned long slen)
	53	{
	54	unsigned long npages;
	55
	56	npages = IOMMU_PAGE_ALIGN(vaddr + slen) - (vaddr & IOMMU_PAGE_MASK);
	57	npages >>= IOMMU_PAGE_SHIFT;
	58
	59	return npages;
	60	}
	61
56997559 JM	62	static int __init setup_protect4gb(char *str)
	63	{
	64	if (strcmp(str, "on") == 0)
	65	protect4gb = 1;
	66	else if (strcmp(str, "off") == 0)
	67	protect4gb = 0;
	68
	69	return 1;
	70	}
	71
1da177e4 LT	72	static int __init setup_iommu(char *str)
	73	{
	74	if (!strcmp(str, "novmerge"))
	75	novmerge = 1;
	76	else if (!strcmp(str, "vmerge"))
	77	novmerge = 0;
	78	return 1;
	79	}
	80
56997559	81	__setup("protect4gb=", setup_protect4gb);
1da177e4 LT	82	__setup("iommu=", setup_iommu);
	83
	84	static unsigned long iommu_range_alloc(struct iommu_table *tbl,
	85	unsigned long npages,
	86	unsigned long *handle,
7daa411b	87	unsigned long mask,
1da177e4 LT	88	unsigned int align_order)
	89	{
	90	unsigned long n, end, i, start;
	91	unsigned long limit;
	92	int largealloc = npages > 15;
	93	int pass = 0;
	94	unsigned long align_mask;
	95
	96	align_mask = 0xffffffffffffffffl >> (64 - align_order);
	97
	98	/* This allocator was derived from x86_64's bit string search */
	99
	100	/* Sanity check */
13a2eea1	101	if (unlikely(npages == 0)) {
1da177e4 LT	102	if (printk_ratelimit())
	103	WARN_ON(1);
	104	return DMA_ERROR_CODE;
	105	}
	106
	107	if (handle && *handle)
	108	start = *handle;
	109	else
	110	start = largealloc ? tbl->it_largehint : tbl->it_hint;
	111
	112	/* Use only half of the table for small allocs (15 pages or less) */
	113	limit = largealloc ? tbl->it_size : tbl->it_halfpoint;
	114
	115	if (largealloc && start < tbl->it_halfpoint)
	116	start = tbl->it_halfpoint;
	117
	118	/* The case below can happen if we have a small segment appended
	119	* to a large, or when the previous alloc was at the very end of
	120	* the available space. If so, go back to the initial start.
	121	*/
	122	if (start >= limit)
	123	start = largealloc ? tbl->it_largehint : tbl->it_hint;
7daa411b	124
1da177e4 LT	125	again:
1da177e4 LT	126
7daa411b OJ	127	if (limit + tbl->it_offset > mask) {
	128	limit = mask - tbl->it_offset + 1;
	129	/* If we're constrained on address range, first try
	130	* at the masked hint to avoid O(n) search complexity,
	131	* but on second pass, start at 0.
	132	*/
	133	if ((start & mask) >= limit \|\| pass > 0)
	134	start = 0;
	135	else
	136	start &= mask;
	137	}
	138
1da177e4 LT	139	n = find_next_zero_bit(tbl->it_map, limit, start);
	140
	141	/* Align allocation */
	142	n = (n + align_mask) & ~align_mask;
	143
	144	end = n + npages;
	145
	146	if (unlikely(end >= limit)) {
	147	if (likely(pass < 2)) {
	148	/* First failure, just rescan the half of the table.
	149	* Second failure, rescan the other half of the table.
	150	*/
	151	start = (largealloc ^ pass) ? tbl->it_halfpoint : 0;
	152	limit = pass ? tbl->it_size : limit;
	153	pass++;
	154	goto again;
	155	} else {
	156	/* Third failure, give up */
	157	return DMA_ERROR_CODE;
	158	}
	159	}
	160
	161	for (i = n; i < end; i++)
	162	if (test_bit(i, tbl->it_map)) {
	163	start = i+1;
	164	goto again;
	165	}
	166
	167	for (i = n; i < end; i++)
	168	__set_bit(i, tbl->it_map);
	169
	170	/* Bump the hint to a new block for small allocs. */
	171	if (largealloc) {
	172	/* Don't bump to new block to avoid fragmentation */
	173	tbl->it_largehint = end;
	174	} else {
	175	/* Overflow will be taken care of at the next allocation */
	176	tbl->it_hint = (end + tbl->it_blocksize - 1) &
	177	~(tbl->it_blocksize - 1);
	178	}
	179
	180	/* Update handle for SG allocations */
	181	if (handle)
	182	*handle = end;
	183
	184	return n;
	185	}
	186
	187	static dma_addr_t iommu_alloc(struct iommu_table tbl, void page,
	188	unsigned int npages, enum dma_data_direction direction,
7daa411b	189	unsigned long mask, unsigned int align_order)
1da177e4 LT	190	{
	191	unsigned long entry, flags;
	192	dma_addr_t ret = DMA_ERROR_CODE;
7daa411b	193
1da177e4 LT	194	spin_lock_irqsave(&(tbl->it_lock), flags);
1da177e4 LT	195
7daa411b	196	entry = iommu_range_alloc(tbl, npages, NULL, mask, align_order);
1da177e4 LT	197
	198	if (unlikely(entry == DMA_ERROR_CODE)) {
	199	spin_unlock_irqrestore(&(tbl->it_lock), flags);
	200	return DMA_ERROR_CODE;
	201	}
	202
	203	entry += tbl->it_offset; /* Offset into real TCE table */
5d2efba6	204	ret = entry << IOMMU_PAGE_SHIFT; /* Set the return dma address */
1da177e4 LT	205
1da177e4 LT	206	/* Put the TCEs in the HW table */
5d2efba6	207	ppc_md.tce_build(tbl, entry, npages, (unsigned long)page & IOMMU_PAGE_MASK,
1da177e4 LT	208	direction);
	209
	210
	211	/* Flush/invalidate TLB caches if necessary */
	212	if (ppc_md.tce_flush)
	213	ppc_md.tce_flush(tbl);
	214
	215	spin_unlock_irqrestore(&(tbl->it_lock), flags);
	216
	217	/* Make sure updates are seen by hardware */
	218	mb();
	219
	220	return ret;
	221	}
	222
	223	static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
	224	unsigned int npages)
	225	{
	226	unsigned long entry, free_entry;
	227	unsigned long i;
	228
5d2efba6	229	entry = dma_addr >> IOMMU_PAGE_SHIFT;
1da177e4 LT	230	free_entry = entry - tbl->it_offset;
	231
	232	if (((free_entry + npages) > tbl->it_size) \|\|
	233	(entry < tbl->it_offset)) {
	234	if (printk_ratelimit()) {
	235	printk(KERN_INFO "iommu_free: invalid entry\n");
	236	printk(KERN_INFO "\tentry = 0x%lx\n", entry);
	237	printk(KERN_INFO "\tdma_addr = 0x%lx\n", (u64)dma_addr);
	238	printk(KERN_INFO "\tTable = 0x%lx\n", (u64)tbl);
	239	printk(KERN_INFO "\tbus# = 0x%lx\n", (u64)tbl->it_busno);
	240	printk(KERN_INFO "\tsize = 0x%lx\n", (u64)tbl->it_size);
	241	printk(KERN_INFO "\tstartOff = 0x%lx\n", (u64)tbl->it_offset);
	242	printk(KERN_INFO "\tindex = 0x%lx\n", (u64)tbl->it_index);
	243	WARN_ON(1);
	244	}
	245	return;
	246	}
	247
	248	ppc_md.tce_free(tbl, entry, npages);
	249
	250	for (i = 0; i < npages; i++)
	251	__clear_bit(free_entry+i, tbl->it_map);
	252	}
	253
	254	static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
	255	unsigned int npages)
	256	{
	257	unsigned long flags;
	258
	259	spin_lock_irqsave(&(tbl->it_lock), flags);
	260
	261	__iommu_free(tbl, dma_addr, npages);
	262
	263	/* Make sure TLB cache is flushed if the HW needs it. We do
	264	* not do an mb() here on purpose, it is not needed on any of
	265	* the current platforms.
	266	*/
	267	if (ppc_md.tce_flush)
	268	ppc_md.tce_flush(tbl);
	269
	270	spin_unlock_irqrestore(&(tbl->it_lock), flags);
	271	}
	272
12d04eef BH	273	int iommu_map_sg(struct iommu_table tbl, struct scatterlist sglist,
	274	int nelems, unsigned long mask,
	275	enum dma_data_direction direction)
1da177e4 LT	276	{
	277	dma_addr_t dma_next = 0, dma_addr;
	278	unsigned long flags;
	279	struct scatterlist s, outs, *segstart;
78bdc310	280	int outcount, incount, i;
d262c32a	281	unsigned int align;
1da177e4 LT	282	unsigned long handle;
	283
	284	BUG_ON(direction == DMA_NONE);
	285
	286	if ((nelems == 0) \|\| !tbl)
	287	return 0;
	288
	289	outs = s = segstart = &sglist[0];
	290	outcount = 1;
ac9af7cb	291	incount = nelems;
1da177e4 LT	292	handle = 0;
	293
	294	/* Init first segment length for backout at failure */
	295	outs->dma_length = 0;
	296
5d2efba6	297	DBG("sg mapping %d elements:\n", nelems);
1da177e4 LT	298
	299	spin_lock_irqsave(&(tbl->it_lock), flags);
	300
78bdc310	301	for_each_sg(sglist, s, nelems, i) {
1da177e4 LT	302	unsigned long vaddr, npages, entry, slen;
	303
	304	slen = s->length;
	305	/* Sanity check */
	306	if (slen == 0) {
	307	dma_next = 0;
	308	continue;
	309	}
	310	/* Allocate iommu entries for that segment */
58b053e4	311	vaddr = (unsigned long) sg_virt(s);
5d2efba6	312	npages = iommu_num_pages(vaddr, slen);
d262c32a BH	313	align = 0;
	314	if (IOMMU_PAGE_SHIFT < PAGE_SHIFT && slen >= PAGE_SIZE &&
	315	(vaddr & ~PAGE_MASK) == 0)
	316	align = PAGE_SHIFT - IOMMU_PAGE_SHIFT;
	317	entry = iommu_range_alloc(tbl, npages, &handle,
	318	mask >> IOMMU_PAGE_SHIFT, align);
1da177e4 LT	319
	320	DBG(" - vaddr: %lx, size: %lx\n", vaddr, slen);
	321
	322	/* Handle failure */
	323	if (unlikely(entry == DMA_ERROR_CODE)) {
	324	if (printk_ratelimit())
	325	printk(KERN_INFO "iommu_alloc failed, tbl %p vaddr %lx"
	326	" npages %lx\n", tbl, vaddr, npages);
	327	goto failure;
	328	}
	329
	330	/* Convert entry to a dma_addr_t */
	331	entry += tbl->it_offset;
5d2efba6 LV	332	dma_addr = entry << IOMMU_PAGE_SHIFT;
5d2efba6 LV	333	dma_addr \|= (s->offset & ~IOMMU_PAGE_MASK);
1da177e4	334
5d2efba6	335	DBG(" - %lu pages, entry: %lx, dma_addr: %lx\n",
1da177e4 LT	336	npages, entry, dma_addr);
	337
	338	/* Insert into HW table */
5d2efba6	339	ppc_md.tce_build(tbl, entry, npages, vaddr & IOMMU_PAGE_MASK, direction);
1da177e4 LT	340
	341	/* If we are in an open segment, try merging */
	342	if (segstart != s) {
	343	DBG(" - trying merge...\n");
	344	/* We cannot merge if:
	345	* - allocated dma_addr isn't contiguous to previous allocation
	346	*/
	347	if (novmerge \|\| (dma_addr != dma_next)) {
	348	/* Can't merge: create a new segment */
	349	segstart = s;
78bdc310 JA	350	outcount++;
78bdc310 JA	351	outs = sg_next(outs);
1da177e4 LT	352	DBG(" can't merge, new segment.\n");
	353	} else {
	354	outs->dma_length += s->length;
5d2efba6	355	DBG(" merged, new len: %ux\n", outs->dma_length);
1da177e4 LT	356	}
	357	}
	358
	359	if (segstart == s) {
	360	/* This is a new segment, fill entries */
	361	DBG(" - filling new segment.\n");
	362	outs->dma_address = dma_addr;
	363	outs->dma_length = slen;
	364	}
	365
	366	/* Calculate next page pointer for contiguous check */
	367	dma_next = dma_addr + slen;
	368
	369	DBG(" - dma next is: %lx\n", dma_next);
	370	}
	371
	372	/* Flush/invalidate TLB caches if necessary */
	373	if (ppc_md.tce_flush)
	374	ppc_md.tce_flush(tbl);
	375
	376	spin_unlock_irqrestore(&(tbl->it_lock), flags);
	377
1da177e4 LT	378	DBG("mapped %d elements:\n", outcount);
1da177e4 LT	379
ac9af7cb	380	/* For the sake of iommu_unmap_sg, we clear out the length in the
1da177e4 LT	381	* next entry of the sglist if we didn't fill the list completely
1da177e4 LT	382	*/
ac9af7cb	383	if (outcount < incount) {
78bdc310	384	outs = sg_next(outs);
1da177e4 LT	385	outs->dma_address = DMA_ERROR_CODE;
	386	outs->dma_length = 0;
	387	}
a958a264 JM	388
	389	/* Make sure updates are seen by hardware */
	390	mb();
	391
1da177e4 LT	392	return outcount;
	393
	394	failure:
78bdc310	395	for_each_sg(sglist, s, nelems, i) {
1da177e4 LT	396	if (s->dma_length != 0) {
	397	unsigned long vaddr, npages;
	398
5d2efba6 LV	399	vaddr = s->dma_address & IOMMU_PAGE_MASK;
5d2efba6 LV	400	npages = iommu_num_pages(s->dma_address, s->dma_length);
1da177e4	401	__iommu_free(tbl, vaddr, npages);
a958a264 JM	402	s->dma_address = DMA_ERROR_CODE;
a958a264 JM	403	s->dma_length = 0;
1da177e4	404	}
78bdc310 JA	405	if (s == outs)
78bdc310 JA	406	break;
1da177e4 LT	407	}
	408	spin_unlock_irqrestore(&(tbl->it_lock), flags);
	409	return 0;
	410	}
	411
	412
	413	void iommu_unmap_sg(struct iommu_table tbl, struct scatterlist sglist,
	414	int nelems, enum dma_data_direction direction)
	415	{
78bdc310	416	struct scatterlist *sg;
1da177e4 LT	417	unsigned long flags;
	418
	419	BUG_ON(direction == DMA_NONE);
	420
	421	if (!tbl)
	422	return;
	423
	424	spin_lock_irqsave(&(tbl->it_lock), flags);
	425
78bdc310	426	sg = sglist;
1da177e4 LT	427	while (nelems--) {
1da177e4 LT	428	unsigned int npages;
78bdc310	429	dma_addr_t dma_handle = sg->dma_address;
1da177e4	430
78bdc310	431	if (sg->dma_length == 0)
1da177e4	432	break;
78bdc310	433	npages = iommu_num_pages(dma_handle, sg->dma_length);
1da177e4	434	__iommu_free(tbl, dma_handle, npages);
78bdc310	435	sg = sg_next(sg);
1da177e4 LT	436	}
	437
	438	/* Flush/invalidate TLBs if necessary. As for iommu_free(), we
	439	* do not do an mb() here, the affected platforms do not need it
	440	* when freeing.
	441	*/
	442	if (ppc_md.tce_flush)
	443	ppc_md.tce_flush(tbl);
	444
	445	spin_unlock_irqrestore(&(tbl->it_lock), flags);
	446	}
	447
	448	/*
	449	* Build a iommu_table structure. This contains a bit map which
	450	* is used to manage allocation of the tce space.
	451	*/
ca1588e7	452	struct iommu_table iommu_init_table(struct iommu_table tbl, int nid)
1da177e4 LT	453	{
1da177e4 LT	454	unsigned long sz;
56997559 JM	455	unsigned long start_index, end_index;
	456	unsigned long entries_per_4g;
	457	unsigned long index;
1da177e4	458	static int welcomed = 0;
ca1588e7	459	struct page *page;
1da177e4 LT	460
	461	/* Set aside 1/4 of the table for large allocations. */
	462	tbl->it_halfpoint = tbl->it_size * 3 / 4;
	463
	464	/* number of bytes needed for the bitmap */
	465	sz = (tbl->it_size + 7) >> 3;
	466
ca1588e7 AB	467	page = alloc_pages_node(nid, GFP_ATOMIC, get_order(sz));
ca1588e7 AB	468	if (!page)
1da177e4	469	panic("iommu_init_table: Can't allocate %ld bytes\n", sz);
ca1588e7	470	tbl->it_map = page_address(page);
1da177e4 LT	471	memset(tbl->it_map, 0, sz);
	472
	473	tbl->it_hint = 0;
	474	tbl->it_largehint = tbl->it_halfpoint;
	475	spin_lock_init(&tbl->it_lock);
	476
5f50867b HM	477	#ifdef CONFIG_CRASH_DUMP
5f50867b HM	478	if (ppc_md.tce_get) {
56997559	479	unsigned long tceval;
5f50867b HM	480	unsigned long tcecount = 0;
	481
	482	/*
	483	* Reserve the existing mappings left by the first kernel.
	484	*/
	485	for (index = 0; index < tbl->it_size; index++) {
	486	tceval = ppc_md.tce_get(tbl, index + tbl->it_offset);
	487	/*
	488	* Freed TCE entry contains 0x7fffffffffffffff on JS20
	489	*/
	490	if (tceval && (tceval != 0x7fffffffffffffffUL)) {
	491	__set_bit(index, tbl->it_map);
	492	tcecount++;
	493	}
	494	}
	495	if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) {
	496	printk(KERN_WARNING "TCE table is full; ");
	497	printk(KERN_WARNING "freeing %d entries for the kdump boot\n",
	498	KDUMP_MIN_TCE_ENTRIES);
	499	for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES;
	500	index < tbl->it_size; index++)
	501	__clear_bit(index, tbl->it_map);
	502	}
	503	}
	504	#else
d3588ba9 JR	505	/* Clear the hardware table in case firmware left allocations in it */
d3588ba9 JR	506	ppc_md.tce_free(tbl, tbl->it_offset, tbl->it_size);
5f50867b	507	#endif
d3588ba9	508
56997559 JM	509	/*
	510	* DMA cannot cross 4 GB boundary. Mark last entry of each 4
	511	* GB chunk as reserved.
	512	*/
	513	if (protect4gb) {
	514	entries_per_4g = 0x100000000l >> IOMMU_PAGE_SHIFT;
	515
	516	/* Mark the last bit before a 4GB boundary as used */
	517	start_index = tbl->it_offset \| (entries_per_4g - 1);
	518	start_index -= tbl->it_offset;
	519
	520	end_index = tbl->it_size;
	521
	522	for (index = start_index; index < end_index - 1; index += entries_per_4g)
	523	__set_bit(index, tbl->it_map);
	524	}
	525
1da177e4 LT	526	if (!welcomed) {
	527	printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n",
	528	novmerge ? "disabled" : "enabled");
	529	welcomed = 1;
	530	}
	531
	532	return tbl;
	533	}
	534
68d315f5	535	void iommu_free_table(struct iommu_table tbl, const char node_name)
1da177e4	536	{
1da177e4 LT	537	unsigned long bitmap_sz, i;
	538	unsigned int order;
	539
	540	if (!tbl \|\| !tbl->it_map) {
	541	printk(KERN_ERR "%s: expected TCE map for %s\n", __FUNCTION__,
68d315f5	542	node_name);
1da177e4 LT	543	return;
	544	}
	545
	546	/* verify that table contains no entries */
	547	/* it_size is in entries, and we're examining 64 at a time */
	548	for (i = 0; i < (tbl->it_size/64); i++) {
	549	if (tbl->it_map[i] != 0) {
	550	printk(KERN_WARNING "%s: Unexpected TCEs for %s\n",
68d315f5	551	__FUNCTION__, node_name);
1da177e4 LT	552	break;
	553	}
	554	}
	555
	556	/* calculate bitmap size in bytes */
	557	bitmap_sz = (tbl->it_size + 7) / 8;
	558
	559	/* free bitmap */
	560	order = get_order(bitmap_sz);
	561	free_pages((unsigned long) tbl->it_map, order);
	562
	563	/* free table */
	564	kfree(tbl);
	565	}
	566
	567	/* Creates TCEs for a user provided buffer. The user buffer must be
	568	* contiguous real kernel storage (not vmalloc). The address of the buffer
	569	* passed here is the kernel (virtual) address of the buffer. The buffer
	570	* need not be page aligned, the dma_addr_t returned will point to the same
	571	* byte within the page as vaddr.
	572	*/
	573	dma_addr_t iommu_map_single(struct iommu_table tbl, void vaddr,
7daa411b OJ	574	size_t size, unsigned long mask,
7daa411b OJ	575	enum dma_data_direction direction)
1da177e4 LT	576	{
	577	dma_addr_t dma_handle = DMA_ERROR_CODE;
	578	unsigned long uaddr;
d262c32a	579	unsigned int npages, align;
1da177e4 LT	580
	581	BUG_ON(direction == DMA_NONE);
	582
	583	uaddr = (unsigned long)vaddr;
5d2efba6	584	npages = iommu_num_pages(uaddr, size);
1da177e4 LT	585
1da177e4 LT	586	if (tbl) {
d262c32a BH	587	align = 0;
	588	if (IOMMU_PAGE_SHIFT < PAGE_SHIFT && size >= PAGE_SIZE &&
	589	((unsigned long)vaddr & ~PAGE_MASK) == 0)
	590	align = PAGE_SHIFT - IOMMU_PAGE_SHIFT;
	591
7daa411b	592	dma_handle = iommu_alloc(tbl, vaddr, npages, direction,
d262c32a	593	mask >> IOMMU_PAGE_SHIFT, align);
1da177e4 LT	594	if (dma_handle == DMA_ERROR_CODE) {
	595	if (printk_ratelimit()) {
	596	printk(KERN_INFO "iommu_alloc failed, "
	597	"tbl %p vaddr %p npages %d\n",
	598	tbl, vaddr, npages);
	599	}
	600	} else
5d2efba6	601	dma_handle \|= (uaddr & ~IOMMU_PAGE_MASK);
1da177e4 LT	602	}
	603
	604	return dma_handle;
	605	}
	606
	607	void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
	608	size_t size, enum dma_data_direction direction)
	609	{
5d2efba6 LV	610	unsigned int npages;
5d2efba6 LV	611
1da177e4 LT	612	BUG_ON(direction == DMA_NONE);
1da177e4 LT	613
5d2efba6 LV	614	if (tbl) {
	615	npages = iommu_num_pages(dma_handle, size);
	616	iommu_free(tbl, dma_handle, npages);
	617	}
1da177e4 LT	618	}
	619
	620	/* Allocates a contiguous real buffer and creates mappings over it.
	621	* Returns the virtual address of the buffer and sets dma_handle
	622	* to the dma address (mapping) of the first page.
	623	*/
	624	void iommu_alloc_coherent(struct iommu_table tbl, size_t size,
8eb6c6e3	625	dma_addr_t *dma_handle, unsigned long mask, gfp_t flag, int node)
1da177e4 LT	626	{
	627	void *ret = NULL;
	628	dma_addr_t mapping;
5d2efba6 LV	629	unsigned int order;
5d2efba6 LV	630	unsigned int nio_pages, io_order;
8eb6c6e3	631	struct page *page;
1da177e4 LT	632
1da177e4 LT	633	size = PAGE_ALIGN(size);
1da177e4 LT	634	order = get_order(size);
	635
	636	/*
	637	* Client asked for way too much space. This is checked later
	638	* anyway. It is easier to debug here for the drivers than in
	639	* the tce tables.
	640	*/
	641	if (order >= IOMAP_MAX_ORDER) {
	642	printk("iommu_alloc_consistent size too large: 0x%lx\n", size);
	643	return NULL;
	644	}
	645
	646	if (!tbl)
	647	return NULL;
	648
	649	/* Alloc enough pages (and possibly more) */
05061354	650	page = alloc_pages_node(node, flag, order);
8eb6c6e3	651	if (!page)
1da177e4	652	return NULL;
8eb6c6e3	653	ret = page_address(page);
1da177e4 LT	654	memset(ret, 0, size);
	655
	656	/* Set up tces to cover the allocated range */
5d2efba6 LV	657	nio_pages = size >> IOMMU_PAGE_SHIFT;
	658	io_order = get_iommu_order(size);
	659	mapping = iommu_alloc(tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
	660	mask >> IOMMU_PAGE_SHIFT, io_order);
1da177e4 LT	661	if (mapping == DMA_ERROR_CODE) {
1da177e4 LT	662	free_pages((unsigned long)ret, order);
8eb6c6e3 CH	663	return NULL;
	664	}
	665	*dma_handle = mapping;
1da177e4 LT	666	return ret;
	667	}
	668
	669	void iommu_free_coherent(struct iommu_table *tbl, size_t size,
	670	void *vaddr, dma_addr_t dma_handle)
	671	{
1da177e4	672	if (tbl) {
5d2efba6 LV	673	unsigned int nio_pages;
	674
	675	size = PAGE_ALIGN(size);
	676	nio_pages = size >> IOMMU_PAGE_SHIFT;
	677	iommu_free(tbl, dma_handle, nio_pages);
1da177e4	678	size = PAGE_ALIGN(size);
1da177e4 LT	679	free_pages((unsigned long)vaddr, get_order(size));
	680	}
	681	}