[linux-2.6-block.git] / arch / powerpc / kernel / idle_power7.S

/*
 *  This file contains the power_save function for Power7 CPUs.
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */

#include <linux/threads.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/cputable.h>
#include <asm/thread_info.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/ppc-opcode.h>
#include <asm/hw_irq.h>
#include <asm/kvm_book3s_asm.h>

#undef DEBUG

	.text

_GLOBAL(power7_idle)
	/* Now check if user or arch enabled NAP mode */
	LOAD_REG_ADDRBASE(r3,powersave_nap)
	lwz	r4,ADDROFF(powersave_nap)(r3)
	cmpwi	0,r4,0
	beqlr
	/* fall through */

_GLOBAL(power7_nap)
	/* NAP is a state loss, we create a regs frame on the
	 * stack, fill it up with the state we care about and
	 * stick a pointer to it in PACAR1. We really only
	 * need to save PC, some CR bits and the NV GPRs,
	 * but for now an interrupt frame will do.
	 */
	mflr	r0
	std	r0,16(r1)
	stdu	r1,-INT_FRAME_SIZE(r1)
	std	r0,_LINK(r1)
	std	r0,_NIP(r1)

#ifndef CONFIG_SMP
	/* Make sure FPU, VSX etc... are flushed as we may lose
	 * state when going to nap mode
	 */
	bl	.discard_lazy_cpu_state
#endif /* CONFIG_SMP */

	/* Hard disable interrupts */
	mfmsr	r9
	rldicl	r9,r9,48,1
	rotldi	r9,r9,16
	mtmsrd	r9,1			/* hard-disable interrupts */

	/* Check if something happened while soft-disabled */
	lbz	r0,PACAIRQHAPPENED(r13)
	cmpwi	cr0,r0,0
	beq	1f
	addi	r1,r1,INT_FRAME_SIZE
	ld	r0,16(r1)
	mtlr	r0
	blr

1:	/* We mark irqs hard disabled as this is the state we'll
	 * be in when returning and we need to tell arch_local_irq_restore()
	 * about it
	 */
	li	r0,PACA_IRQ_HARD_DIS
	stb	r0,PACAIRQHAPPENED(r13)

	/* We haven't lost state ... yet */
	li	r0,0
	stb	r0,PACA_NAPSTATELOST(r13)

	/* Continue saving state */
	SAVE_GPR(2, r1)
	SAVE_NVGPRS(r1)
	mfcr	r3
	std	r3,_CCR(r1)
	std	r9,_MSR(r1)
	std	r1,PACAR1(r13)

_GLOBAL(power7_enter_nap_mode)
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	/* Tell KVM we're napping */
	li	r4,KVM_HWTHREAD_IN_NAP
	stb	r4,HSTATE_HWTHREAD_STATE(r13)
#endif

	/* Magic NAP mode enter sequence */
	std	r0,0(r1)
	ptesync
	ld	r0,0(r1)
1:	cmp	cr0,r0,r0
	bne	1b
	PPC_NAP
	b	.

_GLOBAL(power7_wakeup_loss)
	ld	r1,PACAR1(r13)
	REST_NVGPRS(r1)
	REST_GPR(2, r1)
	ld	r3,_CCR(r1)
	ld	r4,_MSR(r1)
	ld	r5,_NIP(r1)
	addi	r1,r1,INT_FRAME_SIZE
	mtcr	r3
	mtspr	SPRN_SRR1,r4
	mtspr	SPRN_SRR0,r5
	rfid

_GLOBAL(power7_wakeup_noloss)
	lbz	r0,PACA_NAPSTATELOST(r13)
	cmpwi	r0,0
	bne	.power7_wakeup_loss
	ld	r1,PACAR1(r13)
	ld	r4,_MSR(r1)
	ld	r5,_NIP(r1)
	addi	r1,r1,INT_FRAME_SIZE
	mtspr	SPRN_SRR1,r4
	mtspr	SPRN_SRR0,r5
	rfid
Commit	Line	Data
948cf67c	1	/*
7230c564	2	* This file contains the power_save function for Power7 CPUs.
948cf67c BH	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*/
	9
	10	#include <linux/threads.h>
	11	#include <asm/processor.h>
	12	#include <asm/page.h>
	13	#include <asm/cputable.h>
	14	#include <asm/thread_info.h>
	15	#include <asm/ppc_asm.h>
	16	#include <asm/asm-offsets.h>
	17	#include <asm/ppc-opcode.h>
7230c564	18	#include <asm/hw_irq.h>
f0888f70	19	#include <asm/kvm_book3s_asm.h>
948cf67c BH	20
	21	#undef DEBUG
	22
	23	.text
	24
	25	_GLOBAL(power7_idle)
	26	/* Now check if user or arch enabled NAP mode */
	27	LOAD_REG_ADDRBASE(r3,powersave_nap)
	28	lwz r4,ADDROFF(powersave_nap)(r3)
	29	cmpwi 0,r4,0
	30	beqlr
375f561a	31	/* fall through */
948cf67c	32
375f561a	33	_GLOBAL(power7_nap)
948cf67c BH	34	/* NAP is a state loss, we create a regs frame on the
	35	* stack, fill it up with the state we care about and
	36	* stick a pointer to it in PACAR1. We really only
	37	* need to save PC, some CR bits and the NV GPRs,
	38	* but for now an interrupt frame will do.
	39	*/
	40	mflr r0
	41	std r0,16(r1)
	42	stdu r1,-INT_FRAME_SIZE(r1)
	43	std r0,_LINK(r1)
	44	std r0,_NIP(r1)
	45
	46	#ifndef CONFIG_SMP
	47	/* Make sure FPU, VSX etc... are flushed as we may lose
	48	* state when going to nap mode
	49	*/
	50	bl .discard_lazy_cpu_state
	51	#endif /* CONFIG_SMP */
	52
	53	/* Hard disable interrupts */
	54	mfmsr r9
	55	rldicl r9,r9,48,1
	56	rotldi r9,r9,16
	57	mtmsrd r9,1 /* hard-disable interrupts */
7230c564 BH	58
	59	/* Check if something happened while soft-disabled */
	60	lbz r0,PACAIRQHAPPENED(r13)
	61	cmpwi cr0,r0,0
	62	beq 1f
	63	addi r1,r1,INT_FRAME_SIZE
	64	ld r0,16(r1)
	65	mtlr r0
	66	blr
	67
	68	1: /* We mark irqs hard disabled as this is the state we'll
	69	* be in when returning and we need to tell arch_local_irq_restore()
	70	* about it
	71	*/
	72	li r0,PACA_IRQ_HARD_DIS
	73	stb r0,PACAIRQHAPPENED(r13)
	74
	75	/* We haven't lost state ... yet */
948cf67c	76	li r0,0
2fde6d20	77	stb r0,PACA_NAPSTATELOST(r13)
948cf67c BH	78
	79	/* Continue saving state */
	80	SAVE_GPR(2, r1)
	81	SAVE_NVGPRS(r1)
	82	mfcr r3
	83	std r3,_CCR(r1)
	84	std r9,_MSR(r1)
	85	std r1,PACAR1(r13)
	86
1c51089f	87	_GLOBAL(power7_enter_nap_mode)
9975f5e3	88	#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
f0888f70 PM	89	/* Tell KVM we're napping */
	90	li r4,KVM_HWTHREAD_IN_NAP
	91	stb r4,HSTATE_HWTHREAD_STATE(r13)
	92	#endif
	93
948cf67c BH	94	/* Magic NAP mode enter sequence */
	95	std r0,0(r1)
	96	ptesync
	97	ld r0,0(r1)
	98	1: cmp cr0,r0,r0
	99	bne 1b
	100	PPC_NAP
	101	b .
	102
	103	_GLOBAL(power7_wakeup_loss)
948cf67c BH	104	ld r1,PACAR1(r13)
	105	REST_NVGPRS(r1)
	106	REST_GPR(2, r1)
	107	ld r3,_CCR(r1)
	108	ld r4,_MSR(r1)
	109	ld r5,_NIP(r1)
	110	addi r1,r1,INT_FRAME_SIZE
	111	mtcr r3
	112	mtspr SPRN_SRR1,r4
	113	mtspr SPRN_SRR0,r5
	114	rfid
	115
	116	_GLOBAL(power7_wakeup_noloss)
2fde6d20 PM	117	lbz r0,PACA_NAPSTATELOST(r13)
	118	cmpwi r0,0
	119	bne .power7_wakeup_loss
948cf67c BH	120	ld r1,PACAR1(r13)
	121	ld r4,_MSR(r1)
	122	ld r5,_NIP(r1)
	123	addi r1,r1,INT_FRAME_SIZE
	124	mtspr SPRN_SRR1,r4
	125	mtspr SPRN_SRR0,r5
	126	rfid