Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * Kernel execution entry point code. |
3 | * | |
4 | * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> | |
5 | * Initial PowerPC version. | |
6 | * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> | |
7 | * Rewritten for PReP | |
8 | * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> | |
9 | * Low-level exception handers, MMU support, and rewrite. | |
10 | * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> | |
11 | * PowerPC 8xx modifications. | |
12 | * Copyright (c) 1998-1999 TiVo, Inc. | |
13 | * PowerPC 403GCX modifications. | |
14 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> | |
15 | * PowerPC 403GCX/405GP modifications. | |
16 | * Copyright 2000 MontaVista Software Inc. | |
17 | * PPC405 modifications | |
18 | * PowerPC 403GCX/405GP modifications. | |
19 | * Author: MontaVista Software, Inc. | |
20 | * frank_rowand@mvista.com or source@mvista.com | |
21 | * debbie_chu@mvista.com | |
22 | * Copyright 2002-2005 MontaVista Software, Inc. | |
23 | * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> | |
24 | * | |
25 | * This program is free software; you can redistribute it and/or modify it | |
26 | * under the terms of the GNU General Public License as published by the | |
27 | * Free Software Foundation; either version 2 of the License, or (at your | |
28 | * option) any later version. | |
29 | */ | |
30 | ||
e7039845 | 31 | #include <linux/init.h> |
14cf11af PM |
32 | #include <asm/processor.h> |
33 | #include <asm/page.h> | |
34 | #include <asm/mmu.h> | |
35 | #include <asm/pgtable.h> | |
14cf11af PM |
36 | #include <asm/cputable.h> |
37 | #include <asm/thread_info.h> | |
38 | #include <asm/ppc_asm.h> | |
39 | #include <asm/asm-offsets.h> | |
46f52210 | 40 | #include <asm/ptrace.h> |
e7f75ad0 | 41 | #include <asm/synch.h> |
9445aa1a | 42 | #include <asm/export.h> |
6c16816b | 43 | #include <asm/code-patching-asm.h> |
14cf11af PM |
44 | #include "head_booke.h" |
45 | ||
46 | ||
47 | /* As with the other PowerPC ports, it is expected that when code | |
48 | * execution begins here, the following registers contain valid, yet | |
49 | * optional, information: | |
50 | * | |
51 | * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) | |
52 | * r4 - Starting address of the init RAM disk | |
53 | * r5 - Ending address of the init RAM disk | |
54 | * r6 - Start of kernel command line string (e.g. "mem=128") | |
55 | * r7 - End of kernel command line string | |
56 | * | |
57 | */ | |
e7039845 | 58 | __HEAD |
748a7683 KG |
59 | _ENTRY(_stext); |
60 | _ENTRY(_start); | |
14cf11af PM |
61 | /* |
62 | * Reserve a word at a fixed location to store the address | |
63 | * of abatron_pteptrs | |
64 | */ | |
65 | nop | |
6dece0eb | 66 | mr r31,r3 /* save device tree ptr */ |
14cf11af PM |
67 | li r24,0 /* CPU number */ |
68 | ||
26ecb6c4 SP |
69 | #ifdef CONFIG_RELOCATABLE |
70 | /* | |
71 | * Relocate ourselves to the current runtime address. | |
72 | * This is called only by the Boot CPU. | |
73 | * "relocate" is called with our current runtime virutal | |
74 | * address. | |
75 | * r21 will be loaded with the physical runtime address of _stext | |
76 | */ | |
77 | bl 0f /* Get our runtime address */ | |
78 | 0: mflr r21 /* Make it accessible */ | |
79 | addis r21,r21,(_stext - 0b)@ha | |
80 | addi r21,r21,(_stext - 0b)@l /* Get our current runtime base */ | |
81 | ||
82 | /* | |
83 | * We have the runtime (virutal) address of our base. | |
84 | * We calculate our shift of offset from a 256M page. | |
85 | * We could map the 256M page we belong to at PAGE_OFFSET and | |
86 | * get going from there. | |
87 | */ | |
88 | lis r4,KERNELBASE@h | |
89 | ori r4,r4,KERNELBASE@l | |
90 | rlwinm r6,r21,0,4,31 /* r6 = PHYS_START % 256M */ | |
91 | rlwinm r5,r4,0,4,31 /* r5 = KERNELBASE % 256M */ | |
92 | subf r3,r5,r6 /* r3 = r6 - r5 */ | |
93 | add r3,r4,r3 /* Required Virutal Address */ | |
94 | ||
95 | bl relocate | |
96 | #endif | |
97 | ||
795033c3 | 98 | bl init_cpu_state |
14cf11af | 99 | |
14cf11af PM |
100 | /* |
101 | * This is where the main kernel code starts. | |
102 | */ | |
103 | ||
104 | /* ptr to current */ | |
105 | lis r2,init_task@h | |
106 | ori r2,r2,init_task@l | |
107 | ||
108 | /* ptr to current thread */ | |
109 | addi r4,r2,THREAD /* init task's THREAD */ | |
ee43eb78 | 110 | mtspr SPRN_SPRG_THREAD,r4 |
14cf11af PM |
111 | |
112 | /* stack */ | |
113 | lis r1,init_thread_union@h | |
114 | ori r1,r1,init_thread_union@l | |
115 | li r0,0 | |
116 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
117 | ||
118 | bl early_init | |
119 | ||
26ecb6c4 SP |
120 | #ifdef CONFIG_RELOCATABLE |
121 | /* | |
122 | * Relocatable kernel support based on processing of dynamic | |
123 | * relocation entries. | |
124 | * | |
125 | * r25 will contain RPN/ERPN for the start address of memory | |
126 | * r21 will contain the current offset of _stext | |
127 | */ | |
128 | lis r3,kernstart_addr@ha | |
129 | la r3,kernstart_addr@l(r3) | |
130 | ||
131 | /* | |
132 | * Compute the kernstart_addr. | |
133 | * kernstart_addr => (r6,r8) | |
134 | * kernstart_addr & ~0xfffffff => (r6,r7) | |
135 | */ | |
136 | rlwinm r6,r25,0,28,31 /* ERPN. Bits 32-35 of Address */ | |
137 | rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */ | |
138 | rlwinm r8,r21,0,4,31 /* r8 = (_stext & 0xfffffff) */ | |
139 | or r8,r7,r8 /* Compute the lower 32bit of kernstart_addr */ | |
140 | ||
141 | /* Store kernstart_addr */ | |
142 | stw r6,0(r3) /* higher 32bit */ | |
143 | stw r8,4(r3) /* lower 32bit */ | |
144 | ||
145 | /* | |
146 | * Compute the virt_phys_offset : | |
147 | * virt_phys_offset = stext.run - kernstart_addr | |
148 | * | |
149 | * stext.run = (KERNELBASE & ~0xfffffff) + (kernstart_addr & 0xfffffff) | |
150 | * When we relocate, we have : | |
151 | * | |
152 | * (kernstart_addr & 0xfffffff) = (stext.run & 0xfffffff) | |
153 | * | |
154 | * hence: | |
155 | * virt_phys_offset = (KERNELBASE & ~0xfffffff) - (kernstart_addr & ~0xfffffff) | |
156 | * | |
157 | */ | |
158 | ||
159 | /* KERNELBASE&~0xfffffff => (r4,r5) */ | |
160 | li r4, 0 /* higer 32bit */ | |
161 | lis r5,KERNELBASE@h | |
162 | rlwinm r5,r5,0,0,3 /* Align to 256M, lower 32bit */ | |
163 | ||
164 | /* | |
165 | * 64bit subtraction. | |
166 | */ | |
167 | subfc r5,r7,r5 | |
168 | subfe r4,r6,r4 | |
169 | ||
170 | /* Store virt_phys_offset */ | |
171 | lis r3,virt_phys_offset@ha | |
172 | la r3,virt_phys_offset@l(r3) | |
173 | ||
174 | stw r4,0(r3) | |
175 | stw r5,4(r3) | |
176 | ||
177 | #elif defined(CONFIG_DYNAMIC_MEMSTART) | |
9661534d | 178 | /* |
0f890c8d SP |
179 | * Mapping based, page aligned dynamic kernel loading. |
180 | * | |
9661534d DK |
181 | * r25 will contain RPN/ERPN for the start address of memory |
182 | * | |
183 | * Add the difference between KERNELBASE and PAGE_OFFSET to the | |
184 | * start of physical memory to get kernstart_addr. | |
185 | */ | |
186 | lis r3,kernstart_addr@ha | |
187 | la r3,kernstart_addr@l(r3) | |
188 | ||
189 | lis r4,KERNELBASE@h | |
190 | ori r4,r4,KERNELBASE@l | |
191 | lis r5,PAGE_OFFSET@h | |
192 | ori r5,r5,PAGE_OFFSET@l | |
193 | subf r4,r5,r4 | |
194 | ||
195 | rlwinm r6,r25,0,28,31 /* ERPN */ | |
196 | rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */ | |
197 | add r7,r7,r4 | |
198 | ||
199 | stw r6,0(r3) | |
200 | stw r7,4(r3) | |
201 | #endif | |
202 | ||
14cf11af PM |
203 | /* |
204 | * Decide what sort of machine this is and initialize the MMU. | |
205 | */ | |
2edb16ef CL |
206 | #ifdef CONFIG_KASAN |
207 | bl kasan_early_init | |
208 | #endif | |
6dece0eb SW |
209 | li r3,0 |
210 | mr r4,r31 | |
14cf11af PM |
211 | bl machine_init |
212 | bl MMU_init | |
213 | ||
214 | /* Setup PTE pointers for the Abatron bdiGDB */ | |
215 | lis r6, swapper_pg_dir@h | |
216 | ori r6, r6, swapper_pg_dir@l | |
217 | lis r5, abatron_pteptrs@h | |
218 | ori r5, r5, abatron_pteptrs@l | |
219 | lis r4, KERNELBASE@h | |
220 | ori r4, r4, KERNELBASE@l | |
221 | stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ | |
222 | stw r6, 0(r5) | |
223 | ||
029b8f66 DK |
224 | /* Clear the Machine Check Syndrome Register */ |
225 | li r0,0 | |
226 | mtspr SPRN_MCSR,r0 | |
227 | ||
14cf11af PM |
228 | /* Let's move on */ |
229 | lis r4,start_kernel@h | |
230 | ori r4,r4,start_kernel@l | |
231 | lis r3,MSR_KERNEL@h | |
232 | ori r3,r3,MSR_KERNEL@l | |
233 | mtspr SPRN_SRR0,r4 | |
234 | mtspr SPRN_SRR1,r3 | |
235 | rfi /* change context and jump to start_kernel */ | |
236 | ||
237 | /* | |
238 | * Interrupt vector entry code | |
239 | * | |
240 | * The Book E MMUs are always on so we don't need to handle | |
241 | * interrupts in real mode as with previous PPC processors. In | |
242 | * this case we handle interrupts in the kernel virtual address | |
243 | * space. | |
244 | * | |
245 | * Interrupt vectors are dynamically placed relative to the | |
246 | * interrupt prefix as determined by the address of interrupt_base. | |
247 | * The interrupt vectors offsets are programmed using the labels | |
248 | * for each interrupt vector entry. | |
249 | * | |
250 | * Interrupt vectors must be aligned on a 16 byte boundary. | |
251 | * We align on a 32 byte cache line boundary for good measure. | |
252 | */ | |
253 | ||
254 | interrupt_base: | |
255 | /* Critical Input Interrupt */ | |
cfac5784 | 256 | CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception) |
14cf11af PM |
257 | |
258 | /* Machine Check Interrupt */ | |
cfac5784 SW |
259 | CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \ |
260 | machine_check_exception) | |
47c0bd1a | 261 | MCHECK_EXCEPTION(0x0210, MachineCheckA, machine_check_exception) |
14cf11af PM |
262 | |
263 | /* Data Storage Interrupt */ | |
1bc54c03 | 264 | DATA_STORAGE_EXCEPTION |
14cf11af | 265 | |
1bc54c03 | 266 | /* Instruction Storage Interrupt */ |
14cf11af PM |
267 | INSTRUCTION_STORAGE_EXCEPTION |
268 | ||
269 | /* External Input Interrupt */ | |
cfac5784 SW |
270 | EXCEPTION(0x0500, BOOKE_INTERRUPT_EXTERNAL, ExternalInput, \ |
271 | do_IRQ, EXC_XFER_LITE) | |
14cf11af PM |
272 | |
273 | /* Alignment Interrupt */ | |
274 | ALIGNMENT_EXCEPTION | |
275 | ||
276 | /* Program Interrupt */ | |
277 | PROGRAM_EXCEPTION | |
278 | ||
279 | /* Floating Point Unavailable Interrupt */ | |
280 | #ifdef CONFIG_PPC_FPU | |
281 | FP_UNAVAILABLE_EXCEPTION | |
282 | #else | |
cfac5784 SW |
283 | EXCEPTION(0x2010, BOOKE_INTERRUPT_FP_UNAVAIL, \ |
284 | FloatingPointUnavailable, unknown_exception, EXC_XFER_EE) | |
14cf11af | 285 | #endif |
14cf11af PM |
286 | /* System Call Interrupt */ |
287 | START_EXCEPTION(SystemCall) | |
cfac5784 | 288 | NORMAL_EXCEPTION_PROLOG(BOOKE_INTERRUPT_SYSCALL) |
14cf11af PM |
289 | EXC_XFER_EE_LITE(0x0c00, DoSyscall) |
290 | ||
25985edc | 291 | /* Auxiliary Processor Unavailable Interrupt */ |
cfac5784 SW |
292 | EXCEPTION(0x2020, BOOKE_INTERRUPT_AP_UNAVAIL, \ |
293 | AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
294 | |
295 | /* Decrementer Interrupt */ | |
296 | DECREMENTER_EXCEPTION | |
297 | ||
298 | /* Fixed Internal Timer Interrupt */ | |
299 | /* TODO: Add FIT support */ | |
cfac5784 SW |
300 | EXCEPTION(0x1010, BOOKE_INTERRUPT_FIT, FixedIntervalTimer, \ |
301 | unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
302 | |
303 | /* Watchdog Timer Interrupt */ | |
304 | /* TODO: Add watchdog support */ | |
305 | #ifdef CONFIG_BOOKE_WDT | |
cfac5784 | 306 | CRITICAL_EXCEPTION(0x1020, WATCHDOG, WatchdogTimer, WatchdogException) |
14cf11af | 307 | #else |
cfac5784 | 308 | CRITICAL_EXCEPTION(0x1020, WATCHDOG, WatchdogTimer, unknown_exception) |
14cf11af PM |
309 | #endif |
310 | ||
311 | /* Data TLB Error Interrupt */ | |
e7f75ad0 | 312 | START_EXCEPTION(DataTLBError44x) |
ee43eb78 BH |
313 | mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ |
314 | mtspr SPRN_SPRG_WSCRATCH1, r11 | |
315 | mtspr SPRN_SPRG_WSCRATCH2, r12 | |
316 | mtspr SPRN_SPRG_WSCRATCH3, r13 | |
14cf11af | 317 | mfcr r11 |
ee43eb78 | 318 | mtspr SPRN_SPRG_WSCRATCH4, r11 |
14cf11af PM |
319 | mfspr r10, SPRN_DEAR /* Get faulting address */ |
320 | ||
321 | /* If we are faulting a kernel address, we have to use the | |
322 | * kernel page tables. | |
323 | */ | |
8a13c4f9 | 324 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
325 | cmplw r10, r11 |
326 | blt+ 3f | |
327 | lis r11, swapper_pg_dir@h | |
328 | ori r11, r11, swapper_pg_dir@l | |
329 | ||
330 | mfspr r12,SPRN_MMUCR | |
331 | rlwinm r12,r12,0,0,23 /* Clear TID */ | |
332 | ||
333 | b 4f | |
334 | ||
335 | /* Get the PGD for the current thread */ | |
336 | 3: | |
ee43eb78 | 337 | mfspr r11,SPRN_SPRG_THREAD |
14cf11af PM |
338 | lwz r11,PGDIR(r11) |
339 | ||
340 | /* Load PID into MMUCR TID */ | |
341 | mfspr r12,SPRN_MMUCR | |
342 | mfspr r13,SPRN_PID /* Get PID */ | |
343 | rlwimi r12,r13,0,24,31 /* Set TID */ | |
344 | ||
345 | 4: | |
346 | mtspr SPRN_MMUCR,r12 | |
347 | ||
1bc54c03 BH |
348 | /* Mask of required permission bits. Note that while we |
349 | * do copy ESR:ST to _PAGE_RW position as trying to write | |
350 | * to an RO page is pretty common, we don't do it with | |
351 | * _PAGE_DIRTY. We could do it, but it's a fairly rare | |
352 | * event so I'd rather take the overhead when it happens | |
353 | * rather than adding an instruction here. We should measure | |
354 | * whether the whole thing is worth it in the first place | |
355 | * as we could avoid loading SPRN_ESR completely in the first | |
356 | * place... | |
357 | * | |
358 | * TODO: Is it worth doing that mfspr & rlwimi in the first | |
359 | * place or can we save a couple of instructions here ? | |
360 | */ | |
361 | mfspr r12,SPRN_ESR | |
362 | li r13,_PAGE_PRESENT|_PAGE_ACCESSED | |
363 | rlwimi r13,r12,10,30,30 | |
364 | ||
365 | /* Load the PTE */ | |
ca9153a3 IY |
366 | /* Compute pgdir/pmd offset */ |
367 | rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29 | |
14cf11af PM |
368 | lwzx r11, r12, r11 /* Get pgd/pmd entry */ |
369 | rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ | |
370 | beq 2f /* Bail if no table */ | |
371 | ||
ca9153a3 IY |
372 | /* Compute pte address */ |
373 | rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28 | |
1bc54c03 BH |
374 | lwz r11, 0(r12) /* Get high word of pte entry */ |
375 | lwz r12, 4(r12) /* Get low word of pte entry */ | |
14cf11af | 376 | |
1bc54c03 BH |
377 | lis r10,tlb_44x_index@ha |
378 | ||
379 | andc. r13,r13,r12 /* Check permission */ | |
380 | ||
381 | /* Load the next available TLB index */ | |
382 | lwz r13,tlb_44x_index@l(r10) | |
383 | ||
384 | bne 2f /* Bail if permission mismach */ | |
385 | ||
386 | /* Increment, rollover, and store TLB index */ | |
387 | addi r13,r13,1 | |
388 | ||
6c16816b | 389 | patch_site 0f, patch__tlb_44x_hwater_D |
1bc54c03 | 390 | /* Compare with watermark (instruction gets patched) */ |
6c16816b | 391 | 0: cmpwi 0,r13,1 /* reserve entries */ |
1bc54c03 BH |
392 | ble 5f |
393 | li r13,0 | |
394 | 5: | |
395 | /* Store the next available TLB index */ | |
396 | stw r13,tlb_44x_index@l(r10) | |
397 | ||
398 | /* Re-load the faulting address */ | |
399 | mfspr r10,SPRN_DEAR | |
14cf11af PM |
400 | |
401 | /* Jump to common tlb load */ | |
e7f75ad0 | 402 | b finish_tlb_load_44x |
14cf11af PM |
403 | |
404 | 2: | |
405 | /* The bailout. Restore registers to pre-exception conditions | |
406 | * and call the heavyweights to help us out. | |
407 | */ | |
ee43eb78 | 408 | mfspr r11, SPRN_SPRG_RSCRATCH4 |
14cf11af | 409 | mtcr r11 |
ee43eb78 BH |
410 | mfspr r13, SPRN_SPRG_RSCRATCH3 |
411 | mfspr r12, SPRN_SPRG_RSCRATCH2 | |
412 | mfspr r11, SPRN_SPRG_RSCRATCH1 | |
413 | mfspr r10, SPRN_SPRG_RSCRATCH0 | |
1bc54c03 | 414 | b DataStorage |
14cf11af PM |
415 | |
416 | /* Instruction TLB Error Interrupt */ | |
417 | /* | |
418 | * Nearly the same as above, except we get our | |
419 | * information from different registers and bailout | |
420 | * to a different point. | |
421 | */ | |
e7f75ad0 | 422 | START_EXCEPTION(InstructionTLBError44x) |
ee43eb78 BH |
423 | mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ |
424 | mtspr SPRN_SPRG_WSCRATCH1, r11 | |
425 | mtspr SPRN_SPRG_WSCRATCH2, r12 | |
426 | mtspr SPRN_SPRG_WSCRATCH3, r13 | |
14cf11af | 427 | mfcr r11 |
ee43eb78 | 428 | mtspr SPRN_SPRG_WSCRATCH4, r11 |
14cf11af PM |
429 | mfspr r10, SPRN_SRR0 /* Get faulting address */ |
430 | ||
431 | /* If we are faulting a kernel address, we have to use the | |
432 | * kernel page tables. | |
433 | */ | |
8a13c4f9 | 434 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
435 | cmplw r10, r11 |
436 | blt+ 3f | |
437 | lis r11, swapper_pg_dir@h | |
438 | ori r11, r11, swapper_pg_dir@l | |
439 | ||
440 | mfspr r12,SPRN_MMUCR | |
441 | rlwinm r12,r12,0,0,23 /* Clear TID */ | |
442 | ||
443 | b 4f | |
444 | ||
445 | /* Get the PGD for the current thread */ | |
446 | 3: | |
ee43eb78 | 447 | mfspr r11,SPRN_SPRG_THREAD |
14cf11af PM |
448 | lwz r11,PGDIR(r11) |
449 | ||
450 | /* Load PID into MMUCR TID */ | |
451 | mfspr r12,SPRN_MMUCR | |
452 | mfspr r13,SPRN_PID /* Get PID */ | |
453 | rlwimi r12,r13,0,24,31 /* Set TID */ | |
454 | ||
455 | 4: | |
456 | mtspr SPRN_MMUCR,r12 | |
457 | ||
1bc54c03 | 458 | /* Make up the required permissions */ |
ea3cc330 | 459 | li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC |
1bc54c03 | 460 | |
ca9153a3 IY |
461 | /* Compute pgdir/pmd offset */ |
462 | rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29 | |
14cf11af PM |
463 | lwzx r11, r12, r11 /* Get pgd/pmd entry */ |
464 | rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ | |
465 | beq 2f /* Bail if no table */ | |
466 | ||
ca9153a3 IY |
467 | /* Compute pte address */ |
468 | rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28 | |
1bc54c03 BH |
469 | lwz r11, 0(r12) /* Get high word of pte entry */ |
470 | lwz r12, 4(r12) /* Get low word of pte entry */ | |
14cf11af | 471 | |
1bc54c03 BH |
472 | lis r10,tlb_44x_index@ha |
473 | ||
474 | andc. r13,r13,r12 /* Check permission */ | |
475 | ||
476 | /* Load the next available TLB index */ | |
477 | lwz r13,tlb_44x_index@l(r10) | |
478 | ||
479 | bne 2f /* Bail if permission mismach */ | |
480 | ||
481 | /* Increment, rollover, and store TLB index */ | |
482 | addi r13,r13,1 | |
483 | ||
6c16816b | 484 | patch_site 0f, patch__tlb_44x_hwater_I |
1bc54c03 | 485 | /* Compare with watermark (instruction gets patched) */ |
6c16816b | 486 | 0: cmpwi 0,r13,1 /* reserve entries */ |
1bc54c03 BH |
487 | ble 5f |
488 | li r13,0 | |
489 | 5: | |
490 | /* Store the next available TLB index */ | |
491 | stw r13,tlb_44x_index@l(r10) | |
492 | ||
493 | /* Re-load the faulting address */ | |
494 | mfspr r10,SPRN_SRR0 | |
14cf11af PM |
495 | |
496 | /* Jump to common TLB load point */ | |
e7f75ad0 | 497 | b finish_tlb_load_44x |
14cf11af PM |
498 | |
499 | 2: | |
500 | /* The bailout. Restore registers to pre-exception conditions | |
501 | * and call the heavyweights to help us out. | |
502 | */ | |
ee43eb78 | 503 | mfspr r11, SPRN_SPRG_RSCRATCH4 |
14cf11af | 504 | mtcr r11 |
ee43eb78 BH |
505 | mfspr r13, SPRN_SPRG_RSCRATCH3 |
506 | mfspr r12, SPRN_SPRG_RSCRATCH2 | |
507 | mfspr r11, SPRN_SPRG_RSCRATCH1 | |
508 | mfspr r10, SPRN_SPRG_RSCRATCH0 | |
14cf11af PM |
509 | b InstructionStorage |
510 | ||
14cf11af | 511 | /* |
14cf11af PM |
512 | * Both the instruction and data TLB miss get to this |
513 | * point to load the TLB. | |
514 | * r10 - EA of fault | |
1bc54c03 BH |
515 | * r11 - PTE high word value |
516 | * r12 - PTE low word value | |
517 | * r13 - TLB index | |
14cf11af PM |
518 | * MMUCR - loaded with proper value when we get here |
519 | * Upon exit, we reload everything and RFI. | |
520 | */ | |
e7f75ad0 | 521 | finish_tlb_load_44x: |
1bc54c03 | 522 | /* Combine RPN & ERPN an write WS 0 */ |
ca9153a3 | 523 | rlwimi r11,r12,0,0,31-PAGE_SHIFT |
1bc54c03 | 524 | tlbwe r11,r13,PPC44x_TLB_XLAT |
14cf11af PM |
525 | |
526 | /* | |
1bc54c03 | 527 | * Create WS1. This is the faulting address (EPN), |
14cf11af PM |
528 | * page size, and valid flag. |
529 | */ | |
ca9153a3 IY |
530 | li r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE |
531 | /* Insert valid and page size */ | |
532 | rlwimi r10,r11,0,PPC44x_PTE_ADD_MASK_BIT,31 | |
1bc54c03 BH |
533 | tlbwe r10,r13,PPC44x_TLB_PAGEID /* Write PAGEID */ |
534 | ||
535 | /* And WS 2 */ | |
536 | li r10,0xf85 /* Mask to apply from PTE */ | |
537 | rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */ | |
538 | and r11,r12,r10 /* Mask PTE bits to keep */ | |
539 | andi. r10,r12,_PAGE_USER /* User page ? */ | |
540 | beq 1f /* nope, leave U bits empty */ | |
541 | rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */ | |
542 | 1: tlbwe r11,r13,PPC44x_TLB_ATTRIB /* Write ATTRIB */ | |
14cf11af PM |
543 | |
544 | /* Done...restore registers and get out of here. | |
545 | */ | |
ee43eb78 | 546 | mfspr r11, SPRN_SPRG_RSCRATCH4 |
14cf11af | 547 | mtcr r11 |
ee43eb78 BH |
548 | mfspr r13, SPRN_SPRG_RSCRATCH3 |
549 | mfspr r12, SPRN_SPRG_RSCRATCH2 | |
550 | mfspr r11, SPRN_SPRG_RSCRATCH1 | |
551 | mfspr r10, SPRN_SPRG_RSCRATCH0 | |
14cf11af PM |
552 | rfi /* Force context change */ |
553 | ||
e7f75ad0 DK |
554 | /* TLB error interrupts for 476 |
555 | */ | |
556 | #ifdef CONFIG_PPC_47x | |
557 | START_EXCEPTION(DataTLBError47x) | |
558 | mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */ | |
559 | mtspr SPRN_SPRG_WSCRATCH1,r11 | |
560 | mtspr SPRN_SPRG_WSCRATCH2,r12 | |
561 | mtspr SPRN_SPRG_WSCRATCH3,r13 | |
562 | mfcr r11 | |
563 | mtspr SPRN_SPRG_WSCRATCH4,r11 | |
564 | mfspr r10,SPRN_DEAR /* Get faulting address */ | |
565 | ||
566 | /* If we are faulting a kernel address, we have to use the | |
567 | * kernel page tables. | |
568 | */ | |
569 | lis r11,PAGE_OFFSET@h | |
570 | cmplw cr0,r10,r11 | |
571 | blt+ 3f | |
572 | lis r11,swapper_pg_dir@h | |
573 | ori r11,r11, swapper_pg_dir@l | |
574 | li r12,0 /* MMUCR = 0 */ | |
575 | b 4f | |
576 | ||
577 | /* Get the PGD for the current thread and setup MMUCR */ | |
578 | 3: mfspr r11,SPRN_SPRG3 | |
579 | lwz r11,PGDIR(r11) | |
580 | mfspr r12,SPRN_PID /* Get PID */ | |
581 | 4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */ | |
582 | ||
583 | /* Mask of required permission bits. Note that while we | |
584 | * do copy ESR:ST to _PAGE_RW position as trying to write | |
585 | * to an RO page is pretty common, we don't do it with | |
586 | * _PAGE_DIRTY. We could do it, but it's a fairly rare | |
587 | * event so I'd rather take the overhead when it happens | |
588 | * rather than adding an instruction here. We should measure | |
589 | * whether the whole thing is worth it in the first place | |
590 | * as we could avoid loading SPRN_ESR completely in the first | |
591 | * place... | |
592 | * | |
593 | * TODO: Is it worth doing that mfspr & rlwimi in the first | |
594 | * place or can we save a couple of instructions here ? | |
595 | */ | |
596 | mfspr r12,SPRN_ESR | |
597 | li r13,_PAGE_PRESENT|_PAGE_ACCESSED | |
598 | rlwimi r13,r12,10,30,30 | |
599 | ||
600 | /* Load the PTE */ | |
601 | /* Compute pgdir/pmd offset */ | |
602 | rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29 | |
603 | lwzx r11,r12,r11 /* Get pgd/pmd entry */ | |
604 | ||
605 | /* Word 0 is EPN,V,TS,DSIZ */ | |
606 | li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE | |
607 | rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/ | |
608 | li r12,0 | |
609 | tlbwe r10,r12,0 | |
610 | ||
611 | /* XXX can we do better ? Need to make sure tlbwe has established | |
612 | * latch V bit in MMUCR0 before the PTE is loaded further down */ | |
613 | #ifdef CONFIG_SMP | |
614 | isync | |
615 | #endif | |
616 | ||
617 | rlwinm. r12,r11,0,0,20 /* Extract pt base address */ | |
618 | /* Compute pte address */ | |
619 | rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28 | |
620 | beq 2f /* Bail if no table */ | |
621 | lwz r11,0(r12) /* Get high word of pte entry */ | |
622 | ||
623 | /* XXX can we do better ? maybe insert a known 0 bit from r11 into the | |
624 | * bottom of r12 to create a data dependency... We can also use r10 | |
625 | * as destination nowadays | |
626 | */ | |
627 | #ifdef CONFIG_SMP | |
628 | lwsync | |
629 | #endif | |
630 | lwz r12,4(r12) /* Get low word of pte entry */ | |
631 | ||
632 | andc. r13,r13,r12 /* Check permission */ | |
633 | ||
634 | /* Jump to common tlb load */ | |
635 | beq finish_tlb_load_47x | |
636 | ||
637 | 2: /* The bailout. Restore registers to pre-exception conditions | |
638 | * and call the heavyweights to help us out. | |
639 | */ | |
640 | mfspr r11,SPRN_SPRG_RSCRATCH4 | |
641 | mtcr r11 | |
642 | mfspr r13,SPRN_SPRG_RSCRATCH3 | |
643 | mfspr r12,SPRN_SPRG_RSCRATCH2 | |
644 | mfspr r11,SPRN_SPRG_RSCRATCH1 | |
645 | mfspr r10,SPRN_SPRG_RSCRATCH0 | |
646 | b DataStorage | |
647 | ||
648 | /* Instruction TLB Error Interrupt */ | |
649 | /* | |
650 | * Nearly the same as above, except we get our | |
651 | * information from different registers and bailout | |
652 | * to a different point. | |
653 | */ | |
654 | START_EXCEPTION(InstructionTLBError47x) | |
655 | mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */ | |
656 | mtspr SPRN_SPRG_WSCRATCH1,r11 | |
657 | mtspr SPRN_SPRG_WSCRATCH2,r12 | |
658 | mtspr SPRN_SPRG_WSCRATCH3,r13 | |
659 | mfcr r11 | |
660 | mtspr SPRN_SPRG_WSCRATCH4,r11 | |
661 | mfspr r10,SPRN_SRR0 /* Get faulting address */ | |
662 | ||
663 | /* If we are faulting a kernel address, we have to use the | |
664 | * kernel page tables. | |
665 | */ | |
666 | lis r11,PAGE_OFFSET@h | |
667 | cmplw cr0,r10,r11 | |
668 | blt+ 3f | |
669 | lis r11,swapper_pg_dir@h | |
670 | ori r11,r11, swapper_pg_dir@l | |
671 | li r12,0 /* MMUCR = 0 */ | |
672 | b 4f | |
673 | ||
674 | /* Get the PGD for the current thread and setup MMUCR */ | |
675 | 3: mfspr r11,SPRN_SPRG_THREAD | |
676 | lwz r11,PGDIR(r11) | |
677 | mfspr r12,SPRN_PID /* Get PID */ | |
678 | 4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */ | |
679 | ||
680 | /* Make up the required permissions */ | |
681 | li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC | |
682 | ||
683 | /* Load PTE */ | |
684 | /* Compute pgdir/pmd offset */ | |
685 | rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29 | |
686 | lwzx r11,r12,r11 /* Get pgd/pmd entry */ | |
687 | ||
688 | /* Word 0 is EPN,V,TS,DSIZ */ | |
689 | li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE | |
690 | rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/ | |
691 | li r12,0 | |
692 | tlbwe r10,r12,0 | |
693 | ||
694 | /* XXX can we do better ? Need to make sure tlbwe has established | |
695 | * latch V bit in MMUCR0 before the PTE is loaded further down */ | |
696 | #ifdef CONFIG_SMP | |
697 | isync | |
698 | #endif | |
699 | ||
700 | rlwinm. r12,r11,0,0,20 /* Extract pt base address */ | |
701 | /* Compute pte address */ | |
702 | rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28 | |
703 | beq 2f /* Bail if no table */ | |
704 | ||
705 | lwz r11,0(r12) /* Get high word of pte entry */ | |
706 | /* XXX can we do better ? maybe insert a known 0 bit from r11 into the | |
707 | * bottom of r12 to create a data dependency... We can also use r10 | |
708 | * as destination nowadays | |
709 | */ | |
710 | #ifdef CONFIG_SMP | |
711 | lwsync | |
712 | #endif | |
713 | lwz r12,4(r12) /* Get low word of pte entry */ | |
714 | ||
715 | andc. r13,r13,r12 /* Check permission */ | |
716 | ||
717 | /* Jump to common TLB load point */ | |
718 | beq finish_tlb_load_47x | |
719 | ||
720 | 2: /* The bailout. Restore registers to pre-exception conditions | |
721 | * and call the heavyweights to help us out. | |
722 | */ | |
723 | mfspr r11, SPRN_SPRG_RSCRATCH4 | |
724 | mtcr r11 | |
725 | mfspr r13, SPRN_SPRG_RSCRATCH3 | |
726 | mfspr r12, SPRN_SPRG_RSCRATCH2 | |
727 | mfspr r11, SPRN_SPRG_RSCRATCH1 | |
728 | mfspr r10, SPRN_SPRG_RSCRATCH0 | |
729 | b InstructionStorage | |
730 | ||
731 | /* | |
732 | * Both the instruction and data TLB miss get to this | |
733 | * point to load the TLB. | |
734 | * r10 - free to use | |
735 | * r11 - PTE high word value | |
736 | * r12 - PTE low word value | |
737 | * r13 - free to use | |
738 | * MMUCR - loaded with proper value when we get here | |
739 | * Upon exit, we reload everything and RFI. | |
740 | */ | |
741 | finish_tlb_load_47x: | |
742 | /* Combine RPN & ERPN an write WS 1 */ | |
743 | rlwimi r11,r12,0,0,31-PAGE_SHIFT | |
744 | tlbwe r11,r13,1 | |
745 | ||
746 | /* And make up word 2 */ | |
747 | li r10,0xf85 /* Mask to apply from PTE */ | |
748 | rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */ | |
749 | and r11,r12,r10 /* Mask PTE bits to keep */ | |
750 | andi. r10,r12,_PAGE_USER /* User page ? */ | |
751 | beq 1f /* nope, leave U bits empty */ | |
752 | rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */ | |
753 | 1: tlbwe r11,r13,2 | |
754 | ||
755 | /* Done...restore registers and get out of here. | |
756 | */ | |
757 | mfspr r11, SPRN_SPRG_RSCRATCH4 | |
758 | mtcr r11 | |
759 | mfspr r13, SPRN_SPRG_RSCRATCH3 | |
760 | mfspr r12, SPRN_SPRG_RSCRATCH2 | |
761 | mfspr r11, SPRN_SPRG_RSCRATCH1 | |
762 | mfspr r10, SPRN_SPRG_RSCRATCH0 | |
763 | rfi | |
764 | ||
765 | #endif /* CONFIG_PPC_47x */ | |
766 | ||
767 | /* Debug Interrupt */ | |
768 | /* | |
769 | * This statement needs to exist at the end of the IVPR | |
770 | * definition just in case you end up taking a debug | |
771 | * exception within another exception. | |
772 | */ | |
773 | DEBUG_CRIT_EXCEPTION | |
774 | ||
fc2a6cfe BB |
775 | interrupt_end: |
776 | ||
14cf11af PM |
777 | /* |
778 | * Global functions | |
779 | */ | |
780 | ||
47c0bd1a BH |
781 | /* |
782 | * Adjust the machine check IVOR on 440A cores | |
783 | */ | |
784 | _GLOBAL(__fixup_440A_mcheck) | |
785 | li r3,MachineCheckA@l | |
786 | mtspr SPRN_IVOR1,r3 | |
787 | sync | |
788 | blr | |
789 | ||
14cf11af PM |
790 | _GLOBAL(set_context) |
791 | ||
792 | #ifdef CONFIG_BDI_SWITCH | |
793 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
794 | * The PGDIR is the second parameter. | |
795 | */ | |
796 | lis r5, abatron_pteptrs@h | |
797 | ori r5, r5, abatron_pteptrs@l | |
798 | stw r4, 0x4(r5) | |
799 | #endif | |
800 | mtspr SPRN_PID,r3 | |
801 | isync /* Force context change */ | |
802 | blr | |
803 | ||
795033c3 DK |
804 | /* |
805 | * Init CPU state. This is called at boot time or for secondary CPUs | |
806 | * to setup initial TLB entries, setup IVORs, etc... | |
e7f75ad0 | 807 | * |
795033c3 DK |
808 | */ |
809 | _GLOBAL(init_cpu_state) | |
810 | mflr r22 | |
e7f75ad0 | 811 | #ifdef CONFIG_PPC_47x |
446957ba | 812 | /* We use the PVR to differentiate 44x cores from 476 */ |
e7f75ad0 DK |
813 | mfspr r3,SPRN_PVR |
814 | srwi r3,r3,16 | |
df777bd3 TB |
815 | cmplwi cr0,r3,PVR_476FPE@h |
816 | beq head_start_47x | |
e7f75ad0 DK |
817 | cmplwi cr0,r3,PVR_476@h |
818 | beq head_start_47x | |
b4e8c8dd TS |
819 | cmplwi cr0,r3,PVR_476_ISS@h |
820 | beq head_start_47x | |
e7f75ad0 DK |
821 | #endif /* CONFIG_PPC_47x */ |
822 | ||
795033c3 DK |
823 | /* |
824 | * In case the firmware didn't do it, we apply some workarounds | |
825 | * that are good for all 440 core variants here | |
826 | */ | |
827 | mfspr r3,SPRN_CCR0 | |
828 | rlwinm r3,r3,0,0,27 /* disable icache prefetch */ | |
829 | isync | |
830 | mtspr SPRN_CCR0,r3 | |
831 | isync | |
832 | sync | |
833 | ||
834 | /* | |
e7f75ad0 | 835 | * Set up the initial MMU state for 44x |
795033c3 DK |
836 | * |
837 | * We are still executing code at the virtual address | |
838 | * mappings set by the firmware for the base of RAM. | |
839 | * | |
840 | * We first invalidate all TLB entries but the one | |
841 | * we are running from. We then load the KERNELBASE | |
842 | * mappings so we can begin to use kernel addresses | |
843 | * natively and so the interrupt vector locations are | |
844 | * permanently pinned (necessary since Book E | |
845 | * implementations always have translation enabled). | |
846 | * | |
847 | * TODO: Use the known TLB entry we are running from to | |
848 | * determine which physical region we are located | |
849 | * in. This can be used to determine where in RAM | |
850 | * (on a shared CPU system) or PCI memory space | |
851 | * (on a DRAMless system) we are located. | |
852 | * For now, we assume a perfect world which means | |
853 | * we are located at the base of DRAM (physical 0). | |
854 | */ | |
855 | ||
856 | /* | |
857 | * Search TLB for entry that we are currently using. | |
858 | * Invalidate all entries but the one we are using. | |
859 | */ | |
860 | /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */ | |
861 | mfspr r3,SPRN_PID /* Get PID */ | |
862 | mfmsr r4 /* Get MSR */ | |
863 | andi. r4,r4,MSR_IS@l /* TS=1? */ | |
864 | beq wmmucr /* If not, leave STS=0 */ | |
865 | oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */ | |
866 | wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */ | |
867 | sync | |
868 | ||
869 | bl invstr /* Find our address */ | |
870 | invstr: mflr r5 /* Make it accessible */ | |
871 | tlbsx r23,0,r5 /* Find entry we are in */ | |
872 | li r4,0 /* Start at TLB entry 0 */ | |
873 | li r3,0 /* Set PAGEID inval value */ | |
874 | 1: cmpw r23,r4 /* Is this our entry? */ | |
875 | beq skpinv /* If so, skip the inval */ | |
876 | tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ | |
877 | skpinv: addi r4,r4,1 /* Increment */ | |
878 | cmpwi r4,64 /* Are we done? */ | |
879 | bne 1b /* If not, repeat */ | |
880 | isync /* If so, context change */ | |
881 | ||
882 | /* | |
883 | * Configure and load pinned entry into TLB slot 63. | |
884 | */ | |
26ecb6c4 SP |
885 | #ifdef CONFIG_NONSTATIC_KERNEL |
886 | /* | |
887 | * In case of a NONSTATIC_KERNEL we reuse the TLB XLAT | |
888 | * entries of the initial mapping set by the boot loader. | |
889 | * The XLAT entry is stored in r25 | |
890 | */ | |
23913245 SP |
891 | |
892 | /* Read the XLAT entry for our current mapping */ | |
893 | tlbre r25,r23,PPC44x_TLB_XLAT | |
894 | ||
895 | lis r3,KERNELBASE@h | |
896 | ori r3,r3,KERNELBASE@l | |
897 | ||
898 | /* Use our current RPN entry */ | |
899 | mr r4,r25 | |
900 | #else | |
795033c3 DK |
901 | |
902 | lis r3,PAGE_OFFSET@h | |
903 | ori r3,r3,PAGE_OFFSET@l | |
904 | ||
905 | /* Kernel is at the base of RAM */ | |
906 | li r4, 0 /* Load the kernel physical address */ | |
23913245 | 907 | #endif |
795033c3 DK |
908 | |
909 | /* Load the kernel PID = 0 */ | |
910 | li r0,0 | |
911 | mtspr SPRN_PID,r0 | |
912 | sync | |
913 | ||
914 | /* Initialize MMUCR */ | |
915 | li r5,0 | |
916 | mtspr SPRN_MMUCR,r5 | |
917 | sync | |
918 | ||
919 | /* pageid fields */ | |
920 | clrrwi r3,r3,10 /* Mask off the effective page number */ | |
921 | ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M | |
922 | ||
923 | /* xlat fields */ | |
924 | clrrwi r4,r4,10 /* Mask off the real page number */ | |
925 | /* ERPN is 0 for first 4GB page */ | |
926 | ||
927 | /* attrib fields */ | |
928 | /* Added guarded bit to protect against speculative loads/stores */ | |
929 | li r5,0 | |
930 | ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) | |
931 | ||
932 | li r0,63 /* TLB slot 63 */ | |
933 | ||
934 | tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ | |
935 | tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ | |
936 | tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ | |
937 | ||
938 | /* Force context change */ | |
939 | mfmsr r0 | |
940 | mtspr SPRN_SRR1, r0 | |
941 | lis r0,3f@h | |
942 | ori r0,r0,3f@l | |
943 | mtspr SPRN_SRR0,r0 | |
944 | sync | |
945 | rfi | |
946 | ||
947 | /* If necessary, invalidate original entry we used */ | |
948 | 3: cmpwi r23,63 | |
949 | beq 4f | |
950 | li r6,0 | |
951 | tlbwe r6,r23,PPC44x_TLB_PAGEID | |
952 | isync | |
953 | ||
954 | 4: | |
955 | #ifdef CONFIG_PPC_EARLY_DEBUG_44x | |
956 | /* Add UART mapping for early debug. */ | |
957 | ||
958 | /* pageid fields */ | |
959 | lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h | |
960 | ori r3,r3,PPC44x_TLB_VALID|PPC44x_TLB_TS|PPC44x_TLB_64K | |
961 | ||
962 | /* xlat fields */ | |
963 | lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h | |
964 | ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH | |
965 | ||
966 | /* attrib fields */ | |
967 | li r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G) | |
968 | li r0,62 /* TLB slot 0 */ | |
969 | ||
970 | tlbwe r3,r0,PPC44x_TLB_PAGEID | |
971 | tlbwe r4,r0,PPC44x_TLB_XLAT | |
972 | tlbwe r5,r0,PPC44x_TLB_ATTRIB | |
973 | ||
974 | /* Force context change */ | |
975 | isync | |
976 | #endif /* CONFIG_PPC_EARLY_DEBUG_44x */ | |
977 | ||
978 | /* Establish the interrupt vector offsets */ | |
979 | SET_IVOR(0, CriticalInput); | |
980 | SET_IVOR(1, MachineCheck); | |
981 | SET_IVOR(2, DataStorage); | |
982 | SET_IVOR(3, InstructionStorage); | |
983 | SET_IVOR(4, ExternalInput); | |
984 | SET_IVOR(5, Alignment); | |
985 | SET_IVOR(6, Program); | |
986 | SET_IVOR(7, FloatingPointUnavailable); | |
987 | SET_IVOR(8, SystemCall); | |
988 | SET_IVOR(9, AuxillaryProcessorUnavailable); | |
989 | SET_IVOR(10, Decrementer); | |
990 | SET_IVOR(11, FixedIntervalTimer); | |
991 | SET_IVOR(12, WatchdogTimer); | |
e7f75ad0 DK |
992 | SET_IVOR(13, DataTLBError44x); |
993 | SET_IVOR(14, InstructionTLBError44x); | |
795033c3 DK |
994 | SET_IVOR(15, DebugCrit); |
995 | ||
e7f75ad0 DK |
996 | b head_start_common |
997 | ||
998 | ||
999 | #ifdef CONFIG_PPC_47x | |
1000 | ||
1001 | #ifdef CONFIG_SMP | |
1002 | ||
1003 | /* Entry point for secondary 47x processors */ | |
1004 | _GLOBAL(start_secondary_47x) | |
1005 | mr r24,r3 /* CPU number */ | |
1006 | ||
1007 | bl init_cpu_state | |
1008 | ||
1009 | /* Now we need to bolt the rest of kernel memory which | |
1010 | * is done in C code. We must be careful because our task | |
1011 | * struct or our stack can (and will probably) be out | |
1012 | * of reach of the initial 256M TLB entry, so we use a | |
1013 | * small temporary stack in .bss for that. This works | |
1014 | * because only one CPU at a time can be in this code | |
1015 | */ | |
1016 | lis r1,temp_boot_stack@h | |
1017 | ori r1,r1,temp_boot_stack@l | |
1018 | addi r1,r1,1024-STACK_FRAME_OVERHEAD | |
1019 | li r0,0 | |
1020 | stw r0,0(r1) | |
1021 | bl mmu_init_secondary | |
1022 | ||
1023 | /* Now we can get our task struct and real stack pointer */ | |
1024 | ||
4e67bfd7 | 1025 | /* Get current's stack and current */ |
7c19c2e5 CL |
1026 | lis r2,secondary_current@ha |
1027 | lwz r2,secondary_current@l(r2) | |
ed1cd6de | 1028 | lwz r1,TASK_STACK(r2) |
e7f75ad0 DK |
1029 | |
1030 | /* Current stack pointer */ | |
1031 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
1032 | li r0,0 | |
1033 | stw r0,0(r1) | |
1034 | ||
1035 | /* Kernel stack for exception entry in SPRG3 */ | |
1036 | addi r4,r2,THREAD /* init task's THREAD */ | |
1037 | mtspr SPRN_SPRG3,r4 | |
1038 | ||
1039 | b start_secondary | |
1040 | ||
1041 | #endif /* CONFIG_SMP */ | |
1042 | ||
1043 | /* | |
1044 | * Set up the initial MMU state for 44x | |
1045 | * | |
1046 | * We are still executing code at the virtual address | |
1047 | * mappings set by the firmware for the base of RAM. | |
1048 | */ | |
1049 | ||
1050 | head_start_47x: | |
1051 | /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */ | |
1052 | mfspr r3,SPRN_PID /* Get PID */ | |
1053 | mfmsr r4 /* Get MSR */ | |
1054 | andi. r4,r4,MSR_IS@l /* TS=1? */ | |
1055 | beq 1f /* If not, leave STS=0 */ | |
1056 | oris r3,r3,PPC47x_MMUCR_STS@h /* Set STS=1 */ | |
1057 | 1: mtspr SPRN_MMUCR,r3 /* Put MMUCR */ | |
1058 | sync | |
1059 | ||
1060 | /* Find the entry we are running from */ | |
1061 | bl 1f | |
1062 | 1: mflr r23 | |
1063 | tlbsx r23,0,r23 | |
1064 | tlbre r24,r23,0 | |
1065 | tlbre r25,r23,1 | |
1066 | tlbre r26,r23,2 | |
1067 | ||
1068 | /* | |
1069 | * Cleanup time | |
1070 | */ | |
1071 | ||
1072 | /* Initialize MMUCR */ | |
1073 | li r5,0 | |
1074 | mtspr SPRN_MMUCR,r5 | |
1075 | sync | |
1076 | ||
1077 | clear_all_utlb_entries: | |
1078 | ||
1079 | #; Set initial values. | |
1080 | ||
1081 | addis r3,0,0x8000 | |
1082 | addi r4,0,0 | |
1083 | addi r5,0,0 | |
1084 | b clear_utlb_entry | |
1085 | ||
1086 | #; Align the loop to speed things up. | |
1087 | ||
1088 | .align 6 | |
1089 | ||
1090 | clear_utlb_entry: | |
1091 | ||
1092 | tlbwe r4,r3,0 | |
1093 | tlbwe r5,r3,1 | |
1094 | tlbwe r5,r3,2 | |
1095 | addis r3,r3,0x2000 | |
1096 | cmpwi r3,0 | |
1097 | bne clear_utlb_entry | |
1098 | addis r3,0,0x8000 | |
1099 | addis r4,r4,0x100 | |
1100 | cmpwi r4,0 | |
1101 | bne clear_utlb_entry | |
1102 | ||
1103 | #; Restore original entry. | |
1104 | ||
1105 | oris r23,r23,0x8000 /* specify the way */ | |
1106 | tlbwe r24,r23,0 | |
1107 | tlbwe r25,r23,1 | |
1108 | tlbwe r26,r23,2 | |
1109 | ||
1110 | /* | |
1111 | * Configure and load pinned entry into TLB for the kernel core | |
1112 | */ | |
1113 | ||
1114 | lis r3,PAGE_OFFSET@h | |
1115 | ori r3,r3,PAGE_OFFSET@l | |
1116 | ||
e7f75ad0 DK |
1117 | /* Load the kernel PID = 0 */ |
1118 | li r0,0 | |
1119 | mtspr SPRN_PID,r0 | |
1120 | sync | |
1121 | ||
1122 | /* Word 0 */ | |
1123 | clrrwi r3,r3,12 /* Mask off the effective page number */ | |
1124 | ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M | |
1125 | ||
9661534d DK |
1126 | /* Word 1 - use r25. RPN is the same as the original entry */ |
1127 | ||
e7f75ad0 DK |
1128 | /* Word 2 */ |
1129 | li r5,0 | |
1130 | ori r5,r5,PPC47x_TLB2_S_RWX | |
1131 | #ifdef CONFIG_SMP | |
1132 | ori r5,r5,PPC47x_TLB2_M | |
1133 | #endif | |
1134 | ||
1135 | /* We write to way 0 and bolted 0 */ | |
1136 | lis r0,0x8800 | |
1137 | tlbwe r3,r0,0 | |
9661534d | 1138 | tlbwe r25,r0,1 |
e7f75ad0 DK |
1139 | tlbwe r5,r0,2 |
1140 | ||
1141 | /* | |
1142 | * Configure SSPCR, ISPCR and USPCR for now to search everything, we can fix | |
1143 | * them up later | |
1144 | */ | |
1145 | LOAD_REG_IMMEDIATE(r3, 0x9abcdef0) | |
1146 | mtspr SPRN_SSPCR,r3 | |
1147 | mtspr SPRN_USPCR,r3 | |
1148 | LOAD_REG_IMMEDIATE(r3, 0x12345670) | |
1149 | mtspr SPRN_ISPCR,r3 | |
1150 | ||
1151 | /* Force context change */ | |
1152 | mfmsr r0 | |
1153 | mtspr SPRN_SRR1, r0 | |
1154 | lis r0,3f@h | |
1155 | ori r0,r0,3f@l | |
1156 | mtspr SPRN_SRR0,r0 | |
1157 | sync | |
1158 | rfi | |
1159 | ||
1160 | /* Invalidate original entry we used */ | |
1161 | 3: | |
1162 | rlwinm r24,r24,0,21,19 /* clear the "valid" bit */ | |
1163 | tlbwe r24,r23,0 | |
1164 | addi r24,0,0 | |
1165 | tlbwe r24,r23,1 | |
1166 | tlbwe r24,r23,2 | |
1167 | isync /* Clear out the shadow TLB entries */ | |
1168 | ||
1169 | #ifdef CONFIG_PPC_EARLY_DEBUG_44x | |
1170 | /* Add UART mapping for early debug. */ | |
1171 | ||
1172 | /* Word 0 */ | |
1173 | lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h | |
1174 | ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_TS | PPC47x_TLB0_1M | |
1175 | ||
1176 | /* Word 1 */ | |
1177 | lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h | |
1178 | ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH | |
1179 | ||
1180 | /* Word 2 */ | |
1181 | li r5,(PPC47x_TLB2_S_RW | PPC47x_TLB2_IMG) | |
1182 | ||
1183 | /* Bolted in way 0, bolt slot 5, we -hope- we don't hit the same | |
1184 | * congruence class as the kernel, we need to make sure of it at | |
1185 | * some point | |
1186 | */ | |
1187 | lis r0,0x8d00 | |
1188 | tlbwe r3,r0,0 | |
1189 | tlbwe r4,r0,1 | |
1190 | tlbwe r5,r0,2 | |
1191 | ||
1192 | /* Force context change */ | |
1193 | isync | |
1194 | #endif /* CONFIG_PPC_EARLY_DEBUG_44x */ | |
1195 | ||
1196 | /* Establish the interrupt vector offsets */ | |
1197 | SET_IVOR(0, CriticalInput); | |
1198 | SET_IVOR(1, MachineCheckA); | |
1199 | SET_IVOR(2, DataStorage); | |
1200 | SET_IVOR(3, InstructionStorage); | |
1201 | SET_IVOR(4, ExternalInput); | |
1202 | SET_IVOR(5, Alignment); | |
1203 | SET_IVOR(6, Program); | |
1204 | SET_IVOR(7, FloatingPointUnavailable); | |
1205 | SET_IVOR(8, SystemCall); | |
1206 | SET_IVOR(9, AuxillaryProcessorUnavailable); | |
1207 | SET_IVOR(10, Decrementer); | |
1208 | SET_IVOR(11, FixedIntervalTimer); | |
1209 | SET_IVOR(12, WatchdogTimer); | |
1210 | SET_IVOR(13, DataTLBError47x); | |
1211 | SET_IVOR(14, InstructionTLBError47x); | |
1212 | SET_IVOR(15, DebugCrit); | |
1213 | ||
1214 | /* We configure icbi to invalidate 128 bytes at a time since the | |
1215 | * current 32-bit kernel code isn't too happy with icache != dcache | |
97b3be1e AP |
1216 | * block size. We also disable the BTAC as this can cause errors |
1217 | * in some circumstances (see IBM Erratum 47). | |
e7f75ad0 DK |
1218 | */ |
1219 | mfspr r3,SPRN_CCR0 | |
1220 | oris r3,r3,0x0020 | |
97b3be1e | 1221 | ori r3,r3,0x0040 |
e7f75ad0 DK |
1222 | mtspr SPRN_CCR0,r3 |
1223 | isync | |
1224 | ||
1225 | #endif /* CONFIG_PPC_47x */ | |
1226 | ||
1227 | /* | |
1228 | * Here we are back to code that is common between 44x and 47x | |
1229 | * | |
1230 | * We proceed to further kernel initialization and return to the | |
1231 | * main kernel entry | |
1232 | */ | |
1233 | head_start_common: | |
795033c3 DK |
1234 | /* Establish the interrupt vector base */ |
1235 | lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ | |
1236 | mtspr SPRN_IVPR,r4 | |
1237 | ||
9661534d DK |
1238 | /* |
1239 | * If the kernel was loaded at a non-zero 256 MB page, we need to | |
1240 | * mask off the most significant 4 bits to get the relative address | |
1241 | * from the start of physical memory | |
1242 | */ | |
1243 | rlwinm r22,r22,0,4,31 | |
1244 | addis r22,r22,PAGE_OFFSET@h | |
795033c3 | 1245 | mtlr r22 |
e7f75ad0 | 1246 | isync |
795033c3 DK |
1247 | blr |
1248 | ||
14cf11af PM |
1249 | /* |
1250 | * We put a few things here that have to be page-aligned. This stuff | |
1251 | * goes at the beginning of the data segment, which is page-aligned. | |
1252 | */ | |
1253 | .data | |
ca9153a3 | 1254 | .align PAGE_SHIFT |
ea703ce2 KG |
1255 | .globl sdata |
1256 | sdata: | |
1257 | .globl empty_zero_page | |
1258 | empty_zero_page: | |
ca9153a3 | 1259 | .space PAGE_SIZE |
9445aa1a | 1260 | EXPORT_SYMBOL(empty_zero_page) |
14cf11af PM |
1261 | |
1262 | /* | |
1263 | * To support >32-bit physical addresses, we use an 8KB pgdir. | |
1264 | */ | |
ea703ce2 KG |
1265 | .globl swapper_pg_dir |
1266 | swapper_pg_dir: | |
bee86f14 | 1267 | .space PGD_TABLE_SIZE |
14cf11af | 1268 | |
14cf11af PM |
1269 | /* |
1270 | * Room for two PTE pointers, usually the kernel and current user pointers | |
1271 | * to their respective root page table. | |
1272 | */ | |
1273 | abatron_pteptrs: | |
1274 | .space 8 | |
e7f75ad0 DK |
1275 | |
1276 | #ifdef CONFIG_SMP | |
1277 | .align 12 | |
1278 | temp_boot_stack: | |
1279 | .space 1024 | |
1280 | #endif /* CONFIG_SMP */ |