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9994a338 PM |
1 | /* |
2 | * PowerPC version | |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP | |
5 | * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com> | |
6 | * Adapted for Power Macintosh by Paul Mackerras. | |
7 | * Low-level exception handlers and MMU support | |
8 | * rewritten by Paul Mackerras. | |
9 | * Copyright (C) 1996 Paul Mackerras. | |
10 | * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). | |
11 | * | |
12 | * This file contains the system call entry code, context switch | |
13 | * code, and exception/interrupt return code for PowerPC. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | * | |
20 | */ | |
21 | ||
9994a338 | 22 | #include <linux/errno.h> |
c3525940 | 23 | #include <linux/err.h> |
9994a338 PM |
24 | #include <linux/sys.h> |
25 | #include <linux/threads.h> | |
26 | #include <asm/reg.h> | |
27 | #include <asm/page.h> | |
28 | #include <asm/mmu.h> | |
29 | #include <asm/cputable.h> | |
30 | #include <asm/thread_info.h> | |
31 | #include <asm/ppc_asm.h> | |
32 | #include <asm/asm-offsets.h> | |
33 | #include <asm/unistd.h> | |
46f52210 | 34 | #include <asm/ptrace.h> |
9445aa1a | 35 | #include <asm/export.h> |
36a7eeaf | 36 | #include <asm/asm-405.h> |
2c86cd18 | 37 | #include <asm/feature-fixups.h> |
c28218d4 | 38 | #include <asm/barrier.h> |
e2fb9f54 | 39 | #include <asm/kup.h> |
9994a338 | 40 | |
9994a338 PM |
41 | /* |
42 | * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE. | |
43 | */ | |
44 | #if MSR_KERNEL >= 0x10000 | |
45 | #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l | |
46 | #else | |
47 | #define LOAD_MSR_KERNEL(r, x) li r,(x) | |
48 | #endif | |
49 | ||
0eb0d2e7 CL |
50 | /* |
51 | * Align to 4k in order to ensure that all functions modyfing srr0/srr1 | |
52 | * fit into one page in order to not encounter a TLB miss between the | |
53 | * modification of srr0/srr1 and the associated rfi. | |
54 | */ | |
55 | .align 12 | |
56 | ||
9994a338 | 57 | #ifdef CONFIG_BOOKE |
9994a338 PM |
58 | .globl mcheck_transfer_to_handler |
59 | mcheck_transfer_to_handler: | |
fca622c5 KG |
60 | mfspr r0,SPRN_DSRR0 |
61 | stw r0,_DSRR0(r11) | |
62 | mfspr r0,SPRN_DSRR1 | |
63 | stw r0,_DSRR1(r11) | |
64 | /* fall through */ | |
9994a338 PM |
65 | |
66 | .globl debug_transfer_to_handler | |
67 | debug_transfer_to_handler: | |
fca622c5 KG |
68 | mfspr r0,SPRN_CSRR0 |
69 | stw r0,_CSRR0(r11) | |
70 | mfspr r0,SPRN_CSRR1 | |
71 | stw r0,_CSRR1(r11) | |
72 | /* fall through */ | |
9994a338 PM |
73 | |
74 | .globl crit_transfer_to_handler | |
75 | crit_transfer_to_handler: | |
70fe3af8 | 76 | #ifdef CONFIG_PPC_BOOK3E_MMU |
fca622c5 KG |
77 | mfspr r0,SPRN_MAS0 |
78 | stw r0,MAS0(r11) | |
79 | mfspr r0,SPRN_MAS1 | |
80 | stw r0,MAS1(r11) | |
81 | mfspr r0,SPRN_MAS2 | |
82 | stw r0,MAS2(r11) | |
83 | mfspr r0,SPRN_MAS3 | |
84 | stw r0,MAS3(r11) | |
85 | mfspr r0,SPRN_MAS6 | |
86 | stw r0,MAS6(r11) | |
87 | #ifdef CONFIG_PHYS_64BIT | |
88 | mfspr r0,SPRN_MAS7 | |
89 | stw r0,MAS7(r11) | |
90 | #endif /* CONFIG_PHYS_64BIT */ | |
70fe3af8 | 91 | #endif /* CONFIG_PPC_BOOK3E_MMU */ |
fca622c5 KG |
92 | #ifdef CONFIG_44x |
93 | mfspr r0,SPRN_MMUCR | |
94 | stw r0,MMUCR(r11) | |
95 | #endif | |
96 | mfspr r0,SPRN_SRR0 | |
97 | stw r0,_SRR0(r11) | |
98 | mfspr r0,SPRN_SRR1 | |
99 | stw r0,_SRR1(r11) | |
100 | ||
a7916a1d | 101 | /* set the stack limit to the current stack */ |
ee43eb78 | 102 | mfspr r8,SPRN_SPRG_THREAD |
fca622c5 KG |
103 | lwz r0,KSP_LIMIT(r8) |
104 | stw r0,SAVED_KSP_LIMIT(r11) | |
a7916a1d | 105 | rlwinm r0,r1,0,0,(31 - THREAD_SHIFT) |
fca622c5 | 106 | stw r0,KSP_LIMIT(r8) |
9994a338 PM |
107 | /* fall through */ |
108 | #endif | |
109 | ||
110 | #ifdef CONFIG_40x | |
111 | .globl crit_transfer_to_handler | |
112 | crit_transfer_to_handler: | |
113 | lwz r0,crit_r10@l(0) | |
114 | stw r0,GPR10(r11) | |
115 | lwz r0,crit_r11@l(0) | |
116 | stw r0,GPR11(r11) | |
fca622c5 KG |
117 | mfspr r0,SPRN_SRR0 |
118 | stw r0,crit_srr0@l(0) | |
119 | mfspr r0,SPRN_SRR1 | |
120 | stw r0,crit_srr1@l(0) | |
121 | ||
a7916a1d | 122 | /* set the stack limit to the current stack */ |
ee43eb78 | 123 | mfspr r8,SPRN_SPRG_THREAD |
fca622c5 KG |
124 | lwz r0,KSP_LIMIT(r8) |
125 | stw r0,saved_ksp_limit@l(0) | |
a7916a1d | 126 | rlwinm r0,r1,0,0,(31 - THREAD_SHIFT) |
fca622c5 | 127 | stw r0,KSP_LIMIT(r8) |
9994a338 PM |
128 | /* fall through */ |
129 | #endif | |
130 | ||
131 | /* | |
132 | * This code finishes saving the registers to the exception frame | |
133 | * and jumps to the appropriate handler for the exception, turning | |
134 | * on address translation. | |
135 | * Note that we rely on the caller having set cr0.eq iff the exception | |
136 | * occurred in kernel mode (i.e. MSR:PR = 0). | |
137 | */ | |
138 | .globl transfer_to_handler_full | |
139 | transfer_to_handler_full: | |
140 | SAVE_NVGPRS(r11) | |
141 | /* fall through */ | |
142 | ||
143 | .globl transfer_to_handler | |
144 | transfer_to_handler: | |
145 | stw r2,GPR2(r11) | |
146 | stw r12,_NIP(r11) | |
147 | stw r9,_MSR(r11) | |
148 | andi. r2,r9,MSR_PR | |
149 | mfctr r12 | |
150 | mfspr r2,SPRN_XER | |
151 | stw r12,_CTR(r11) | |
152 | stw r2,_XER(r11) | |
ee43eb78 | 153 | mfspr r12,SPRN_SPRG_THREAD |
9994a338 | 154 | beq 2f /* if from user, fix up THREAD.regs */ |
e2fb9f54 | 155 | addi r2, r12, -THREAD |
9994a338 PM |
156 | addi r11,r1,STACK_FRAME_OVERHEAD |
157 | stw r11,PT_REGS(r12) | |
158 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
159 | /* Check to see if the dbcr0 register is set up to debug. Use the | |
4eaddb4d | 160 | internal debug mode bit to do this. */ |
9994a338 | 161 | lwz r12,THREAD_DBCR0(r12) |
2325f0a0 | 162 | andis. r12,r12,DBCR0_IDM@h |
6b9166f0 | 163 | #endif |
f7354cca | 164 | ACCOUNT_CPU_USER_ENTRY(r2, r11, r12) |
6b9166f0 | 165 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) |
9994a338 PM |
166 | beq+ 3f |
167 | /* From user and task is ptraced - load up global dbcr0 */ | |
168 | li r12,-1 /* clear all pending debug events */ | |
169 | mtspr SPRN_DBSR,r12 | |
170 | lis r11,global_dbcr0@ha | |
171 | tophys(r11,r11) | |
172 | addi r11,r11,global_dbcr0@l | |
4eaddb4d | 173 | #ifdef CONFIG_SMP |
f7354cca | 174 | lwz r9,TASK_CPU(r2) |
4eaddb4d KG |
175 | slwi r9,r9,3 |
176 | add r11,r11,r9 | |
177 | #endif | |
9994a338 PM |
178 | lwz r12,0(r11) |
179 | mtspr SPRN_DBCR0,r12 | |
180 | lwz r12,4(r11) | |
181 | addi r12,r12,-1 | |
182 | stw r12,4(r11) | |
183 | #endif | |
c223c903 | 184 | |
9994a338 | 185 | b 3f |
f39224a8 | 186 | |
9994a338 PM |
187 | 2: /* if from kernel, check interrupted DOZE/NAP mode and |
188 | * check for stack overflow | |
189 | */ | |
e2fb9f54 CL |
190 | kuap_save_and_lock r11, r12, r9, r2, r0 |
191 | addi r2, r12, -THREAD | |
85218827 KG |
192 | lwz r9,KSP_LIMIT(r12) |
193 | cmplw r1,r9 /* if r1 <= ksp_limit */ | |
f39224a8 PM |
194 | ble- stack_ovf /* then the kernel stack overflowed */ |
195 | 5: | |
d7cceda9 | 196 | #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500) |
f7354cca | 197 | lwz r12,TI_LOCAL_FLAGS(r2) |
f39224a8 PM |
198 | mtcrf 0x01,r12 |
199 | bt- 31-TLF_NAPPING,4f | |
a560643e | 200 | bt- 31-TLF_SLEEPING,7f |
d7cceda9 | 201 | #endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_E500 */ |
9994a338 PM |
202 | .globl transfer_to_handler_cont |
203 | transfer_to_handler_cont: | |
9994a338 PM |
204 | 3: |
205 | mflr r9 | |
f7354cca | 206 | tovirt(r2, r2) /* set r2 to current */ |
9994a338 PM |
207 | lwz r11,0(r9) /* virtual address of handler */ |
208 | lwz r9,4(r9) /* where to go when done */ | |
cd99ddbe | 209 | #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) |
75b82472 CL |
210 | mtspr SPRN_NRI, r0 |
211 | #endif | |
5d38902c BH |
212 | #ifdef CONFIG_TRACE_IRQFLAGS |
213 | lis r12,reenable_mmu@h | |
214 | ori r12,r12,reenable_mmu@l | |
215 | mtspr SPRN_SRR0,r12 | |
216 | mtspr SPRN_SRR1,r10 | |
217 | SYNC | |
218 | RFI | |
219 | reenable_mmu: /* re-enable mmu so we can */ | |
220 | mfmsr r10 | |
221 | lwz r12,_MSR(r1) | |
222 | xor r10,r10,r12 | |
223 | andi. r10,r10,MSR_EE /* Did EE change? */ | |
224 | beq 1f | |
225 | ||
2cd76629 KH |
226 | /* |
227 | * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1. | |
228 | * If from user mode there is only one stack frame on the stack, and | |
229 | * accessing CALLER_ADDR1 will cause oops. So we need create a dummy | |
230 | * stack frame to make trace_hardirqs_off happy. | |
08f1ec8a BH |
231 | * |
232 | * This is handy because we also need to save a bunch of GPRs, | |
233 | * r3 can be different from GPR3(r1) at this point, r9 and r11 | |
234 | * contains the old MSR and handler address respectively, | |
235 | * r4 & r5 can contain page fault arguments that need to be passed | |
236 | * along as well. r12, CCR, CTR, XER etc... are left clobbered as | |
237 | * they aren't useful past this point (aren't syscall arguments), | |
238 | * the rest is restored from the exception frame. | |
2cd76629 | 239 | */ |
08f1ec8a BH |
240 | stwu r1,-32(r1) |
241 | stw r9,8(r1) | |
242 | stw r11,12(r1) | |
243 | stw r3,16(r1) | |
244 | stw r4,20(r1) | |
245 | stw r5,24(r1) | |
2cd76629 | 246 | bl trace_hardirqs_off |
08f1ec8a BH |
247 | lwz r5,24(r1) |
248 | lwz r4,20(r1) | |
249 | lwz r3,16(r1) | |
250 | lwz r11,12(r1) | |
251 | lwz r9,8(r1) | |
252 | addi r1,r1,32 | |
5d38902c | 253 | lwz r0,GPR0(r1) |
5d38902c BH |
254 | lwz r6,GPR6(r1) |
255 | lwz r7,GPR7(r1) | |
256 | lwz r8,GPR8(r1) | |
5d38902c BH |
257 | 1: mtctr r11 |
258 | mtlr r9 | |
259 | bctr /* jump to handler */ | |
260 | #else /* CONFIG_TRACE_IRQFLAGS */ | |
9994a338 PM |
261 | mtspr SPRN_SRR0,r11 |
262 | mtspr SPRN_SRR1,r10 | |
263 | mtlr r9 | |
264 | SYNC | |
265 | RFI /* jump to handler, enable MMU */ | |
5d38902c | 266 | #endif /* CONFIG_TRACE_IRQFLAGS */ |
9994a338 | 267 | |
d7cceda9 | 268 | #if defined (CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500) |
f39224a8 | 269 | 4: rlwinm r12,r12,0,~_TLF_NAPPING |
f7354cca | 270 | stw r12,TI_LOCAL_FLAGS(r2) |
fc4033b2 | 271 | b power_save_ppc32_restore |
a560643e PM |
272 | |
273 | 7: rlwinm r12,r12,0,~_TLF_SLEEPING | |
f7354cca | 274 | stw r12,TI_LOCAL_FLAGS(r2) |
a560643e PM |
275 | lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */ |
276 | rlwinm r9,r9,0,~MSR_EE | |
277 | lwz r12,_LINK(r11) /* and return to address in LR */ | |
e2fb9f54 | 278 | kuap_restore r11, r2, r3, r4, r5 |
a560643e | 279 | b fast_exception_return |
a0652fc9 PM |
280 | #endif |
281 | ||
9994a338 PM |
282 | /* |
283 | * On kernel stack overflow, load up an initial stack pointer | |
284 | * and call StackOverflow(regs), which should not return. | |
285 | */ | |
286 | stack_ovf: | |
287 | /* sometimes we use a statically-allocated stack, which is OK. */ | |
f39224a8 PM |
288 | lis r12,_end@h |
289 | ori r12,r12,_end@l | |
290 | cmplw r1,r12 | |
291 | ble 5b /* r1 <= &_end is OK */ | |
9994a338 PM |
292 | SAVE_NVGPRS(r11) |
293 | addi r3,r1,STACK_FRAME_OVERHEAD | |
294 | lis r1,init_thread_union@ha | |
295 | addi r1,r1,init_thread_union@l | |
296 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
297 | lis r9,StackOverflow@ha | |
298 | addi r9,r9,StackOverflow@l | |
299 | LOAD_MSR_KERNEL(r10,MSR_KERNEL) | |
cd99ddbe | 300 | #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) |
75b82472 CL |
301 | mtspr SPRN_NRI, r0 |
302 | #endif | |
9994a338 PM |
303 | mtspr SPRN_SRR0,r9 |
304 | mtspr SPRN_SRR1,r10 | |
305 | SYNC | |
306 | RFI | |
307 | ||
308 | /* | |
309 | * Handle a system call. | |
310 | */ | |
311 | .stabs "arch/powerpc/kernel/",N_SO,0,0,0f | |
312 | .stabs "entry_32.S",N_SO,0,0,0f | |
313 | 0: | |
314 | ||
315 | _GLOBAL(DoSyscall) | |
9994a338 PM |
316 | stw r3,ORIG_GPR3(r1) |
317 | li r12,0 | |
318 | stw r12,RESULT(r1) | |
319 | lwz r11,_CCR(r1) /* Clear SO bit in CR */ | |
320 | rlwinm r11,r11,0,4,2 | |
321 | stw r11,_CCR(r1) | |
5d38902c BH |
322 | #ifdef CONFIG_TRACE_IRQFLAGS |
323 | /* Return from syscalls can (and generally will) hard enable | |
324 | * interrupts. You aren't supposed to call a syscall with | |
325 | * interrupts disabled in the first place. However, to ensure | |
326 | * that we get it right vs. lockdep if it happens, we force | |
327 | * that hard enable here with appropriate tracing if we see | |
328 | * that we have been called with interrupts off | |
329 | */ | |
330 | mfmsr r11 | |
331 | andi. r12,r11,MSR_EE | |
332 | bne+ 1f | |
333 | /* We came in with interrupts disabled, we enable them now */ | |
334 | bl trace_hardirqs_on | |
335 | mfmsr r11 | |
336 | lwz r0,GPR0(r1) | |
337 | lwz r3,GPR3(r1) | |
338 | lwz r4,GPR4(r1) | |
339 | ori r11,r11,MSR_EE | |
340 | lwz r5,GPR5(r1) | |
341 | lwz r6,GPR6(r1) | |
342 | lwz r7,GPR7(r1) | |
343 | lwz r8,GPR8(r1) | |
344 | mtmsr r11 | |
345 | 1: | |
346 | #endif /* CONFIG_TRACE_IRQFLAGS */ | |
f7354cca | 347 | lwz r11,TI_FLAGS(r2) |
10ea8343 | 348 | andi. r11,r11,_TIF_SYSCALL_DOTRACE |
9994a338 PM |
349 | bne- syscall_dotrace |
350 | syscall_dotrace_cont: | |
351 | cmplwi 0,r0,NR_syscalls | |
352 | lis r10,sys_call_table@h | |
353 | ori r10,r10,sys_call_table@l | |
354 | slwi r0,r0,2 | |
355 | bge- 66f | |
c28218d4 DC |
356 | |
357 | barrier_nospec_asm | |
358 | /* | |
359 | * Prevent the load of the handler below (based on the user-passed | |
360 | * system call number) being speculatively executed until the test | |
361 | * against NR_syscalls and branch to .66f above has | |
362 | * committed. | |
363 | */ | |
364 | ||
9994a338 PM |
365 | lwzx r10,r10,r0 /* Fetch system call handler [ptr] */ |
366 | mtlr r10 | |
367 | addi r9,r1,STACK_FRAME_OVERHEAD | |
368 | PPC440EP_ERR42 | |
369 | blrl /* Call handler */ | |
370 | .globl ret_from_syscall | |
371 | ret_from_syscall: | |
6f37be4b BF |
372 | #ifdef CONFIG_DEBUG_RSEQ |
373 | /* Check whether the syscall is issued inside a restartable sequence */ | |
374 | stw r3,GPR3(r1) | |
375 | addi r3,r1,STACK_FRAME_OVERHEAD | |
376 | bl rseq_syscall | |
377 | lwz r3,GPR3(r1) | |
378 | #endif | |
9994a338 | 379 | mr r6,r3 |
9994a338 | 380 | /* disable interrupts so current_thread_info()->flags can't change */ |
401d1f02 | 381 | LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */ |
5d38902c | 382 | /* Note: We don't bother telling lockdep about it */ |
9994a338 PM |
383 | SYNC |
384 | MTMSRD(r10) | |
f7354cca | 385 | lwz r9,TI_FLAGS(r2) |
c3525940 | 386 | li r8,-MAX_ERRNO |
10ea8343 | 387 | andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK) |
9994a338 | 388 | bne- syscall_exit_work |
401d1f02 DW |
389 | cmplw 0,r3,r8 |
390 | blt+ syscall_exit_cont | |
391 | lwz r11,_CCR(r1) /* Load CR */ | |
392 | neg r3,r3 | |
393 | oris r11,r11,0x1000 /* Set SO bit in CR */ | |
394 | stw r11,_CCR(r1) | |
9994a338 | 395 | syscall_exit_cont: |
5d38902c BH |
396 | lwz r8,_MSR(r1) |
397 | #ifdef CONFIG_TRACE_IRQFLAGS | |
398 | /* If we are going to return from the syscall with interrupts | |
399 | * off, we trace that here. It shouldn't happen though but we | |
400 | * want to catch the bugger if it does right ? | |
401 | */ | |
402 | andi. r10,r8,MSR_EE | |
403 | bne+ 1f | |
404 | stw r3,GPR3(r1) | |
405 | bl trace_hardirqs_off | |
406 | lwz r3,GPR3(r1) | |
407 | 1: | |
408 | #endif /* CONFIG_TRACE_IRQFLAGS */ | |
9994a338 | 409 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) |
4eaddb4d KG |
410 | /* If the process has its own DBCR0 value, load it up. The internal |
411 | debug mode bit tells us that dbcr0 should be loaded. */ | |
9994a338 | 412 | lwz r0,THREAD+THREAD_DBCR0(r2) |
2325f0a0 | 413 | andis. r10,r0,DBCR0_IDM@h |
9994a338 PM |
414 | bnel- load_dbcr0 |
415 | #endif | |
b98ac05d | 416 | #ifdef CONFIG_44x |
e7f75ad0 | 417 | BEGIN_MMU_FTR_SECTION |
b98ac05d BH |
418 | lis r4,icache_44x_need_flush@ha |
419 | lwz r5,icache_44x_need_flush@l(r4) | |
420 | cmplwi cr0,r5,0 | |
421 | bne- 2f | |
422 | 1: | |
e7f75ad0 | 423 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x) |
b98ac05d | 424 | #endif /* CONFIG_44x */ |
b64f87c1 BB |
425 | BEGIN_FTR_SECTION |
426 | lwarx r7,0,r1 | |
427 | END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) | |
9994a338 | 428 | stwcx. r0,0,r1 /* to clear the reservation */ |
f7354cca | 429 | ACCOUNT_CPU_USER_EXIT(r2, r5, r7) |
e2fb9f54 | 430 | kuap_check r2, r4 |
9994a338 PM |
431 | lwz r4,_LINK(r1) |
432 | lwz r5,_CCR(r1) | |
433 | mtlr r4 | |
434 | mtcr r5 | |
435 | lwz r7,_NIP(r1) | |
9994a338 PM |
436 | lwz r2,GPR2(r1) |
437 | lwz r1,GPR1(r1) | |
cd99ddbe | 438 | #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) |
75b82472 CL |
439 | mtspr SPRN_NRI, r0 |
440 | #endif | |
9994a338 PM |
441 | mtspr SPRN_SRR0,r7 |
442 | mtspr SPRN_SRR1,r8 | |
443 | SYNC | |
444 | RFI | |
b98ac05d BH |
445 | #ifdef CONFIG_44x |
446 | 2: li r7,0 | |
447 | iccci r0,r0 | |
448 | stw r7,icache_44x_need_flush@l(r4) | |
449 | b 1b | |
450 | #endif /* CONFIG_44x */ | |
9994a338 PM |
451 | |
452 | 66: li r3,-ENOSYS | |
453 | b ret_from_syscall | |
454 | ||
455 | .globl ret_from_fork | |
456 | ret_from_fork: | |
457 | REST_NVGPRS(r1) | |
458 | bl schedule_tail | |
459 | li r3,0 | |
460 | b ret_from_syscall | |
461 | ||
58254e10 AV |
462 | .globl ret_from_kernel_thread |
463 | ret_from_kernel_thread: | |
464 | REST_NVGPRS(r1) | |
465 | bl schedule_tail | |
466 | mtlr r14 | |
467 | mr r3,r15 | |
468 | PPC440EP_ERR42 | |
469 | blrl | |
470 | li r3,0 | |
be6abfa7 | 471 | b ret_from_syscall |
9994a338 PM |
472 | |
473 | /* Traced system call support */ | |
474 | syscall_dotrace: | |
475 | SAVE_NVGPRS(r1) | |
476 | li r0,0xc00 | |
d73e0c99 | 477 | stw r0,_TRAP(r1) |
9994a338 PM |
478 | addi r3,r1,STACK_FRAME_OVERHEAD |
479 | bl do_syscall_trace_enter | |
4f72c427 RM |
480 | /* |
481 | * Restore argument registers possibly just changed. | |
482 | * We use the return value of do_syscall_trace_enter | |
483 | * for call number to look up in the table (r0). | |
484 | */ | |
485 | mr r0,r3 | |
9994a338 PM |
486 | lwz r3,GPR3(r1) |
487 | lwz r4,GPR4(r1) | |
488 | lwz r5,GPR5(r1) | |
489 | lwz r6,GPR6(r1) | |
490 | lwz r7,GPR7(r1) | |
491 | lwz r8,GPR8(r1) | |
492 | REST_NVGPRS(r1) | |
d3837414 ME |
493 | |
494 | cmplwi r0,NR_syscalls | |
495 | /* Return code is already in r3 thanks to do_syscall_trace_enter() */ | |
496 | bge- ret_from_syscall | |
9994a338 PM |
497 | b syscall_dotrace_cont |
498 | ||
499 | syscall_exit_work: | |
401d1f02 | 500 | andi. r0,r9,_TIF_RESTOREALL |
1bd79336 PM |
501 | beq+ 0f |
502 | REST_NVGPRS(r1) | |
503 | b 2f | |
504 | 0: cmplw 0,r3,r8 | |
401d1f02 DW |
505 | blt+ 1f |
506 | andi. r0,r9,_TIF_NOERROR | |
507 | bne- 1f | |
508 | lwz r11,_CCR(r1) /* Load CR */ | |
509 | neg r3,r3 | |
510 | oris r11,r11,0x1000 /* Set SO bit in CR */ | |
511 | stw r11,_CCR(r1) | |
512 | ||
513 | 1: stw r6,RESULT(r1) /* Save result */ | |
9994a338 | 514 | stw r3,GPR3(r1) /* Update return value */ |
401d1f02 DW |
515 | 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK) |
516 | beq 4f | |
517 | ||
1bd79336 | 518 | /* Clear per-syscall TIF flags if any are set. */ |
401d1f02 DW |
519 | |
520 | li r11,_TIF_PERSYSCALL_MASK | |
f7354cca | 521 | addi r12,r2,TI_FLAGS |
401d1f02 DW |
522 | 3: lwarx r8,0,r12 |
523 | andc r8,r8,r11 | |
524 | #ifdef CONFIG_IBM405_ERR77 | |
525 | dcbt 0,r12 | |
526 | #endif | |
527 | stwcx. r8,0,r12 | |
528 | bne- 3b | |
401d1f02 DW |
529 | |
530 | 4: /* Anything which requires enabling interrupts? */ | |
10ea8343 | 531 | andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP) |
1bd79336 PM |
532 | beq ret_from_except |
533 | ||
5d38902c BH |
534 | /* Re-enable interrupts. There is no need to trace that with |
535 | * lockdep as we are supposed to have IRQs on at this point | |
536 | */ | |
1bd79336 PM |
537 | ori r10,r10,MSR_EE |
538 | SYNC | |
539 | MTMSRD(r10) | |
401d1f02 DW |
540 | |
541 | /* Save NVGPRS if they're not saved already */ | |
d73e0c99 | 542 | lwz r4,_TRAP(r1) |
9994a338 | 543 | andi. r4,r4,1 |
401d1f02 | 544 | beq 5f |
9994a338 PM |
545 | SAVE_NVGPRS(r1) |
546 | li r4,0xc00 | |
d73e0c99 | 547 | stw r4,_TRAP(r1) |
1bd79336 | 548 | 5: |
9994a338 PM |
549 | addi r3,r1,STACK_FRAME_OVERHEAD |
550 | bl do_syscall_trace_leave | |
1bd79336 | 551 | b ret_from_except_full |
9994a338 | 552 | |
9994a338 | 553 | /* |
401d1f02 DW |
554 | * The fork/clone functions need to copy the full register set into |
555 | * the child process. Therefore we need to save all the nonvolatile | |
556 | * registers (r13 - r31) before calling the C code. | |
9994a338 | 557 | */ |
9994a338 PM |
558 | .globl ppc_fork |
559 | ppc_fork: | |
560 | SAVE_NVGPRS(r1) | |
d73e0c99 | 561 | lwz r0,_TRAP(r1) |
9994a338 | 562 | rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */ |
d73e0c99 | 563 | stw r0,_TRAP(r1) /* register set saved */ |
9994a338 PM |
564 | b sys_fork |
565 | ||
566 | .globl ppc_vfork | |
567 | ppc_vfork: | |
568 | SAVE_NVGPRS(r1) | |
d73e0c99 | 569 | lwz r0,_TRAP(r1) |
9994a338 | 570 | rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */ |
d73e0c99 | 571 | stw r0,_TRAP(r1) /* register set saved */ |
9994a338 PM |
572 | b sys_vfork |
573 | ||
574 | .globl ppc_clone | |
575 | ppc_clone: | |
576 | SAVE_NVGPRS(r1) | |
d73e0c99 | 577 | lwz r0,_TRAP(r1) |
9994a338 | 578 | rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */ |
d73e0c99 | 579 | stw r0,_TRAP(r1) /* register set saved */ |
9994a338 PM |
580 | b sys_clone |
581 | ||
1bd79336 PM |
582 | .globl ppc_swapcontext |
583 | ppc_swapcontext: | |
584 | SAVE_NVGPRS(r1) | |
585 | lwz r0,_TRAP(r1) | |
586 | rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */ | |
587 | stw r0,_TRAP(r1) /* register set saved */ | |
588 | b sys_swapcontext | |
589 | ||
9994a338 PM |
590 | /* |
591 | * Top-level page fault handling. | |
592 | * This is in assembler because if do_page_fault tells us that | |
593 | * it is a bad kernel page fault, we want to save the non-volatile | |
594 | * registers before calling bad_page_fault. | |
595 | */ | |
596 | .globl handle_page_fault | |
597 | handle_page_fault: | |
598 | stw r4,_DAR(r1) | |
599 | addi r3,r1,STACK_FRAME_OVERHEAD | |
d7cceda9 | 600 | #ifdef CONFIG_PPC_BOOK3S_32 |
64d0a506 | 601 | andis. r0,r5,DSISR_DABRMATCH@h |
d300627c | 602 | bne- handle_dabr_fault |
d300627c | 603 | #endif |
64d0a506 | 604 | bl do_page_fault |
9994a338 PM |
605 | cmpwi r3,0 |
606 | beq+ ret_from_except | |
607 | SAVE_NVGPRS(r1) | |
d73e0c99 | 608 | lwz r0,_TRAP(r1) |
9994a338 | 609 | clrrwi r0,r0,1 |
d73e0c99 | 610 | stw r0,_TRAP(r1) |
9994a338 PM |
611 | mr r5,r3 |
612 | addi r3,r1,STACK_FRAME_OVERHEAD | |
613 | lwz r4,_DAR(r1) | |
614 | bl bad_page_fault | |
615 | b ret_from_except_full | |
616 | ||
d7cceda9 | 617 | #ifdef CONFIG_PPC_BOOK3S_32 |
d300627c BH |
618 | /* We have a data breakpoint exception - handle it */ |
619 | handle_dabr_fault: | |
620 | SAVE_NVGPRS(r1) | |
621 | lwz r0,_TRAP(r1) | |
622 | clrrwi r0,r0,1 | |
623 | stw r0,_TRAP(r1) | |
624 | bl do_break | |
625 | b ret_from_except_full | |
626 | #endif | |
627 | ||
9994a338 PM |
628 | /* |
629 | * This routine switches between two different tasks. The process | |
630 | * state of one is saved on its kernel stack. Then the state | |
631 | * of the other is restored from its kernel stack. The memory | |
632 | * management hardware is updated to the second process's state. | |
633 | * Finally, we can return to the second process. | |
634 | * On entry, r3 points to the THREAD for the current task, r4 | |
635 | * points to the THREAD for the new task. | |
636 | * | |
637 | * This routine is always called with interrupts disabled. | |
638 | * | |
639 | * Note: there are two ways to get to the "going out" portion | |
640 | * of this code; either by coming in via the entry (_switch) | |
641 | * or via "fork" which must set up an environment equivalent | |
642 | * to the "_switch" path. If you change this , you'll have to | |
643 | * change the fork code also. | |
644 | * | |
645 | * The code which creates the new task context is in 'copy_thread' | |
646 | * in arch/ppc/kernel/process.c | |
647 | */ | |
648 | _GLOBAL(_switch) | |
649 | stwu r1,-INT_FRAME_SIZE(r1) | |
650 | mflr r0 | |
651 | stw r0,INT_FRAME_SIZE+4(r1) | |
652 | /* r3-r12 are caller saved -- Cort */ | |
653 | SAVE_NVGPRS(r1) | |
654 | stw r0,_NIP(r1) /* Return to switch caller */ | |
655 | mfmsr r11 | |
656 | li r0,MSR_FP /* Disable floating-point */ | |
657 | #ifdef CONFIG_ALTIVEC | |
658 | BEGIN_FTR_SECTION | |
659 | oris r0,r0,MSR_VEC@h /* Disable altivec */ | |
660 | mfspr r12,SPRN_VRSAVE /* save vrsave register value */ | |
661 | stw r12,THREAD+THREAD_VRSAVE(r2) | |
662 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
663 | #endif /* CONFIG_ALTIVEC */ | |
664 | #ifdef CONFIG_SPE | |
5e14d21e | 665 | BEGIN_FTR_SECTION |
9994a338 PM |
666 | oris r0,r0,MSR_SPE@h /* Disable SPE */ |
667 | mfspr r12,SPRN_SPEFSCR /* save spefscr register value */ | |
668 | stw r12,THREAD+THREAD_SPEFSCR(r2) | |
5e14d21e | 669 | END_FTR_SECTION_IFSET(CPU_FTR_SPE) |
9994a338 PM |
670 | #endif /* CONFIG_SPE */ |
671 | and. r0,r0,r11 /* FP or altivec or SPE enabled? */ | |
672 | beq+ 1f | |
673 | andc r11,r11,r0 | |
674 | MTMSRD(r11) | |
675 | isync | |
676 | 1: stw r11,_MSR(r1) | |
677 | mfcr r10 | |
678 | stw r10,_CCR(r1) | |
679 | stw r1,KSP(r3) /* Set old stack pointer */ | |
680 | ||
e2fb9f54 | 681 | kuap_check r2, r4 |
9994a338 PM |
682 | #ifdef CONFIG_SMP |
683 | /* We need a sync somewhere here to make sure that if the | |
684 | * previous task gets rescheduled on another CPU, it sees all | |
685 | * stores it has performed on this one. | |
686 | */ | |
687 | sync | |
688 | #endif /* CONFIG_SMP */ | |
689 | ||
690 | tophys(r0,r4) | |
ee43eb78 | 691 | mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */ |
9994a338 PM |
692 | lwz r1,KSP(r4) /* Load new stack pointer */ |
693 | ||
694 | /* save the old current 'last' for return value */ | |
695 | mr r3,r2 | |
696 | addi r2,r4,-THREAD /* Update current */ | |
697 | ||
698 | #ifdef CONFIG_ALTIVEC | |
699 | BEGIN_FTR_SECTION | |
700 | lwz r0,THREAD+THREAD_VRSAVE(r2) | |
701 | mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */ | |
702 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
703 | #endif /* CONFIG_ALTIVEC */ | |
704 | #ifdef CONFIG_SPE | |
5e14d21e | 705 | BEGIN_FTR_SECTION |
9994a338 PM |
706 | lwz r0,THREAD+THREAD_SPEFSCR(r2) |
707 | mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */ | |
5e14d21e | 708 | END_FTR_SECTION_IFSET(CPU_FTR_SPE) |
9994a338 | 709 | #endif /* CONFIG_SPE */ |
f2574030 | 710 | |
9994a338 PM |
711 | lwz r0,_CCR(r1) |
712 | mtcrf 0xFF,r0 | |
713 | /* r3-r12 are destroyed -- Cort */ | |
714 | REST_NVGPRS(r1) | |
715 | ||
716 | lwz r4,_NIP(r1) /* Return to _switch caller in new task */ | |
717 | mtlr r4 | |
718 | addi r1,r1,INT_FRAME_SIZE | |
719 | blr | |
720 | ||
721 | .globl fast_exception_return | |
722 | fast_exception_return: | |
723 | #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) | |
724 | andi. r10,r9,MSR_RI /* check for recoverable interrupt */ | |
725 | beq 1f /* if not, we've got problems */ | |
726 | #endif | |
727 | ||
728 | 2: REST_4GPRS(3, r11) | |
729 | lwz r10,_CCR(r11) | |
730 | REST_GPR(1, r11) | |
731 | mtcr r10 | |
732 | lwz r10,_LINK(r11) | |
733 | mtlr r10 | |
9580b71b CL |
734 | /* Clear the exception_marker on the stack to avoid confusing stacktrace */ |
735 | li r10, 0 | |
736 | stw r10, 8(r11) | |
9994a338 | 737 | REST_GPR(10, r11) |
cd99ddbe | 738 | #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) |
75b82472 CL |
739 | mtspr SPRN_NRI, r0 |
740 | #endif | |
9994a338 PM |
741 | mtspr SPRN_SRR1,r9 |
742 | mtspr SPRN_SRR0,r12 | |
743 | REST_GPR(9, r11) | |
744 | REST_GPR(12, r11) | |
745 | lwz r11,GPR11(r11) | |
746 | SYNC | |
747 | RFI | |
748 | ||
749 | #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) | |
750 | /* check if the exception happened in a restartable section */ | |
751 | 1: lis r3,exc_exit_restart_end@ha | |
752 | addi r3,r3,exc_exit_restart_end@l | |
753 | cmplw r12,r3 | |
754 | bge 3f | |
755 | lis r4,exc_exit_restart@ha | |
756 | addi r4,r4,exc_exit_restart@l | |
757 | cmplw r12,r4 | |
758 | blt 3f | |
759 | lis r3,fee_restarts@ha | |
760 | tophys(r3,r3) | |
761 | lwz r5,fee_restarts@l(r3) | |
762 | addi r5,r5,1 | |
763 | stw r5,fee_restarts@l(r3) | |
764 | mr r12,r4 /* restart at exc_exit_restart */ | |
765 | b 2b | |
766 | ||
991eb43a KG |
767 | .section .bss |
768 | .align 2 | |
769 | fee_restarts: | |
770 | .space 4 | |
771 | .previous | |
9994a338 PM |
772 | |
773 | /* aargh, a nonrecoverable interrupt, panic */ | |
774 | /* aargh, we don't know which trap this is */ | |
775 | /* but the 601 doesn't implement the RI bit, so assume it's OK */ | |
776 | 3: | |
777 | BEGIN_FTR_SECTION | |
778 | b 2b | |
779 | END_FTR_SECTION_IFSET(CPU_FTR_601) | |
780 | li r10,-1 | |
d73e0c99 | 781 | stw r10,_TRAP(r11) |
9994a338 PM |
782 | addi r3,r1,STACK_FRAME_OVERHEAD |
783 | lis r10,MSR_KERNEL@h | |
784 | ori r10,r10,MSR_KERNEL@l | |
785 | bl transfer_to_handler_full | |
51423a9c | 786 | .long unrecoverable_exception |
9994a338 PM |
787 | .long ret_from_except |
788 | #endif | |
789 | ||
9994a338 PM |
790 | .globl ret_from_except_full |
791 | ret_from_except_full: | |
792 | REST_NVGPRS(r1) | |
793 | /* fall through */ | |
794 | ||
795 | .globl ret_from_except | |
796 | ret_from_except: | |
797 | /* Hard-disable interrupts so that current_thread_info()->flags | |
798 | * can't change between when we test it and when we return | |
799 | * from the interrupt. */ | |
5d38902c | 800 | /* Note: We don't bother telling lockdep about it */ |
9994a338 PM |
801 | LOAD_MSR_KERNEL(r10,MSR_KERNEL) |
802 | SYNC /* Some chip revs have problems here... */ | |
803 | MTMSRD(r10) /* disable interrupts */ | |
804 | ||
805 | lwz r3,_MSR(r1) /* Returning to user mode? */ | |
806 | andi. r0,r3,MSR_PR | |
807 | beq resume_kernel | |
808 | ||
809 | user_exc_return: /* r10 contains MSR_KERNEL here */ | |
810 | /* Check current_thread_info()->flags */ | |
f7354cca | 811 | lwz r9,TI_FLAGS(r2) |
7a10174e | 812 | andi. r0,r9,_TIF_USER_WORK_MASK |
9994a338 PM |
813 | bne do_work |
814 | ||
815 | restore_user: | |
816 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) | |
4eaddb4d KG |
817 | /* Check whether this process has its own DBCR0 value. The internal |
818 | debug mode bit tells us that dbcr0 should be loaded. */ | |
9994a338 | 819 | lwz r0,THREAD+THREAD_DBCR0(r2) |
2325f0a0 | 820 | andis. r10,r0,DBCR0_IDM@h |
9994a338 PM |
821 | bnel- load_dbcr0 |
822 | #endif | |
f7354cca | 823 | ACCOUNT_CPU_USER_EXIT(r2, r10, r11) |
9994a338 | 824 | |
9994a338 PM |
825 | b restore |
826 | ||
827 | /* N.B. the only way to get here is from the beq following ret_from_except. */ | |
828 | resume_kernel: | |
a9c4e541 | 829 | /* check current_thread_info, _TIF_EMULATE_STACK_STORE */ |
f7354cca | 830 | lwz r8,TI_FLAGS(r2) |
f7b33677 | 831 | andis. r0,r8,_TIF_EMULATE_STACK_STORE@h |
a9c4e541 TC |
832 | beq+ 1f |
833 | ||
834 | addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */ | |
835 | ||
836 | lwz r3,GPR1(r1) | |
837 | subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */ | |
838 | mr r4,r1 /* src: current exception frame */ | |
839 | mr r1,r3 /* Reroute the trampoline frame to r1 */ | |
840 | ||
841 | /* Copy from the original to the trampoline. */ | |
842 | li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */ | |
843 | li r6,0 /* start offset: 0 */ | |
844 | mtctr r5 | |
845 | 2: lwzx r0,r6,r4 | |
846 | stwx r0,r6,r3 | |
847 | addi r6,r6,4 | |
848 | bdnz 2b | |
849 | ||
850 | /* Do real store operation to complete stwu */ | |
851 | lwz r5,GPR1(r1) | |
852 | stw r8,0(r5) | |
853 | ||
854 | /* Clear _TIF_EMULATE_STACK_STORE flag */ | |
855 | lis r11,_TIF_EMULATE_STACK_STORE@h | |
f7354cca | 856 | addi r5,r2,TI_FLAGS |
a9c4e541 TC |
857 | 0: lwarx r8,0,r5 |
858 | andc r8,r8,r11 | |
859 | #ifdef CONFIG_IBM405_ERR77 | |
860 | dcbt 0,r5 | |
861 | #endif | |
862 | stwcx. r8,0,r5 | |
863 | bne- 0b | |
864 | 1: | |
865 | ||
866 | #ifdef CONFIG_PREEMPT | |
867 | /* check current_thread_info->preempt_count */ | |
f7354cca | 868 | lwz r0,TI_PREEMPT(r2) |
9994a338 | 869 | cmpwi 0,r0,0 /* if non-zero, just restore regs and return */ |
e2fb9f54 | 870 | bne restore_kuap |
a9c4e541 | 871 | andi. r8,r8,_TIF_NEED_RESCHED |
e2fb9f54 | 872 | beq+ restore_kuap |
a9c4e541 | 873 | lwz r3,_MSR(r1) |
9994a338 | 874 | andi. r0,r3,MSR_EE /* interrupts off? */ |
e2fb9f54 | 875 | beq restore_kuap /* don't schedule if so */ |
5d38902c BH |
876 | #ifdef CONFIG_TRACE_IRQFLAGS |
877 | /* Lockdep thinks irqs are enabled, we need to call | |
878 | * preempt_schedule_irq with IRQs off, so we inform lockdep | |
879 | * now that we -did- turn them off already | |
880 | */ | |
881 | bl trace_hardirqs_off | |
882 | #endif | |
9994a338 | 883 | 1: bl preempt_schedule_irq |
f7354cca | 884 | lwz r3,TI_FLAGS(r2) |
9994a338 PM |
885 | andi. r0,r3,_TIF_NEED_RESCHED |
886 | bne- 1b | |
5d38902c BH |
887 | #ifdef CONFIG_TRACE_IRQFLAGS |
888 | /* And now, to properly rebalance the above, we tell lockdep they | |
889 | * are being turned back on, which will happen when we return | |
890 | */ | |
891 | bl trace_hardirqs_on | |
892 | #endif | |
9994a338 | 893 | #endif /* CONFIG_PREEMPT */ |
e2fb9f54 CL |
894 | restore_kuap: |
895 | kuap_restore r1, r2, r9, r10, r0 | |
9994a338 PM |
896 | |
897 | /* interrupts are hard-disabled at this point */ | |
898 | restore: | |
b98ac05d | 899 | #ifdef CONFIG_44x |
e7f75ad0 DK |
900 | BEGIN_MMU_FTR_SECTION |
901 | b 1f | |
902 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) | |
b98ac05d BH |
903 | lis r4,icache_44x_need_flush@ha |
904 | lwz r5,icache_44x_need_flush@l(r4) | |
905 | cmplwi cr0,r5,0 | |
906 | beq+ 1f | |
907 | li r6,0 | |
908 | iccci r0,r0 | |
909 | stw r6,icache_44x_need_flush@l(r4) | |
910 | 1: | |
911 | #endif /* CONFIG_44x */ | |
5d38902c BH |
912 | |
913 | lwz r9,_MSR(r1) | |
914 | #ifdef CONFIG_TRACE_IRQFLAGS | |
915 | /* Lockdep doesn't know about the fact that IRQs are temporarily turned | |
916 | * off in this assembly code while peeking at TI_FLAGS() and such. However | |
917 | * we need to inform it if the exception turned interrupts off, and we | |
918 | * are about to trun them back on. | |
919 | * | |
920 | * The problem here sadly is that we don't know whether the exceptions was | |
921 | * one that turned interrupts off or not. So we always tell lockdep about | |
922 | * turning them on here when we go back to wherever we came from with EE | |
923 | * on, even if that may meen some redudant calls being tracked. Maybe later | |
924 | * we could encode what the exception did somewhere or test the exception | |
925 | * type in the pt_regs but that sounds overkill | |
926 | */ | |
927 | andi. r10,r9,MSR_EE | |
928 | beq 1f | |
06ca2188 SR |
929 | /* |
930 | * Since the ftrace irqsoff latency trace checks CALLER_ADDR1, | |
931 | * which is the stack frame here, we need to force a stack frame | |
932 | * in case we came from user space. | |
933 | */ | |
934 | stwu r1,-32(r1) | |
935 | mflr r0 | |
936 | stw r0,4(r1) | |
937 | stwu r1,-32(r1) | |
5d38902c | 938 | bl trace_hardirqs_on |
06ca2188 SR |
939 | lwz r1,0(r1) |
940 | lwz r1,0(r1) | |
5d38902c BH |
941 | lwz r9,_MSR(r1) |
942 | 1: | |
943 | #endif /* CONFIG_TRACE_IRQFLAGS */ | |
944 | ||
9994a338 PM |
945 | lwz r0,GPR0(r1) |
946 | lwz r2,GPR2(r1) | |
947 | REST_4GPRS(3, r1) | |
948 | REST_2GPRS(7, r1) | |
949 | ||
950 | lwz r10,_XER(r1) | |
951 | lwz r11,_CTR(r1) | |
952 | mtspr SPRN_XER,r10 | |
953 | mtctr r11 | |
954 | ||
955 | PPC405_ERR77(0,r1) | |
b64f87c1 BB |
956 | BEGIN_FTR_SECTION |
957 | lwarx r11,0,r1 | |
958 | END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) | |
9994a338 PM |
959 | stwcx. r0,0,r1 /* to clear the reservation */ |
960 | ||
961 | #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) | |
9994a338 PM |
962 | andi. r10,r9,MSR_RI /* check if this exception occurred */ |
963 | beql nonrecoverable /* at a bad place (MSR:RI = 0) */ | |
964 | ||
965 | lwz r10,_CCR(r1) | |
966 | lwz r11,_LINK(r1) | |
967 | mtcrf 0xFF,r10 | |
968 | mtlr r11 | |
969 | ||
9580b71b CL |
970 | /* Clear the exception_marker on the stack to avoid confusing stacktrace */ |
971 | li r10, 0 | |
972 | stw r10, 8(r1) | |
9994a338 PM |
973 | /* |
974 | * Once we put values in SRR0 and SRR1, we are in a state | |
975 | * where exceptions are not recoverable, since taking an | |
976 | * exception will trash SRR0 and SRR1. Therefore we clear the | |
977 | * MSR:RI bit to indicate this. If we do take an exception, | |
978 | * we can't return to the point of the exception but we | |
979 | * can restart the exception exit path at the label | |
980 | * exc_exit_restart below. -- paulus | |
981 | */ | |
982 | LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI) | |
983 | SYNC | |
984 | MTMSRD(r10) /* clear the RI bit */ | |
985 | .globl exc_exit_restart | |
986 | exc_exit_restart: | |
9994a338 | 987 | lwz r12,_NIP(r1) |
9994a338 PM |
988 | mtspr SPRN_SRR0,r12 |
989 | mtspr SPRN_SRR1,r9 | |
990 | REST_4GPRS(9, r1) | |
991 | lwz r1,GPR1(r1) | |
992 | .globl exc_exit_restart_end | |
993 | exc_exit_restart_end: | |
994 | SYNC | |
995 | RFI | |
996 | ||
997 | #else /* !(CONFIG_4xx || CONFIG_BOOKE) */ | |
998 | /* | |
999 | * This is a bit different on 4xx/Book-E because it doesn't have | |
1000 | * the RI bit in the MSR. | |
1001 | * The TLB miss handler checks if we have interrupted | |
1002 | * the exception exit path and restarts it if so | |
1003 | * (well maybe one day it will... :). | |
1004 | */ | |
1005 | lwz r11,_LINK(r1) | |
1006 | mtlr r11 | |
1007 | lwz r10,_CCR(r1) | |
1008 | mtcrf 0xff,r10 | |
9580b71b CL |
1009 | /* Clear the exception_marker on the stack to avoid confusing stacktrace */ |
1010 | li r10, 0 | |
1011 | stw r10, 8(r1) | |
9994a338 PM |
1012 | REST_2GPRS(9, r1) |
1013 | .globl exc_exit_restart | |
1014 | exc_exit_restart: | |
1015 | lwz r11,_NIP(r1) | |
1016 | lwz r12,_MSR(r1) | |
1017 | exc_exit_start: | |
1018 | mtspr SPRN_SRR0,r11 | |
1019 | mtspr SPRN_SRR1,r12 | |
1020 | REST_2GPRS(11, r1) | |
1021 | lwz r1,GPR1(r1) | |
1022 | .globl exc_exit_restart_end | |
1023 | exc_exit_restart_end: | |
1024 | PPC405_ERR77_SYNC | |
1025 | rfi | |
1026 | b . /* prevent prefetch past rfi */ | |
1027 | ||
1028 | /* | |
1029 | * Returning from a critical interrupt in user mode doesn't need | |
1030 | * to be any different from a normal exception. For a critical | |
1031 | * interrupt in the kernel, we just return (without checking for | |
1032 | * preemption) since the interrupt may have happened at some crucial | |
1033 | * place (e.g. inside the TLB miss handler), and because we will be | |
1034 | * running with r1 pointing into critical_stack, not the current | |
1035 | * process's kernel stack (and therefore current_thread_info() will | |
1036 | * give the wrong answer). | |
1037 | * We have to restore various SPRs that may have been in use at the | |
1038 | * time of the critical interrupt. | |
1039 | * | |
1040 | */ | |
1041 | #ifdef CONFIG_40x | |
1042 | #define PPC_40x_TURN_OFF_MSR_DR \ | |
1043 | /* avoid any possible TLB misses here by turning off MSR.DR, we \ | |
1044 | * assume the instructions here are mapped by a pinned TLB entry */ \ | |
1045 | li r10,MSR_IR; \ | |
1046 | mtmsr r10; \ | |
1047 | isync; \ | |
1048 | tophys(r1, r1); | |
1049 | #else | |
1050 | #define PPC_40x_TURN_OFF_MSR_DR | |
1051 | #endif | |
1052 | ||
1053 | #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \ | |
1054 | REST_NVGPRS(r1); \ | |
1055 | lwz r3,_MSR(r1); \ | |
1056 | andi. r3,r3,MSR_PR; \ | |
1057 | LOAD_MSR_KERNEL(r10,MSR_KERNEL); \ | |
1058 | bne user_exc_return; \ | |
1059 | lwz r0,GPR0(r1); \ | |
1060 | lwz r2,GPR2(r1); \ | |
1061 | REST_4GPRS(3, r1); \ | |
1062 | REST_2GPRS(7, r1); \ | |
1063 | lwz r10,_XER(r1); \ | |
1064 | lwz r11,_CTR(r1); \ | |
1065 | mtspr SPRN_XER,r10; \ | |
1066 | mtctr r11; \ | |
1067 | PPC405_ERR77(0,r1); \ | |
1068 | stwcx. r0,0,r1; /* to clear the reservation */ \ | |
1069 | lwz r11,_LINK(r1); \ | |
1070 | mtlr r11; \ | |
1071 | lwz r10,_CCR(r1); \ | |
1072 | mtcrf 0xff,r10; \ | |
1073 | PPC_40x_TURN_OFF_MSR_DR; \ | |
1074 | lwz r9,_DEAR(r1); \ | |
1075 | lwz r10,_ESR(r1); \ | |
1076 | mtspr SPRN_DEAR,r9; \ | |
1077 | mtspr SPRN_ESR,r10; \ | |
1078 | lwz r11,_NIP(r1); \ | |
1079 | lwz r12,_MSR(r1); \ | |
1080 | mtspr exc_lvl_srr0,r11; \ | |
1081 | mtspr exc_lvl_srr1,r12; \ | |
1082 | lwz r9,GPR9(r1); \ | |
1083 | lwz r12,GPR12(r1); \ | |
1084 | lwz r10,GPR10(r1); \ | |
1085 | lwz r11,GPR11(r1); \ | |
1086 | lwz r1,GPR1(r1); \ | |
1087 | PPC405_ERR77_SYNC; \ | |
1088 | exc_lvl_rfi; \ | |
1089 | b .; /* prevent prefetch past exc_lvl_rfi */ | |
1090 | ||
fca622c5 KG |
1091 | #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \ |
1092 | lwz r9,_##exc_lvl_srr0(r1); \ | |
1093 | lwz r10,_##exc_lvl_srr1(r1); \ | |
1094 | mtspr SPRN_##exc_lvl_srr0,r9; \ | |
1095 | mtspr SPRN_##exc_lvl_srr1,r10; | |
1096 | ||
70fe3af8 | 1097 | #if defined(CONFIG_PPC_BOOK3E_MMU) |
fca622c5 KG |
1098 | #ifdef CONFIG_PHYS_64BIT |
1099 | #define RESTORE_MAS7 \ | |
1100 | lwz r11,MAS7(r1); \ | |
1101 | mtspr SPRN_MAS7,r11; | |
1102 | #else | |
1103 | #define RESTORE_MAS7 | |
1104 | #endif /* CONFIG_PHYS_64BIT */ | |
1105 | #define RESTORE_MMU_REGS \ | |
1106 | lwz r9,MAS0(r1); \ | |
1107 | lwz r10,MAS1(r1); \ | |
1108 | lwz r11,MAS2(r1); \ | |
1109 | mtspr SPRN_MAS0,r9; \ | |
1110 | lwz r9,MAS3(r1); \ | |
1111 | mtspr SPRN_MAS1,r10; \ | |
1112 | lwz r10,MAS6(r1); \ | |
1113 | mtspr SPRN_MAS2,r11; \ | |
1114 | mtspr SPRN_MAS3,r9; \ | |
1115 | mtspr SPRN_MAS6,r10; \ | |
1116 | RESTORE_MAS7; | |
1117 | #elif defined(CONFIG_44x) | |
1118 | #define RESTORE_MMU_REGS \ | |
1119 | lwz r9,MMUCR(r1); \ | |
1120 | mtspr SPRN_MMUCR,r9; | |
1121 | #else | |
1122 | #define RESTORE_MMU_REGS | |
1123 | #endif | |
1124 | ||
1125 | #ifdef CONFIG_40x | |
9994a338 PM |
1126 | .globl ret_from_crit_exc |
1127 | ret_from_crit_exc: | |
ee43eb78 | 1128 | mfspr r9,SPRN_SPRG_THREAD |
fca622c5 KG |
1129 | lis r10,saved_ksp_limit@ha; |
1130 | lwz r10,saved_ksp_limit@l(r10); | |
1131 | tovirt(r9,r9); | |
1132 | stw r10,KSP_LIMIT(r9) | |
1133 | lis r9,crit_srr0@ha; | |
1134 | lwz r9,crit_srr0@l(r9); | |
1135 | lis r10,crit_srr1@ha; | |
1136 | lwz r10,crit_srr1@l(r10); | |
1137 | mtspr SPRN_SRR0,r9; | |
1138 | mtspr SPRN_SRR1,r10; | |
16c57b36 | 1139 | RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI) |
fca622c5 | 1140 | #endif /* CONFIG_40x */ |
9994a338 PM |
1141 | |
1142 | #ifdef CONFIG_BOOKE | |
fca622c5 KG |
1143 | .globl ret_from_crit_exc |
1144 | ret_from_crit_exc: | |
ee43eb78 | 1145 | mfspr r9,SPRN_SPRG_THREAD |
fca622c5 KG |
1146 | lwz r10,SAVED_KSP_LIMIT(r1) |
1147 | stw r10,KSP_LIMIT(r9) | |
1148 | RESTORE_xSRR(SRR0,SRR1); | |
1149 | RESTORE_MMU_REGS; | |
16c57b36 | 1150 | RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI) |
fca622c5 | 1151 | |
9994a338 PM |
1152 | .globl ret_from_debug_exc |
1153 | ret_from_debug_exc: | |
ee43eb78 | 1154 | mfspr r9,SPRN_SPRG_THREAD |
fca622c5 KG |
1155 | lwz r10,SAVED_KSP_LIMIT(r1) |
1156 | stw r10,KSP_LIMIT(r9) | |
fca622c5 KG |
1157 | RESTORE_xSRR(SRR0,SRR1); |
1158 | RESTORE_xSRR(CSRR0,CSRR1); | |
1159 | RESTORE_MMU_REGS; | |
16c57b36 | 1160 | RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI) |
9994a338 PM |
1161 | |
1162 | .globl ret_from_mcheck_exc | |
1163 | ret_from_mcheck_exc: | |
ee43eb78 | 1164 | mfspr r9,SPRN_SPRG_THREAD |
fca622c5 KG |
1165 | lwz r10,SAVED_KSP_LIMIT(r1) |
1166 | stw r10,KSP_LIMIT(r9) | |
1167 | RESTORE_xSRR(SRR0,SRR1); | |
1168 | RESTORE_xSRR(CSRR0,CSRR1); | |
1169 | RESTORE_xSRR(DSRR0,DSRR1); | |
1170 | RESTORE_MMU_REGS; | |
16c57b36 | 1171 | RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI) |
9994a338 PM |
1172 | #endif /* CONFIG_BOOKE */ |
1173 | ||
1174 | /* | |
1175 | * Load the DBCR0 value for a task that is being ptraced, | |
1176 | * having first saved away the global DBCR0. Note that r0 | |
1177 | * has the dbcr0 value to set upon entry to this. | |
1178 | */ | |
1179 | load_dbcr0: | |
1180 | mfmsr r10 /* first disable debug exceptions */ | |
1181 | rlwinm r10,r10,0,~MSR_DE | |
1182 | mtmsr r10 | |
1183 | isync | |
1184 | mfspr r10,SPRN_DBCR0 | |
1185 | lis r11,global_dbcr0@ha | |
1186 | addi r11,r11,global_dbcr0@l | |
4eaddb4d | 1187 | #ifdef CONFIG_SMP |
f7354cca | 1188 | lwz r9,TASK_CPU(r2) |
4eaddb4d KG |
1189 | slwi r9,r9,3 |
1190 | add r11,r11,r9 | |
1191 | #endif | |
9994a338 PM |
1192 | stw r10,0(r11) |
1193 | mtspr SPRN_DBCR0,r0 | |
1194 | lwz r10,4(r11) | |
1195 | addi r10,r10,1 | |
1196 | stw r10,4(r11) | |
1197 | li r11,-1 | |
1198 | mtspr SPRN_DBSR,r11 /* clear all pending debug events */ | |
1199 | blr | |
1200 | ||
991eb43a KG |
1201 | .section .bss |
1202 | .align 4 | |
1203 | global_dbcr0: | |
4eaddb4d | 1204 | .space 8*NR_CPUS |
991eb43a | 1205 | .previous |
9994a338 PM |
1206 | #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */ |
1207 | ||
1208 | do_work: /* r10 contains MSR_KERNEL here */ | |
1209 | andi. r0,r9,_TIF_NEED_RESCHED | |
1210 | beq do_user_signal | |
1211 | ||
1212 | do_resched: /* r10 contains MSR_KERNEL here */ | |
5d38902c BH |
1213 | /* Note: We don't need to inform lockdep that we are enabling |
1214 | * interrupts here. As far as it knows, they are already enabled | |
1215 | */ | |
9994a338 PM |
1216 | ori r10,r10,MSR_EE |
1217 | SYNC | |
1218 | MTMSRD(r10) /* hard-enable interrupts */ | |
1219 | bl schedule | |
1220 | recheck: | |
5d38902c BH |
1221 | /* Note: And we don't tell it we are disabling them again |
1222 | * neither. Those disable/enable cycles used to peek at | |
1223 | * TI_FLAGS aren't advertised. | |
1224 | */ | |
9994a338 PM |
1225 | LOAD_MSR_KERNEL(r10,MSR_KERNEL) |
1226 | SYNC | |
1227 | MTMSRD(r10) /* disable interrupts */ | |
f7354cca | 1228 | lwz r9,TI_FLAGS(r2) |
9994a338 PM |
1229 | andi. r0,r9,_TIF_NEED_RESCHED |
1230 | bne- do_resched | |
7a10174e | 1231 | andi. r0,r9,_TIF_USER_WORK_MASK |
9994a338 PM |
1232 | beq restore_user |
1233 | do_user_signal: /* r10 contains MSR_KERNEL here */ | |
1234 | ori r10,r10,MSR_EE | |
1235 | SYNC | |
1236 | MTMSRD(r10) /* hard-enable interrupts */ | |
1237 | /* save r13-r31 in the exception frame, if not already done */ | |
d73e0c99 | 1238 | lwz r3,_TRAP(r1) |
9994a338 PM |
1239 | andi. r0,r3,1 |
1240 | beq 2f | |
1241 | SAVE_NVGPRS(r1) | |
1242 | rlwinm r3,r3,0,0,30 | |
d73e0c99 | 1243 | stw r3,_TRAP(r1) |
7d6d637d RM |
1244 | 2: addi r3,r1,STACK_FRAME_OVERHEAD |
1245 | mr r4,r9 | |
18b246fa | 1246 | bl do_notify_resume |
9994a338 PM |
1247 | REST_NVGPRS(r1) |
1248 | b recheck | |
1249 | ||
1250 | /* | |
1251 | * We come here when we are at the end of handling an exception | |
1252 | * that occurred at a place where taking an exception will lose | |
1253 | * state information, such as the contents of SRR0 and SRR1. | |
1254 | */ | |
1255 | nonrecoverable: | |
1256 | lis r10,exc_exit_restart_end@ha | |
1257 | addi r10,r10,exc_exit_restart_end@l | |
1258 | cmplw r12,r10 | |
1259 | bge 3f | |
1260 | lis r11,exc_exit_restart@ha | |
1261 | addi r11,r11,exc_exit_restart@l | |
1262 | cmplw r12,r11 | |
1263 | blt 3f | |
1264 | lis r10,ee_restarts@ha | |
1265 | lwz r12,ee_restarts@l(r10) | |
1266 | addi r12,r12,1 | |
1267 | stw r12,ee_restarts@l(r10) | |
1268 | mr r12,r11 /* restart at exc_exit_restart */ | |
1269 | blr | |
1270 | 3: /* OK, we can't recover, kill this process */ | |
1271 | /* but the 601 doesn't implement the RI bit, so assume it's OK */ | |
1272 | BEGIN_FTR_SECTION | |
1273 | blr | |
1274 | END_FTR_SECTION_IFSET(CPU_FTR_601) | |
d73e0c99 | 1275 | lwz r3,_TRAP(r1) |
9994a338 | 1276 | andi. r0,r3,1 |
ed1cd6de | 1277 | beq 5f |
9994a338 PM |
1278 | SAVE_NVGPRS(r1) |
1279 | rlwinm r3,r3,0,0,30 | |
d73e0c99 | 1280 | stw r3,_TRAP(r1) |
ed1cd6de CL |
1281 | 5: mfspr r2,SPRN_SPRG_THREAD |
1282 | addi r2,r2,-THREAD | |
1283 | tovirt(r2,r2) /* set back r2 to current */ | |
9994a338 | 1284 | 4: addi r3,r1,STACK_FRAME_OVERHEAD |
51423a9c | 1285 | bl unrecoverable_exception |
9994a338 PM |
1286 | /* shouldn't return */ |
1287 | b 4b | |
1288 | ||
991eb43a KG |
1289 | .section .bss |
1290 | .align 2 | |
1291 | ee_restarts: | |
1292 | .space 4 | |
1293 | .previous | |
9994a338 PM |
1294 | |
1295 | /* | |
1296 | * PROM code for specific machines follows. Put it | |
1297 | * here so it's easy to add arch-specific sections later. | |
1298 | * -- Cort | |
1299 | */ | |
033ef338 | 1300 | #ifdef CONFIG_PPC_RTAS |
9994a338 PM |
1301 | /* |
1302 | * On CHRP, the Run-Time Abstraction Services (RTAS) have to be | |
1303 | * called with the MMU off. | |
1304 | */ | |
1305 | _GLOBAL(enter_rtas) | |
1306 | stwu r1,-INT_FRAME_SIZE(r1) | |
1307 | mflr r0 | |
1308 | stw r0,INT_FRAME_SIZE+4(r1) | |
e58c3495 | 1309 | LOAD_REG_ADDR(r4, rtas) |
9994a338 PM |
1310 | lis r6,1f@ha /* physical return address for rtas */ |
1311 | addi r6,r6,1f@l | |
1312 | tophys(r6,r6) | |
1313 | tophys(r7,r1) | |
033ef338 PM |
1314 | lwz r8,RTASENTRY(r4) |
1315 | lwz r4,RTASBASE(r4) | |
9994a338 PM |
1316 | mfmsr r9 |
1317 | stw r9,8(r1) | |
1318 | LOAD_MSR_KERNEL(r0,MSR_KERNEL) | |
1319 | SYNC /* disable interrupts so SRR0/1 */ | |
1320 | MTMSRD(r0) /* don't get trashed */ | |
1321 | li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR) | |
1322 | mtlr r6 | |
0df977ea | 1323 | stw r7, THREAD + RTAS_SP(r2) |
9994a338 PM |
1324 | mtspr SPRN_SRR0,r8 |
1325 | mtspr SPRN_SRR1,r9 | |
1326 | RFI | |
1327 | 1: tophys(r9,r1) | |
1328 | lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */ | |
1329 | lwz r9,8(r9) /* original msr value */ | |
9994a338 PM |
1330 | addi r1,r1,INT_FRAME_SIZE |
1331 | li r0,0 | |
0df977ea CL |
1332 | tophys(r7, r2) |
1333 | stw r0, THREAD + RTAS_SP(r7) | |
9994a338 PM |
1334 | mtspr SPRN_SRR0,r8 |
1335 | mtspr SPRN_SRR1,r9 | |
1336 | RFI /* return to caller */ | |
1337 | ||
1338 | .globl machine_check_in_rtas | |
1339 | machine_check_in_rtas: | |
1340 | twi 31,0,0 | |
1341 | /* XXX load up BATs and panic */ | |
1342 | ||
033ef338 | 1343 | #endif /* CONFIG_PPC_RTAS */ |