Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3c8c90ab LV |
2 | * Copyright IBM Corporation 2001, 2005, 2006 |
3 | * Copyright Dave Engebretsen & Todd Inglett 2001 | |
4 | * Copyright Linas Vepstas 2005, 2006 | |
cb3bc9d0 | 5 | * Copyright 2001-2012 IBM Corporation. |
69376502 | 6 | * |
1da177e4 LT |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
69376502 | 11 | * |
1da177e4 LT |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
69376502 | 16 | * |
1da177e4 LT |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
3c8c90ab LV |
20 | * |
21 | * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> | |
1da177e4 LT |
22 | */ |
23 | ||
6dee3fb9 | 24 | #include <linux/delay.h> |
7f52a526 | 25 | #include <linux/debugfs.h> |
cb3bc9d0 | 26 | #include <linux/sched.h> |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/list.h> | |
1da177e4 LT |
29 | #include <linux/pci.h> |
30 | #include <linux/proc_fs.h> | |
31 | #include <linux/rbtree.h> | |
66f9af83 | 32 | #include <linux/reboot.h> |
1da177e4 LT |
33 | #include <linux/seq_file.h> |
34 | #include <linux/spinlock.h> | |
66b15db6 | 35 | #include <linux/export.h> |
acaa6176 SR |
36 | #include <linux/of.h> |
37 | ||
60063497 | 38 | #include <linux/atomic.h> |
1e54b938 | 39 | #include <asm/debug.h> |
1da177e4 | 40 | #include <asm/eeh.h> |
172ca926 | 41 | #include <asm/eeh_event.h> |
1da177e4 | 42 | #include <asm/io.h> |
212d16cd | 43 | #include <asm/iommu.h> |
1da177e4 | 44 | #include <asm/machdep.h> |
172ca926 | 45 | #include <asm/ppc-pci.h> |
1da177e4 | 46 | #include <asm/rtas.h> |
1da177e4 | 47 | |
1da177e4 LT |
48 | |
49 | /** Overview: | |
50 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
51 | * dealing with PCI bus errors that can't be dealt with within the | |
52 | * usual PCI framework, except by check-stopping the CPU. Systems | |
53 | * that are designed for high-availability/reliability cannot afford | |
54 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
55 | * An EEH-capable bridge operates by converting a detected error | |
56 | * into a "slot freeze", taking the PCI adapter off-line, making | |
57 | * the slot behave, from the OS'es point of view, as if the slot | |
58 | * were "empty": all reads return 0xff's and all writes are silently | |
59 | * ignored. EEH slot isolation events can be triggered by parity | |
60 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
61 | * which in turn might be caused by low voltage on the bus, dust, |
62 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
63 | * |
64 | * Note, however, that one of the leading causes of EEH slot | |
65 | * freeze events are buggy device drivers, buggy device microcode, | |
66 | * or buggy device hardware. This is because any attempt by the | |
67 | * device to bus-master data to a memory address that is not | |
68 | * assigned to the device will trigger a slot freeze. (The idea | |
69 | * is to prevent devices-gone-wild from corrupting system memory). | |
70 | * Buggy hardware/drivers will have a miserable time co-existing | |
71 | * with EEH. | |
72 | * | |
73 | * Ideally, a PCI device driver, when suspecting that an isolation | |
25985edc | 74 | * event has occurred (e.g. by reading 0xff's), will then ask EEH |
1da177e4 LT |
75 | * whether this is the case, and then take appropriate steps to |
76 | * reset the PCI slot, the PCI device, and then resume operations. | |
77 | * However, until that day, the checking is done here, with the | |
78 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
79 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
80 | * and sent out for processing. | |
81 | */ | |
82 | ||
5c1344e9 | 83 | /* If a device driver keeps reading an MMIO register in an interrupt |
f36c5227 MM |
84 | * handler after a slot isolation event, it might be broken. |
85 | * This sets the threshold for how many read attempts we allow | |
86 | * before printing an error message. | |
1da177e4 | 87 | */ |
2fd30be8 | 88 | #define EEH_MAX_FAILS 2100000 |
1da177e4 | 89 | |
17213c3b | 90 | /* Time to wait for a PCI slot to report status, in milliseconds */ |
fb48dc22 | 91 | #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000) |
9c547768 | 92 | |
d7bb8862 | 93 | /* |
8a5ad356 GS |
94 | * EEH probe mode support, which is part of the flags, |
95 | * is to support multiple platforms for EEH. Some platforms | |
96 | * like pSeries do PCI emunation based on device tree. | |
97 | * However, other platforms like powernv probe PCI devices | |
98 | * from hardware. The flag is used to distinguish that. | |
99 | * In addition, struct eeh_ops::probe would be invoked for | |
100 | * particular OF node or PCI device so that the corresponding | |
101 | * PE would be created there. | |
d7bb8862 | 102 | */ |
8a5ad356 GS |
103 | int eeh_subsystem_flags; |
104 | EXPORT_SYMBOL(eeh_subsystem_flags); | |
105 | ||
106 | /* Platform dependent EEH operations */ | |
107 | struct eeh_ops *eeh_ops = NULL; | |
d7bb8862 | 108 | |
fd761fd8 | 109 | /* Lock to avoid races due to multiple reports of an error */ |
4907581d | 110 | DEFINE_RAW_SPINLOCK(confirm_error_lock); |
fd761fd8 | 111 | |
212d16cd GS |
112 | /* Lock to protect passed flags */ |
113 | static DEFINE_MUTEX(eeh_dev_mutex); | |
114 | ||
17213c3b LV |
115 | /* Buffer for reporting pci register dumps. Its here in BSS, and |
116 | * not dynamically alloced, so that it ends up in RMO where RTAS | |
117 | * can access it. | |
118 | */ | |
d99bb1db LV |
119 | #define EEH_PCI_REGS_LOG_LEN 4096 |
120 | static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; | |
121 | ||
e575f8db GS |
122 | /* |
123 | * The struct is used to maintain the EEH global statistic | |
124 | * information. Besides, the EEH global statistics will be | |
125 | * exported to user space through procfs | |
126 | */ | |
127 | struct eeh_stats { | |
128 | u64 no_device; /* PCI device not found */ | |
129 | u64 no_dn; /* OF node not found */ | |
130 | u64 no_cfg_addr; /* Config address not found */ | |
131 | u64 ignored_check; /* EEH check skipped */ | |
132 | u64 total_mmio_ffs; /* Total EEH checks */ | |
133 | u64 false_positives; /* Unnecessary EEH checks */ | |
134 | u64 slot_resets; /* PE reset */ | |
135 | }; | |
136 | ||
137 | static struct eeh_stats eeh_stats; | |
1da177e4 | 138 | |
7684b40c LV |
139 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
140 | ||
7f52a526 GS |
141 | static int __init eeh_setup(char *str) |
142 | { | |
143 | if (!strcmp(str, "off")) | |
144 | eeh_subsystem_flags |= EEH_FORCE_DISABLED; | |
145 | ||
146 | return 1; | |
147 | } | |
148 | __setup("eeh=", eeh_setup); | |
149 | ||
d99bb1db | 150 | /** |
cce4b2d2 | 151 | * eeh_gather_pci_data - Copy assorted PCI config space registers to buff |
f631acd3 | 152 | * @edev: device to report data for |
d99bb1db LV |
153 | * @buf: point to buffer in which to log |
154 | * @len: amount of room in buffer | |
155 | * | |
156 | * This routine captures assorted PCI configuration space data, | |
157 | * and puts them into a buffer for RTAS error logging. | |
158 | */ | |
f631acd3 | 159 | static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len) |
d99bb1db | 160 | { |
f631acd3 | 161 | struct device_node *dn = eeh_dev_to_of_node(edev); |
d99bb1db | 162 | u32 cfg; |
fcf9892b | 163 | int cap, i; |
d99bb1db LV |
164 | int n = 0; |
165 | ||
f631acd3 | 166 | n += scnprintf(buf+n, len-n, "%s\n", dn->full_name); |
2d86c385 | 167 | pr_warn("EEH: of node=%s\n", dn->full_name); |
fcf9892b | 168 | |
3780444c | 169 | eeh_ops->read_config(dn, PCI_VENDOR_ID, 4, &cfg); |
fcf9892b | 170 | n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); |
2d86c385 | 171 | pr_warn("EEH: PCI device/vendor: %08x\n", cfg); |
fcf9892b | 172 | |
3780444c | 173 | eeh_ops->read_config(dn, PCI_COMMAND, 4, &cfg); |
d99bb1db | 174 | n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); |
2d86c385 | 175 | pr_warn("EEH: PCI cmd/status register: %08x\n", cfg); |
fcf9892b | 176 | |
0b9369f4 | 177 | /* Gather bridge-specific registers */ |
2a18dfc6 | 178 | if (edev->mode & EEH_DEV_BRIDGE) { |
3780444c | 179 | eeh_ops->read_config(dn, PCI_SEC_STATUS, 2, &cfg); |
0b9369f4 | 180 | n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); |
2d86c385 | 181 | pr_warn("EEH: Bridge secondary status: %04x\n", cfg); |
0b9369f4 | 182 | |
3780444c | 183 | eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &cfg); |
0b9369f4 | 184 | n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); |
2d86c385 | 185 | pr_warn("EEH: Bridge control: %04x\n", cfg); |
0b9369f4 LV |
186 | } |
187 | ||
fcf9892b | 188 | /* Dump out the PCI-X command and status regs */ |
2a18dfc6 | 189 | cap = edev->pcix_cap; |
fcf9892b | 190 | if (cap) { |
3780444c | 191 | eeh_ops->read_config(dn, cap, 4, &cfg); |
fcf9892b | 192 | n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); |
2d86c385 | 193 | pr_warn("EEH: PCI-X cmd: %08x\n", cfg); |
fcf9892b | 194 | |
3780444c | 195 | eeh_ops->read_config(dn, cap+4, 4, &cfg); |
fcf9892b | 196 | n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); |
2d86c385 | 197 | pr_warn("EEH: PCI-X status: %08x\n", cfg); |
fcf9892b LV |
198 | } |
199 | ||
2a18dfc6 GS |
200 | /* If PCI-E capable, dump PCI-E cap 10 */ |
201 | cap = edev->pcie_cap; | |
202 | if (cap) { | |
fcf9892b | 203 | n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); |
2d86c385 | 204 | pr_warn("EEH: PCI-E capabilities and status follow:\n"); |
fcf9892b LV |
205 | |
206 | for (i=0; i<=8; i++) { | |
2a18dfc6 | 207 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); |
fcf9892b | 208 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
2d86c385 | 209 | pr_warn("EEH: PCI-E %02x: %08x\n", i, cfg); |
fcf9892b | 210 | } |
2a18dfc6 | 211 | } |
fcf9892b | 212 | |
2a18dfc6 GS |
213 | /* If AER capable, dump it */ |
214 | cap = edev->aer_cap; | |
215 | if (cap) { | |
216 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); | |
217 | pr_warn("EEH: PCI-E AER capability register set follows:\n"); | |
218 | ||
219 | for (i=0; i<14; i++) { | |
220 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); | |
221 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
222 | pr_warn("EEH: PCI-E AER %02x: %08x\n", i, cfg); | |
fcf9892b LV |
223 | } |
224 | } | |
0b9369f4 | 225 | |
d99bb1db LV |
226 | return n; |
227 | } | |
228 | ||
cb3bc9d0 GS |
229 | /** |
230 | * eeh_slot_error_detail - Generate combined log including driver log and error log | |
ff477966 | 231 | * @pe: EEH PE |
cb3bc9d0 GS |
232 | * @severity: temporary or permanent error log |
233 | * | |
234 | * This routine should be called to generate the combined log, which | |
235 | * is comprised of driver log and error log. The driver log is figured | |
236 | * out from the config space of the corresponding PCI device, while | |
237 | * the error log is fetched through platform dependent function call. | |
238 | */ | |
ff477966 | 239 | void eeh_slot_error_detail(struct eeh_pe *pe, int severity) |
d99bb1db LV |
240 | { |
241 | size_t loglen = 0; | |
9feed42e | 242 | struct eeh_dev *edev, *tmp; |
d99bb1db | 243 | |
c35ae179 GS |
244 | /* |
245 | * When the PHB is fenced or dead, it's pointless to collect | |
246 | * the data from PCI config space because it should return | |
247 | * 0xFF's. For ER, we still retrieve the data from the PCI | |
248 | * config space. | |
78954700 GS |
249 | * |
250 | * For pHyp, we have to enable IO for log retrieval. Otherwise, | |
251 | * 0xFF's is always returned from PCI config space. | |
c35ae179 | 252 | */ |
9e049375 | 253 | if (!(pe->type & EEH_PE_PHB)) { |
78954700 GS |
254 | if (eeh_probe_mode_devtree()) |
255 | eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); | |
c35ae179 GS |
256 | eeh_ops->configure_bridge(pe); |
257 | eeh_pe_restore_bars(pe); | |
258 | ||
259 | pci_regs_buf[0] = 0; | |
9feed42e | 260 | eeh_pe_for_each_dev(pe, edev, tmp) { |
c35ae179 GS |
261 | loglen += eeh_gather_pci_data(edev, pci_regs_buf + loglen, |
262 | EEH_PCI_REGS_LOG_LEN - loglen); | |
263 | } | |
264 | } | |
ff477966 GS |
265 | |
266 | eeh_ops->get_log(pe, severity, pci_regs_buf, loglen); | |
d99bb1db LV |
267 | } |
268 | ||
1da177e4 | 269 | /** |
cb3bc9d0 GS |
270 | * eeh_token_to_phys - Convert EEH address token to phys address |
271 | * @token: I/O token, should be address in the form 0xA.... | |
272 | * | |
273 | * This routine should be called to convert virtual I/O address | |
274 | * to physical one. | |
1da177e4 LT |
275 | */ |
276 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
277 | { | |
278 | pte_t *ptep; | |
279 | unsigned long pa; | |
12bc9f6f | 280 | int hugepage_shift; |
1da177e4 | 281 | |
12bc9f6f AK |
282 | /* |
283 | * We won't find hugepages here, iomem | |
284 | */ | |
285 | ptep = find_linux_pte_or_hugepte(init_mm.pgd, token, &hugepage_shift); | |
1da177e4 LT |
286 | if (!ptep) |
287 | return token; | |
12bc9f6f | 288 | WARN_ON(hugepage_shift); |
1da177e4 LT |
289 | pa = pte_pfn(*ptep) << PAGE_SHIFT; |
290 | ||
291 | return pa | (token & (PAGE_SIZE-1)); | |
292 | } | |
293 | ||
b95cd2cd GS |
294 | /* |
295 | * On PowerNV platform, we might already have fenced PHB there. | |
296 | * For that case, it's meaningless to recover frozen PE. Intead, | |
297 | * We have to handle fenced PHB firstly. | |
298 | */ | |
299 | static int eeh_phb_check_failure(struct eeh_pe *pe) | |
300 | { | |
301 | struct eeh_pe *phb_pe; | |
302 | unsigned long flags; | |
303 | int ret; | |
304 | ||
305 | if (!eeh_probe_mode_dev()) | |
306 | return -EPERM; | |
307 | ||
308 | /* Find the PHB PE */ | |
309 | phb_pe = eeh_phb_pe_get(pe->phb); | |
310 | if (!phb_pe) { | |
311 | pr_warning("%s Can't find PE for PHB#%d\n", | |
312 | __func__, pe->phb->global_number); | |
313 | return -EEXIST; | |
314 | } | |
315 | ||
316 | /* If the PHB has been in problematic state */ | |
317 | eeh_serialize_lock(&flags); | |
9e049375 | 318 | if (phb_pe->state & EEH_PE_ISOLATED) { |
b95cd2cd GS |
319 | ret = 0; |
320 | goto out; | |
321 | } | |
322 | ||
323 | /* Check PHB state */ | |
324 | ret = eeh_ops->get_state(phb_pe, NULL); | |
325 | if ((ret < 0) || | |
326 | (ret == EEH_STATE_NOT_SUPPORT) || | |
327 | (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) == | |
328 | (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) { | |
329 | ret = 0; | |
330 | goto out; | |
331 | } | |
332 | ||
333 | /* Isolate the PHB and send event */ | |
334 | eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED); | |
335 | eeh_serialize_unlock(flags); | |
b95cd2cd | 336 | |
357b2f3d GS |
337 | pr_err("EEH: PHB#%x failure detected, location: %s\n", |
338 | phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe)); | |
56ca4fde | 339 | dump_stack(); |
5293bf97 | 340 | eeh_send_failure_event(phb_pe); |
b95cd2cd GS |
341 | |
342 | return 1; | |
343 | out: | |
344 | eeh_serialize_unlock(flags); | |
345 | return ret; | |
346 | } | |
347 | ||
1da177e4 | 348 | /** |
f8f7d63f GS |
349 | * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze |
350 | * @edev: eeh device | |
1da177e4 LT |
351 | * |
352 | * Check for an EEH failure for the given device node. Call this | |
353 | * routine if the result of a read was all 0xff's and you want to | |
354 | * find out if this is due to an EEH slot freeze. This routine | |
355 | * will query firmware for the EEH status. | |
356 | * | |
357 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 358 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
359 | * |
360 | * It is safe to call this routine in an interrupt context. | |
361 | */ | |
f8f7d63f | 362 | int eeh_dev_check_failure(struct eeh_dev *edev) |
1da177e4 LT |
363 | { |
364 | int ret; | |
1ad7a72c | 365 | int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
1da177e4 | 366 | unsigned long flags; |
f8f7d63f GS |
367 | struct device_node *dn; |
368 | struct pci_dev *dev; | |
357b2f3d | 369 | struct eeh_pe *pe, *parent_pe, *phb_pe; |
fd761fd8 | 370 | int rc = 0; |
f36c5227 | 371 | const char *location; |
1da177e4 | 372 | |
e575f8db | 373 | eeh_stats.total_mmio_ffs++; |
1da177e4 | 374 | |
2ec5a0ad | 375 | if (!eeh_enabled()) |
1da177e4 LT |
376 | return 0; |
377 | ||
f8f7d63f | 378 | if (!edev) { |
e575f8db | 379 | eeh_stats.no_dn++; |
1da177e4 | 380 | return 0; |
177bc936 | 381 | } |
f8f7d63f GS |
382 | dn = eeh_dev_to_of_node(edev); |
383 | dev = eeh_dev_to_pci_dev(edev); | |
66523d9f | 384 | pe = edev->pe; |
1da177e4 LT |
385 | |
386 | /* Access to IO BARs might get this far and still not want checking. */ | |
66523d9f | 387 | if (!pe) { |
e575f8db | 388 | eeh_stats.ignored_check++; |
66523d9f GS |
389 | pr_debug("EEH: Ignored check for %s %s\n", |
390 | eeh_pci_name(dev), dn->full_name); | |
1da177e4 LT |
391 | return 0; |
392 | } | |
393 | ||
66523d9f | 394 | if (!pe->addr && !pe->config_addr) { |
e575f8db | 395 | eeh_stats.no_cfg_addr++; |
1da177e4 LT |
396 | return 0; |
397 | } | |
398 | ||
b95cd2cd GS |
399 | /* |
400 | * On PowerNV platform, we might already have fenced PHB | |
401 | * there and we need take care of that firstly. | |
402 | */ | |
403 | ret = eeh_phb_check_failure(pe); | |
404 | if (ret > 0) | |
405 | return ret; | |
406 | ||
05ec424e GS |
407 | /* |
408 | * If the PE isn't owned by us, we shouldn't check the | |
409 | * state. Instead, let the owner handle it if the PE has | |
410 | * been frozen. | |
411 | */ | |
412 | if (eeh_pe_passed(pe)) | |
413 | return 0; | |
414 | ||
fd761fd8 LV |
415 | /* If we already have a pending isolation event for this |
416 | * slot, we know it's bad already, we don't need to check. | |
417 | * Do this checking under a lock; as multiple PCI devices | |
418 | * in one slot might report errors simultaneously, and we | |
419 | * only want one error recovery routine running. | |
1da177e4 | 420 | */ |
4907581d | 421 | eeh_serialize_lock(&flags); |
fd761fd8 | 422 | rc = 1; |
66523d9f GS |
423 | if (pe->state & EEH_PE_ISOLATED) { |
424 | pe->check_count++; | |
425 | if (pe->check_count % EEH_MAX_FAILS == 0) { | |
f36c5227 | 426 | location = of_get_property(dn, "ibm,loc-code", NULL); |
cb3bc9d0 | 427 | printk(KERN_ERR "EEH: %d reads ignored for recovering device at " |
f36c5227 | 428 | "location=%s driver=%s pci addr=%s\n", |
66523d9f | 429 | pe->check_count, location, |
778a785f | 430 | eeh_driver_name(dev), eeh_pci_name(dev)); |
cb3bc9d0 | 431 | printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n", |
778a785f | 432 | eeh_driver_name(dev)); |
5c1344e9 | 433 | dump_stack(); |
1da177e4 | 434 | } |
fd761fd8 | 435 | goto dn_unlock; |
1da177e4 LT |
436 | } |
437 | ||
438 | /* | |
439 | * Now test for an EEH failure. This is VERY expensive. | |
440 | * Note that the eeh_config_addr may be a parent device | |
441 | * in the case of a device behind a bridge, or it may be | |
442 | * function zero of a multi-function device. | |
443 | * In any case they must share a common PHB. | |
444 | */ | |
66523d9f | 445 | ret = eeh_ops->get_state(pe, NULL); |
76e6faf7 | 446 | |
39d16e29 | 447 | /* Note that config-io to empty slots may fail; |
cb3bc9d0 | 448 | * they are empty when they don't have children. |
eb594a47 GS |
449 | * We will punt with the following conditions: Failure to get |
450 | * PE's state, EEH not support and Permanently unavailable | |
451 | * state, PE is in good state. | |
cb3bc9d0 | 452 | */ |
eb594a47 GS |
453 | if ((ret < 0) || |
454 | (ret == EEH_STATE_NOT_SUPPORT) || | |
1ad7a72c | 455 | ((ret & active_flags) == active_flags)) { |
e575f8db | 456 | eeh_stats.false_positives++; |
66523d9f | 457 | pe->false_positives++; |
fd761fd8 LV |
458 | rc = 0; |
459 | goto dn_unlock; | |
76e6faf7 LV |
460 | } |
461 | ||
1ad7a72c GS |
462 | /* |
463 | * It should be corner case that the parent PE has been | |
464 | * put into frozen state as well. We should take care | |
465 | * that at first. | |
466 | */ | |
467 | parent_pe = pe->parent; | |
468 | while (parent_pe) { | |
469 | /* Hit the ceiling ? */ | |
470 | if (parent_pe->type & EEH_PE_PHB) | |
471 | break; | |
472 | ||
473 | /* Frozen parent PE ? */ | |
474 | ret = eeh_ops->get_state(parent_pe, NULL); | |
475 | if (ret > 0 && | |
476 | (ret & active_flags) != active_flags) | |
477 | pe = parent_pe; | |
478 | ||
479 | /* Next parent level */ | |
480 | parent_pe = parent_pe->parent; | |
481 | } | |
482 | ||
e575f8db | 483 | eeh_stats.slot_resets++; |
a84f273c | 484 | |
fd761fd8 LV |
485 | /* Avoid repeated reports of this failure, including problems |
486 | * with other functions on this device, and functions under | |
cb3bc9d0 GS |
487 | * bridges. |
488 | */ | |
66523d9f | 489 | eeh_pe_state_mark(pe, EEH_PE_ISOLATED); |
4907581d | 490 | eeh_serialize_unlock(flags); |
1da177e4 | 491 | |
1da177e4 LT |
492 | /* Most EEH events are due to device driver bugs. Having |
493 | * a stack trace will help the device-driver authors figure | |
cb3bc9d0 GS |
494 | * out what happened. So print that out. |
495 | */ | |
357b2f3d GS |
496 | phb_pe = eeh_phb_pe_get(pe->phb); |
497 | pr_err("EEH: Frozen PHB#%x-PE#%x detected\n", | |
498 | pe->phb->global_number, pe->addr); | |
499 | pr_err("EEH: PE location: %s, PHB location: %s\n", | |
500 | eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe)); | |
56ca4fde GS |
501 | dump_stack(); |
502 | ||
5293bf97 GS |
503 | eeh_send_failure_event(pe); |
504 | ||
fd761fd8 LV |
505 | return 1; |
506 | ||
507 | dn_unlock: | |
4907581d | 508 | eeh_serialize_unlock(flags); |
fd761fd8 | 509 | return rc; |
1da177e4 LT |
510 | } |
511 | ||
f8f7d63f | 512 | EXPORT_SYMBOL_GPL(eeh_dev_check_failure); |
1da177e4 LT |
513 | |
514 | /** | |
cb3bc9d0 GS |
515 | * eeh_check_failure - Check if all 1's data is due to EEH slot freeze |
516 | * @token: I/O token, should be address in the form 0xA.... | |
517 | * @val: value, should be all 1's (XXX why do we need this arg??) | |
1da177e4 | 518 | * |
1da177e4 LT |
519 | * Check for an EEH failure at the given token address. Call this |
520 | * routine if the result of a read was all 0xff's and you want to | |
521 | * find out if this is due to an EEH slot freeze event. This routine | |
522 | * will query firmware for the EEH status. | |
523 | * | |
524 | * Note this routine is safe to call in an interrupt context. | |
525 | */ | |
526 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
527 | { | |
528 | unsigned long addr; | |
f8f7d63f | 529 | struct eeh_dev *edev; |
1da177e4 LT |
530 | |
531 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
532 | addr = eeh_token_to_phys((unsigned long __force) token); | |
3ab96a02 | 533 | edev = eeh_addr_cache_get_dev(addr); |
f8f7d63f | 534 | if (!edev) { |
e575f8db | 535 | eeh_stats.no_device++; |
1da177e4 | 536 | return val; |
177bc936 | 537 | } |
1da177e4 | 538 | |
f8f7d63f | 539 | eeh_dev_check_failure(edev); |
1da177e4 LT |
540 | return val; |
541 | } | |
542 | ||
543 | EXPORT_SYMBOL(eeh_check_failure); | |
544 | ||
6dee3fb9 | 545 | |
47b5c838 | 546 | /** |
cce4b2d2 | 547 | * eeh_pci_enable - Enable MMIO or DMA transfers for this slot |
ff477966 | 548 | * @pe: EEH PE |
cb3bc9d0 GS |
549 | * |
550 | * This routine should be called to reenable frozen MMIO or DMA | |
551 | * so that it would work correctly again. It's useful while doing | |
552 | * recovery or log collection on the indicated device. | |
47b5c838 | 553 | */ |
ff477966 | 554 | int eeh_pci_enable(struct eeh_pe *pe, int function) |
47b5c838 | 555 | { |
78954700 GS |
556 | int rc, flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
557 | ||
558 | /* | |
559 | * pHyp doesn't allow to enable IO or DMA on unfrozen PE. | |
560 | * Also, it's pointless to enable them on unfrozen PE. So | |
561 | * we have the check here. | |
562 | */ | |
563 | if (function == EEH_OPT_THAW_MMIO || | |
564 | function == EEH_OPT_THAW_DMA) { | |
565 | rc = eeh_ops->get_state(pe, NULL); | |
566 | if (rc < 0) | |
567 | return rc; | |
568 | ||
569 | /* Needn't to enable or already enabled */ | |
570 | if ((rc == EEH_STATE_NOT_SUPPORT) || | |
571 | ((rc & flags) == flags)) | |
572 | return 0; | |
573 | } | |
47b5c838 | 574 | |
ff477966 | 575 | rc = eeh_ops->set_option(pe, function); |
47b5c838 | 576 | if (rc) |
78954700 GS |
577 | pr_warn("%s: Unexpected state change %d on " |
578 | "PHB#%d-PE#%x, err=%d\n", | |
579 | __func__, function, pe->phb->global_number, | |
580 | pe->addr, rc); | |
47b5c838 | 581 | |
ff477966 | 582 | rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); |
78954700 GS |
583 | if (rc <= 0) |
584 | return rc; | |
585 | ||
586 | if ((function == EEH_OPT_THAW_MMIO) && | |
587 | (rc & EEH_STATE_MMIO_ENABLED)) | |
588 | return 0; | |
589 | ||
590 | if ((function == EEH_OPT_THAW_DMA) && | |
591 | (rc & EEH_STATE_DMA_ENABLED)) | |
fa1be476 LV |
592 | return 0; |
593 | ||
47b5c838 LV |
594 | return rc; |
595 | } | |
596 | ||
00c2ae35 BK |
597 | /** |
598 | * pcibios_set_pcie_slot_reset - Set PCI-E reset state | |
cb3bc9d0 GS |
599 | * @dev: pci device struct |
600 | * @state: reset state to enter | |
00c2ae35 BK |
601 | * |
602 | * Return value: | |
603 | * 0 if success | |
cb3bc9d0 | 604 | */ |
00c2ae35 BK |
605 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) |
606 | { | |
c270a24c GS |
607 | struct eeh_dev *edev = pci_dev_to_eeh_dev(dev); |
608 | struct eeh_pe *pe = edev->pe; | |
609 | ||
610 | if (!pe) { | |
611 | pr_err("%s: No PE found on PCI device %s\n", | |
612 | __func__, pci_name(dev)); | |
613 | return -EINVAL; | |
614 | } | |
00c2ae35 BK |
615 | |
616 | switch (state) { | |
617 | case pcie_deassert_reset: | |
c270a24c | 618 | eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); |
00c2ae35 BK |
619 | break; |
620 | case pcie_hot_reset: | |
c270a24c | 621 | eeh_ops->reset(pe, EEH_RESET_HOT); |
00c2ae35 BK |
622 | break; |
623 | case pcie_warm_reset: | |
c270a24c | 624 | eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); |
00c2ae35 BK |
625 | break; |
626 | default: | |
627 | return -EINVAL; | |
628 | }; | |
629 | ||
630 | return 0; | |
631 | } | |
632 | ||
cb5b5624 | 633 | /** |
c270a24c GS |
634 | * eeh_set_pe_freset - Check the required reset for the indicated device |
635 | * @data: EEH device | |
636 | * @flag: return value | |
cb3bc9d0 GS |
637 | * |
638 | * Each device might have its preferred reset type: fundamental or | |
639 | * hot reset. The routine is used to collected the information for | |
640 | * the indicated device and its children so that the bunch of the | |
641 | * devices could be reset properly. | |
642 | */ | |
c270a24c | 643 | static void *eeh_set_dev_freset(void *data, void *flag) |
cb3bc9d0 GS |
644 | { |
645 | struct pci_dev *dev; | |
c270a24c GS |
646 | unsigned int *freset = (unsigned int *)flag; |
647 | struct eeh_dev *edev = (struct eeh_dev *)data; | |
6dee3fb9 | 648 | |
c270a24c | 649 | dev = eeh_dev_to_pci_dev(edev); |
cb3bc9d0 GS |
650 | if (dev) |
651 | *freset |= dev->needs_freset; | |
652 | ||
c270a24c | 653 | return NULL; |
cb3bc9d0 GS |
654 | } |
655 | ||
656 | /** | |
cce4b2d2 | 657 | * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second |
c270a24c | 658 | * @pe: EEH PE |
cb3bc9d0 GS |
659 | * |
660 | * Assert the PCI #RST line for 1/4 second. | |
661 | */ | |
c270a24c | 662 | static void eeh_reset_pe_once(struct eeh_pe *pe) |
6dee3fb9 | 663 | { |
308fc4f8 | 664 | unsigned int freset = 0; |
6e19314c | 665 | |
308fc4f8 RL |
666 | /* Determine type of EEH reset required for |
667 | * Partitionable Endpoint, a hot-reset (1) | |
668 | * or a fundamental reset (3). | |
669 | * A fundamental reset required by any device under | |
670 | * Partitionable Endpoint trumps hot-reset. | |
a84f273c | 671 | */ |
c270a24c | 672 | eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset); |
308fc4f8 RL |
673 | |
674 | if (freset) | |
c270a24c | 675 | eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); |
6e19314c | 676 | else |
c270a24c | 677 | eeh_ops->reset(pe, EEH_RESET_HOT); |
6dee3fb9 | 678 | |
c270a24c | 679 | eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); |
e1029263 LV |
680 | } |
681 | ||
cb3bc9d0 | 682 | /** |
cce4b2d2 | 683 | * eeh_reset_pe - Reset the indicated PE |
c270a24c | 684 | * @pe: EEH PE |
cb3bc9d0 GS |
685 | * |
686 | * This routine should be called to reset indicated device, including | |
687 | * PE. A PE might include multiple PCI devices and sometimes PCI bridges | |
688 | * might be involved as well. | |
689 | */ | |
c270a24c | 690 | int eeh_reset_pe(struct eeh_pe *pe) |
e1029263 | 691 | { |
326a98ea | 692 | int flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
e1029263 LV |
693 | int i, rc; |
694 | ||
9c547768 LV |
695 | /* Take three shots at resetting the bus */ |
696 | for (i=0; i<3; i++) { | |
c270a24c | 697 | eeh_reset_pe_once(pe); |
6dee3fb9 | 698 | |
78954700 GS |
699 | /* |
700 | * EEH_PE_ISOLATED is expected to be removed after | |
701 | * BAR restore. | |
702 | */ | |
c270a24c | 703 | rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); |
78954700 | 704 | if ((rc & flags) == flags) |
b6495c0c | 705 | return 0; |
e1029263 | 706 | |
e1029263 | 707 | if (rc < 0) { |
c270a24c GS |
708 | pr_err("%s: Unrecoverable slot failure on PHB#%d-PE#%x", |
709 | __func__, pe->phb->global_number, pe->addr); | |
b6495c0c | 710 | return -1; |
e1029263 | 711 | } |
c270a24c GS |
712 | pr_err("EEH: bus reset %d failed on PHB#%d-PE#%x, rc=%d\n", |
713 | i+1, pe->phb->global_number, pe->addr, rc); | |
6dee3fb9 | 714 | } |
b6495c0c | 715 | |
9c547768 | 716 | return -1; |
6dee3fb9 LV |
717 | } |
718 | ||
8b553f32 | 719 | /** |
cb3bc9d0 | 720 | * eeh_save_bars - Save device bars |
f631acd3 | 721 | * @edev: PCI device associated EEH device |
8b553f32 LV |
722 | * |
723 | * Save the values of the device bars. Unlike the restore | |
724 | * routine, this routine is *not* recursive. This is because | |
31116f0b | 725 | * PCI devices are added individually; but, for the restore, |
8b553f32 LV |
726 | * an entire slot is reset at a time. |
727 | */ | |
d7bb8862 | 728 | void eeh_save_bars(struct eeh_dev *edev) |
8b553f32 LV |
729 | { |
730 | int i; | |
f631acd3 | 731 | struct device_node *dn; |
8b553f32 | 732 | |
f631acd3 | 733 | if (!edev) |
8b553f32 | 734 | return; |
f631acd3 | 735 | dn = eeh_dev_to_of_node(edev); |
a84f273c | 736 | |
8b553f32 | 737 | for (i = 0; i < 16; i++) |
3780444c | 738 | eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]); |
bf898ec5 GS |
739 | |
740 | /* | |
741 | * For PCI bridges including root port, we need enable bus | |
742 | * master explicitly. Otherwise, it can't fetch IODA table | |
743 | * entries correctly. So we cache the bit in advance so that | |
744 | * we can restore it after reset, either PHB range or PE range. | |
745 | */ | |
746 | if (edev->mode & EEH_DEV_BRIDGE) | |
747 | edev->config_space[1] |= PCI_COMMAND_MASTER; | |
8b553f32 LV |
748 | } |
749 | ||
aa1e6374 GS |
750 | /** |
751 | * eeh_ops_register - Register platform dependent EEH operations | |
752 | * @ops: platform dependent EEH operations | |
753 | * | |
754 | * Register the platform dependent EEH operation callback | |
755 | * functions. The platform should call this function before | |
756 | * any other EEH operations. | |
757 | */ | |
758 | int __init eeh_ops_register(struct eeh_ops *ops) | |
759 | { | |
760 | if (!ops->name) { | |
761 | pr_warning("%s: Invalid EEH ops name for %p\n", | |
762 | __func__, ops); | |
763 | return -EINVAL; | |
764 | } | |
765 | ||
766 | if (eeh_ops && eeh_ops != ops) { | |
767 | pr_warning("%s: EEH ops of platform %s already existing (%s)\n", | |
768 | __func__, eeh_ops->name, ops->name); | |
769 | return -EEXIST; | |
770 | } | |
771 | ||
772 | eeh_ops = ops; | |
773 | ||
774 | return 0; | |
775 | } | |
776 | ||
777 | /** | |
778 | * eeh_ops_unregister - Unreigster platform dependent EEH operations | |
779 | * @name: name of EEH platform operations | |
780 | * | |
781 | * Unregister the platform dependent EEH operation callback | |
782 | * functions. | |
783 | */ | |
784 | int __exit eeh_ops_unregister(const char *name) | |
785 | { | |
786 | if (!name || !strlen(name)) { | |
787 | pr_warning("%s: Invalid EEH ops name\n", | |
788 | __func__); | |
789 | return -EINVAL; | |
790 | } | |
791 | ||
792 | if (eeh_ops && !strcmp(eeh_ops->name, name)) { | |
793 | eeh_ops = NULL; | |
794 | return 0; | |
795 | } | |
796 | ||
797 | return -EEXIST; | |
798 | } | |
799 | ||
66f9af83 GS |
800 | static int eeh_reboot_notifier(struct notifier_block *nb, |
801 | unsigned long action, void *unused) | |
802 | { | |
803 | eeh_set_enable(false); | |
804 | return NOTIFY_DONE; | |
805 | } | |
806 | ||
807 | static struct notifier_block eeh_reboot_nb = { | |
808 | .notifier_call = eeh_reboot_notifier, | |
809 | }; | |
810 | ||
cb3bc9d0 GS |
811 | /** |
812 | * eeh_init - EEH initialization | |
813 | * | |
1da177e4 LT |
814 | * Initialize EEH by trying to enable it for all of the adapters in the system. |
815 | * As a side effect we can determine here if eeh is supported at all. | |
816 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
817 | * check. If a user turns off EEH for a particular adapter they are really | |
818 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
819 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
820 | * EEH for all slots/all devices. | |
821 | * | |
822 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
823 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
824 | * newer systems can boot. | |
825 | */ | |
eeb6361f | 826 | int eeh_init(void) |
1da177e4 | 827 | { |
1a5c2e63 GS |
828 | struct pci_controller *hose, *tmp; |
829 | struct device_node *phb; | |
51fb5f56 GS |
830 | static int cnt = 0; |
831 | int ret = 0; | |
832 | ||
833 | /* | |
834 | * We have to delay the initialization on PowerNV after | |
835 | * the PCI hierarchy tree has been built because the PEs | |
836 | * are figured out based on PCI devices instead of device | |
837 | * tree nodes | |
838 | */ | |
839 | if (machine_is(powernv) && cnt++ <= 0) | |
840 | return ret; | |
e2af155c | 841 | |
66f9af83 GS |
842 | /* Register reboot notifier */ |
843 | ret = register_reboot_notifier(&eeh_reboot_nb); | |
844 | if (ret) { | |
845 | pr_warn("%s: Failed to register notifier (%d)\n", | |
846 | __func__, ret); | |
847 | return ret; | |
848 | } | |
849 | ||
e2af155c GS |
850 | /* call platform initialization function */ |
851 | if (!eeh_ops) { | |
852 | pr_warning("%s: Platform EEH operation not found\n", | |
853 | __func__); | |
35e5cfe2 | 854 | return -EEXIST; |
e2af155c GS |
855 | } else if ((ret = eeh_ops->init())) { |
856 | pr_warning("%s: Failed to call platform init function (%d)\n", | |
857 | __func__, ret); | |
35e5cfe2 | 858 | return ret; |
e2af155c | 859 | } |
1da177e4 | 860 | |
c8608558 GS |
861 | /* Initialize EEH event */ |
862 | ret = eeh_event_init(); | |
863 | if (ret) | |
864 | return ret; | |
865 | ||
1a5c2e63 | 866 | /* Enable EEH for all adapters */ |
d7bb8862 GS |
867 | if (eeh_probe_mode_devtree()) { |
868 | list_for_each_entry_safe(hose, tmp, | |
869 | &hose_list, list_node) { | |
870 | phb = hose->dn; | |
871 | traverse_pci_devices(phb, eeh_ops->of_probe, NULL); | |
872 | } | |
51fb5f56 GS |
873 | } else if (eeh_probe_mode_dev()) { |
874 | list_for_each_entry_safe(hose, tmp, | |
875 | &hose_list, list_node) | |
876 | pci_walk_bus(hose->bus, eeh_ops->dev_probe, NULL); | |
877 | } else { | |
8a5ad356 GS |
878 | pr_warn("%s: Invalid probe mode %x", |
879 | __func__, eeh_subsystem_flags); | |
51fb5f56 | 880 | return -EINVAL; |
1da177e4 LT |
881 | } |
882 | ||
21fd21f5 GS |
883 | /* |
884 | * Call platform post-initialization. Actually, It's good chance | |
885 | * to inform platform that EEH is ready to supply service if the | |
886 | * I/O cache stuff has been built up. | |
887 | */ | |
888 | if (eeh_ops->post_init) { | |
889 | ret = eeh_ops->post_init(); | |
890 | if (ret) | |
891 | return ret; | |
892 | } | |
893 | ||
2ec5a0ad | 894 | if (eeh_enabled()) |
d7bb8862 | 895 | pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n"); |
1da177e4 | 896 | else |
d7bb8862 | 897 | pr_warning("EEH: No capable adapters found\n"); |
35e5cfe2 GS |
898 | |
899 | return ret; | |
1da177e4 LT |
900 | } |
901 | ||
35e5cfe2 GS |
902 | core_initcall_sync(eeh_init); |
903 | ||
1da177e4 | 904 | /** |
cb3bc9d0 | 905 | * eeh_add_device_early - Enable EEH for the indicated device_node |
1da177e4 LT |
906 | * @dn: device node for which to set up EEH |
907 | * | |
908 | * This routine must be used to perform EEH initialization for PCI | |
909 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
910 | * This routine must be called before any i/o is performed to the | |
911 | * adapter (inluding any config-space i/o). | |
912 | * Whether this actually enables EEH or not for this device depends | |
913 | * on the CEC architecture, type of the device, on earlier boot | |
914 | * command-line arguments & etc. | |
915 | */ | |
f2856491 | 916 | void eeh_add_device_early(struct device_node *dn) |
1da177e4 LT |
917 | { |
918 | struct pci_controller *phb; | |
1da177e4 | 919 | |
26a74850 GS |
920 | /* |
921 | * If we're doing EEH probe based on PCI device, we | |
922 | * would delay the probe until late stage because | |
923 | * the PCI device isn't available this moment. | |
924 | */ | |
925 | if (!eeh_probe_mode_devtree()) | |
926 | return; | |
927 | ||
1e38b714 | 928 | if (!of_node_to_eeh_dev(dn)) |
1da177e4 | 929 | return; |
f631acd3 | 930 | phb = of_node_to_eeh_dev(dn)->phb; |
f751f841 LV |
931 | |
932 | /* USB Bus children of PCI devices will not have BUID's */ | |
933 | if (NULL == phb || 0 == phb->buid) | |
1da177e4 | 934 | return; |
1da177e4 | 935 | |
d7bb8862 | 936 | eeh_ops->of_probe(dn, NULL); |
1da177e4 | 937 | } |
1da177e4 | 938 | |
cb3bc9d0 GS |
939 | /** |
940 | * eeh_add_device_tree_early - Enable EEH for the indicated device | |
941 | * @dn: device node | |
942 | * | |
943 | * This routine must be used to perform EEH initialization for the | |
944 | * indicated PCI device that was added after system boot (e.g. | |
945 | * hotplug, dlpar). | |
946 | */ | |
e2a296ee LV |
947 | void eeh_add_device_tree_early(struct device_node *dn) |
948 | { | |
949 | struct device_node *sib; | |
acaa6176 SR |
950 | |
951 | for_each_child_of_node(dn, sib) | |
e2a296ee LV |
952 | eeh_add_device_tree_early(sib); |
953 | eeh_add_device_early(dn); | |
954 | } | |
955 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
956 | ||
1da177e4 | 957 | /** |
cb3bc9d0 | 958 | * eeh_add_device_late - Perform EEH initialization for the indicated pci device |
1da177e4 LT |
959 | * @dev: pci device for which to set up EEH |
960 | * | |
961 | * This routine must be used to complete EEH initialization for PCI | |
962 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
963 | */ | |
f2856491 | 964 | void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 965 | { |
56b0fca3 | 966 | struct device_node *dn; |
f631acd3 | 967 | struct eeh_dev *edev; |
56b0fca3 | 968 | |
2ec5a0ad | 969 | if (!dev || !eeh_enabled()) |
1da177e4 LT |
970 | return; |
971 | ||
57b066ff | 972 | pr_debug("EEH: Adding device %s\n", pci_name(dev)); |
1da177e4 | 973 | |
56b0fca3 | 974 | dn = pci_device_to_OF_node(dev); |
2ef822c5 | 975 | edev = of_node_to_eeh_dev(dn); |
f631acd3 | 976 | if (edev->pdev == dev) { |
57b066ff BH |
977 | pr_debug("EEH: Already referenced !\n"); |
978 | return; | |
979 | } | |
f5c57710 GS |
980 | |
981 | /* | |
982 | * The EEH cache might not be removed correctly because of | |
983 | * unbalanced kref to the device during unplug time, which | |
984 | * relies on pcibios_release_device(). So we have to remove | |
985 | * that here explicitly. | |
986 | */ | |
987 | if (edev->pdev) { | |
988 | eeh_rmv_from_parent_pe(edev); | |
989 | eeh_addr_cache_rmv_dev(edev->pdev); | |
990 | eeh_sysfs_remove_device(edev->pdev); | |
ab55d218 | 991 | edev->mode &= ~EEH_DEV_SYSFS; |
f5c57710 | 992 | |
f26c7a03 GS |
993 | /* |
994 | * We definitely should have the PCI device removed | |
995 | * though it wasn't correctly. So we needn't call | |
996 | * into error handler afterwards. | |
997 | */ | |
998 | edev->mode |= EEH_DEV_NO_HANDLER; | |
999 | ||
f5c57710 GS |
1000 | edev->pdev = NULL; |
1001 | dev->dev.archdata.edev = NULL; | |
1002 | } | |
57b066ff | 1003 | |
f631acd3 GS |
1004 | edev->pdev = dev; |
1005 | dev->dev.archdata.edev = edev; | |
56b0fca3 | 1006 | |
26a74850 GS |
1007 | /* |
1008 | * We have to do the EEH probe here because the PCI device | |
1009 | * hasn't been created yet in the early stage. | |
1010 | */ | |
1011 | if (eeh_probe_mode_dev()) | |
1012 | eeh_ops->dev_probe(dev, NULL); | |
1013 | ||
3ab96a02 | 1014 | eeh_addr_cache_insert_dev(dev); |
1da177e4 | 1015 | } |
794e085e | 1016 | |
cb3bc9d0 GS |
1017 | /** |
1018 | * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus | |
1019 | * @bus: PCI bus | |
1020 | * | |
1021 | * This routine must be used to perform EEH initialization for PCI | |
1022 | * devices which are attached to the indicated PCI bus. The PCI bus | |
1023 | * is added after system boot through hotplug or dlpar. | |
1024 | */ | |
794e085e NF |
1025 | void eeh_add_device_tree_late(struct pci_bus *bus) |
1026 | { | |
1027 | struct pci_dev *dev; | |
1028 | ||
1029 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
a84f273c GS |
1030 | eeh_add_device_late(dev); |
1031 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1032 | struct pci_bus *subbus = dev->subordinate; | |
1033 | if (subbus) | |
1034 | eeh_add_device_tree_late(subbus); | |
1035 | } | |
794e085e NF |
1036 | } |
1037 | } | |
1038 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 | 1039 | |
6a040ce7 TLSC |
1040 | /** |
1041 | * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus | |
1042 | * @bus: PCI bus | |
1043 | * | |
1044 | * This routine must be used to add EEH sysfs files for PCI | |
1045 | * devices which are attached to the indicated PCI bus. The PCI bus | |
1046 | * is added after system boot through hotplug or dlpar. | |
1047 | */ | |
1048 | void eeh_add_sysfs_files(struct pci_bus *bus) | |
1049 | { | |
1050 | struct pci_dev *dev; | |
1051 | ||
1052 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1053 | eeh_sysfs_add_device(dev); | |
1054 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1055 | struct pci_bus *subbus = dev->subordinate; | |
1056 | if (subbus) | |
1057 | eeh_add_sysfs_files(subbus); | |
1058 | } | |
1059 | } | |
1060 | } | |
1061 | EXPORT_SYMBOL_GPL(eeh_add_sysfs_files); | |
1062 | ||
1da177e4 | 1063 | /** |
cb3bc9d0 | 1064 | * eeh_remove_device - Undo EEH setup for the indicated pci device |
1da177e4 LT |
1065 | * @dev: pci device to be removed |
1066 | * | |
794e085e NF |
1067 | * This routine should be called when a device is removed from |
1068 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
1069 | * the PCI device from the EEH subsystem. I/O errors affecting | |
1070 | * this device will no longer be detected after this call; thus, | |
1071 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 1072 | */ |
807a827d | 1073 | void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 1074 | { |
f631acd3 GS |
1075 | struct eeh_dev *edev; |
1076 | ||
2ec5a0ad | 1077 | if (!dev || !eeh_enabled()) |
1da177e4 | 1078 | return; |
f631acd3 | 1079 | edev = pci_dev_to_eeh_dev(dev); |
1da177e4 LT |
1080 | |
1081 | /* Unregister the device with the EEH/PCI address search system */ | |
57b066ff | 1082 | pr_debug("EEH: Removing device %s\n", pci_name(dev)); |
56b0fca3 | 1083 | |
f5c57710 | 1084 | if (!edev || !edev->pdev || !edev->pe) { |
57b066ff BH |
1085 | pr_debug("EEH: Not referenced !\n"); |
1086 | return; | |
b055a9e1 | 1087 | } |
f5c57710 GS |
1088 | |
1089 | /* | |
1090 | * During the hotplug for EEH error recovery, we need the EEH | |
1091 | * device attached to the parent PE in order for BAR restore | |
1092 | * a bit later. So we keep it for BAR restore and remove it | |
1093 | * from the parent PE during the BAR resotre. | |
1094 | */ | |
f631acd3 GS |
1095 | edev->pdev = NULL; |
1096 | dev->dev.archdata.edev = NULL; | |
f5c57710 GS |
1097 | if (!(edev->pe->state & EEH_PE_KEEP)) |
1098 | eeh_rmv_from_parent_pe(edev); | |
1099 | else | |
1100 | edev->mode |= EEH_DEV_DISCONNECTED; | |
57b066ff | 1101 | |
f26c7a03 GS |
1102 | /* |
1103 | * We're removing from the PCI subsystem, that means | |
1104 | * the PCI device driver can't support EEH or not | |
1105 | * well. So we rely on hotplug completely to do recovery | |
1106 | * for the specific PCI device. | |
1107 | */ | |
1108 | edev->mode |= EEH_DEV_NO_HANDLER; | |
1109 | ||
3ab96a02 | 1110 | eeh_addr_cache_rmv_dev(dev); |
57b066ff | 1111 | eeh_sysfs_remove_device(dev); |
ab55d218 | 1112 | edev->mode &= ~EEH_DEV_SYSFS; |
1da177e4 | 1113 | } |
1da177e4 | 1114 | |
212d16cd GS |
1115 | /** |
1116 | * eeh_dev_open - Increase count of pass through devices for PE | |
1117 | * @pdev: PCI device | |
1118 | * | |
1119 | * Increase count of passed through devices for the indicated | |
1120 | * PE. In the result, the EEH errors detected on the PE won't be | |
1121 | * reported. The PE owner will be responsible for detection | |
1122 | * and recovery. | |
1123 | */ | |
1124 | int eeh_dev_open(struct pci_dev *pdev) | |
1125 | { | |
1126 | struct eeh_dev *edev; | |
1127 | ||
1128 | mutex_lock(&eeh_dev_mutex); | |
1129 | ||
1130 | /* No PCI device ? */ | |
1131 | if (!pdev) | |
1132 | goto out; | |
1133 | ||
1134 | /* No EEH device or PE ? */ | |
1135 | edev = pci_dev_to_eeh_dev(pdev); | |
1136 | if (!edev || !edev->pe) | |
1137 | goto out; | |
1138 | ||
1139 | /* Increase PE's pass through count */ | |
1140 | atomic_inc(&edev->pe->pass_dev_cnt); | |
1141 | mutex_unlock(&eeh_dev_mutex); | |
1142 | ||
1143 | return 0; | |
1144 | out: | |
1145 | mutex_unlock(&eeh_dev_mutex); | |
1146 | return -ENODEV; | |
1147 | } | |
1148 | EXPORT_SYMBOL_GPL(eeh_dev_open); | |
1149 | ||
1150 | /** | |
1151 | * eeh_dev_release - Decrease count of pass through devices for PE | |
1152 | * @pdev: PCI device | |
1153 | * | |
1154 | * Decrease count of pass through devices for the indicated PE. If | |
1155 | * there is no passed through device in PE, the EEH errors detected | |
1156 | * on the PE will be reported and handled as usual. | |
1157 | */ | |
1158 | void eeh_dev_release(struct pci_dev *pdev) | |
1159 | { | |
1160 | struct eeh_dev *edev; | |
1161 | ||
1162 | mutex_lock(&eeh_dev_mutex); | |
1163 | ||
1164 | /* No PCI device ? */ | |
1165 | if (!pdev) | |
1166 | goto out; | |
1167 | ||
1168 | /* No EEH device ? */ | |
1169 | edev = pci_dev_to_eeh_dev(pdev); | |
1170 | if (!edev || !edev->pe || !eeh_pe_passed(edev->pe)) | |
1171 | goto out; | |
1172 | ||
1173 | /* Decrease PE's pass through count */ | |
1174 | atomic_dec(&edev->pe->pass_dev_cnt); | |
1175 | WARN_ON(atomic_read(&edev->pe->pass_dev_cnt) < 0); | |
1176 | out: | |
1177 | mutex_unlock(&eeh_dev_mutex); | |
1178 | } | |
1179 | EXPORT_SYMBOL(eeh_dev_release); | |
1180 | ||
1181 | /** | |
1182 | * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE | |
1183 | * @group: IOMMU group | |
1184 | * | |
1185 | * The routine is called to convert IOMMU group to EEH PE. | |
1186 | */ | |
1187 | struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group) | |
1188 | { | |
1189 | struct iommu_table *tbl; | |
1190 | struct pci_dev *pdev = NULL; | |
1191 | struct eeh_dev *edev; | |
1192 | bool found = false; | |
1193 | ||
1194 | /* No IOMMU group ? */ | |
1195 | if (!group) | |
1196 | return NULL; | |
1197 | ||
1198 | /* No PCI device ? */ | |
1199 | for_each_pci_dev(pdev) { | |
1200 | tbl = get_iommu_table_base(&pdev->dev); | |
1201 | if (tbl && tbl->it_group == group) { | |
1202 | found = true; | |
1203 | break; | |
1204 | } | |
1205 | } | |
1206 | if (!found) | |
1207 | return NULL; | |
1208 | ||
1209 | /* No EEH device or PE ? */ | |
1210 | edev = pci_dev_to_eeh_dev(pdev); | |
1211 | if (!edev || !edev->pe) | |
1212 | return NULL; | |
1213 | ||
1214 | return edev->pe; | |
1215 | } | |
1216 | ||
1217 | /** | |
1218 | * eeh_pe_set_option - Set options for the indicated PE | |
1219 | * @pe: EEH PE | |
1220 | * @option: requested option | |
1221 | * | |
1222 | * The routine is called to enable or disable EEH functionality | |
1223 | * on the indicated PE, to enable IO or DMA for the frozen PE. | |
1224 | */ | |
1225 | int eeh_pe_set_option(struct eeh_pe *pe, int option) | |
1226 | { | |
1227 | int ret = 0; | |
1228 | ||
1229 | /* Invalid PE ? */ | |
1230 | if (!pe) | |
1231 | return -ENODEV; | |
1232 | ||
1233 | /* | |
1234 | * EEH functionality could possibly be disabled, just | |
1235 | * return error for the case. And the EEH functinality | |
1236 | * isn't expected to be disabled on one specific PE. | |
1237 | */ | |
1238 | switch (option) { | |
1239 | case EEH_OPT_ENABLE: | |
1240 | if (eeh_enabled()) | |
1241 | break; | |
1242 | ret = -EIO; | |
1243 | break; | |
1244 | case EEH_OPT_DISABLE: | |
1245 | break; | |
1246 | case EEH_OPT_THAW_MMIO: | |
1247 | case EEH_OPT_THAW_DMA: | |
1248 | if (!eeh_ops || !eeh_ops->set_option) { | |
1249 | ret = -ENOENT; | |
1250 | break; | |
1251 | } | |
1252 | ||
1253 | ret = eeh_ops->set_option(pe, option); | |
1254 | break; | |
1255 | default: | |
1256 | pr_debug("%s: Option %d out of range (%d, %d)\n", | |
1257 | __func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA); | |
1258 | ret = -EINVAL; | |
1259 | } | |
1260 | ||
1261 | return ret; | |
1262 | } | |
1263 | EXPORT_SYMBOL_GPL(eeh_pe_set_option); | |
1264 | ||
1265 | /** | |
1266 | * eeh_pe_get_state - Retrieve PE's state | |
1267 | * @pe: EEH PE | |
1268 | * | |
1269 | * Retrieve the PE's state, which includes 3 aspects: enabled | |
1270 | * DMA, enabled IO and asserted reset. | |
1271 | */ | |
1272 | int eeh_pe_get_state(struct eeh_pe *pe) | |
1273 | { | |
1274 | int result, ret = 0; | |
1275 | bool rst_active, dma_en, mmio_en; | |
1276 | ||
1277 | /* Existing PE ? */ | |
1278 | if (!pe) | |
1279 | return -ENODEV; | |
1280 | ||
1281 | if (!eeh_ops || !eeh_ops->get_state) | |
1282 | return -ENOENT; | |
1283 | ||
1284 | result = eeh_ops->get_state(pe, NULL); | |
1285 | rst_active = !!(result & EEH_STATE_RESET_ACTIVE); | |
1286 | dma_en = !!(result & EEH_STATE_DMA_ENABLED); | |
1287 | mmio_en = !!(result & EEH_STATE_MMIO_ENABLED); | |
1288 | ||
1289 | if (rst_active) | |
1290 | ret = EEH_PE_STATE_RESET; | |
1291 | else if (dma_en && mmio_en) | |
1292 | ret = EEH_PE_STATE_NORMAL; | |
1293 | else if (!dma_en && !mmio_en) | |
1294 | ret = EEH_PE_STATE_STOPPED_IO_DMA; | |
1295 | else if (!dma_en && mmio_en) | |
1296 | ret = EEH_PE_STATE_STOPPED_DMA; | |
1297 | else | |
1298 | ret = EEH_PE_STATE_UNAVAIL; | |
1299 | ||
1300 | return ret; | |
1301 | } | |
1302 | EXPORT_SYMBOL_GPL(eeh_pe_get_state); | |
1303 | ||
1304 | /** | |
1305 | * eeh_pe_reset - Issue PE reset according to specified type | |
1306 | * @pe: EEH PE | |
1307 | * @option: reset type | |
1308 | * | |
1309 | * The routine is called to reset the specified PE with the | |
1310 | * indicated type, either fundamental reset or hot reset. | |
1311 | * PE reset is the most important part for error recovery. | |
1312 | */ | |
1313 | int eeh_pe_reset(struct eeh_pe *pe, int option) | |
1314 | { | |
1315 | int ret = 0; | |
1316 | ||
1317 | /* Invalid PE ? */ | |
1318 | if (!pe) | |
1319 | return -ENODEV; | |
1320 | ||
1321 | if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset) | |
1322 | return -ENOENT; | |
1323 | ||
1324 | switch (option) { | |
1325 | case EEH_RESET_DEACTIVATE: | |
1326 | ret = eeh_ops->reset(pe, option); | |
1327 | if (ret) | |
1328 | break; | |
1329 | ||
1330 | /* | |
1331 | * The PE is still in frozen state and we need to clear | |
1332 | * that. It's good to clear frozen state after deassert | |
1333 | * to avoid messy IO access during reset, which might | |
1334 | * cause recursive frozen PE. | |
1335 | */ | |
1336 | ret = eeh_ops->set_option(pe, EEH_OPT_THAW_MMIO); | |
1337 | if (!ret) | |
1338 | ret = eeh_ops->set_option(pe, EEH_OPT_THAW_DMA); | |
1339 | if (!ret) | |
1340 | eeh_pe_state_clear(pe, EEH_PE_ISOLATED); | |
1341 | break; | |
1342 | case EEH_RESET_HOT: | |
1343 | case EEH_RESET_FUNDAMENTAL: | |
1344 | ret = eeh_ops->reset(pe, option); | |
1345 | break; | |
1346 | default: | |
1347 | pr_debug("%s: Unsupported option %d\n", | |
1348 | __func__, option); | |
1349 | ret = -EINVAL; | |
1350 | } | |
1351 | ||
1352 | return ret; | |
1353 | } | |
1354 | EXPORT_SYMBOL_GPL(eeh_pe_reset); | |
1355 | ||
1356 | /** | |
1357 | * eeh_pe_configure - Configure PCI bridges after PE reset | |
1358 | * @pe: EEH PE | |
1359 | * | |
1360 | * The routine is called to restore the PCI config space for | |
1361 | * those PCI devices, especially PCI bridges affected by PE | |
1362 | * reset issued previously. | |
1363 | */ | |
1364 | int eeh_pe_configure(struct eeh_pe *pe) | |
1365 | { | |
1366 | int ret = 0; | |
1367 | ||
1368 | /* Invalid PE ? */ | |
1369 | if (!pe) | |
1370 | return -ENODEV; | |
1371 | ||
1372 | /* Restore config space for the affected devices */ | |
1373 | eeh_pe_restore_bars(pe); | |
1374 | ||
1375 | return ret; | |
1376 | } | |
1377 | EXPORT_SYMBOL_GPL(eeh_pe_configure); | |
1378 | ||
1da177e4 LT |
1379 | static int proc_eeh_show(struct seq_file *m, void *v) |
1380 | { | |
2ec5a0ad | 1381 | if (!eeh_enabled()) { |
1da177e4 | 1382 | seq_printf(m, "EEH Subsystem is globally disabled\n"); |
e575f8db | 1383 | seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs); |
1da177e4 LT |
1384 | } else { |
1385 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 | 1386 | seq_printf(m, |
e575f8db GS |
1387 | "no device=%llu\n" |
1388 | "no device node=%llu\n" | |
1389 | "no config address=%llu\n" | |
1390 | "check not wanted=%llu\n" | |
1391 | "eeh_total_mmio_ffs=%llu\n" | |
1392 | "eeh_false_positives=%llu\n" | |
1393 | "eeh_slot_resets=%llu\n", | |
1394 | eeh_stats.no_device, | |
1395 | eeh_stats.no_dn, | |
1396 | eeh_stats.no_cfg_addr, | |
1397 | eeh_stats.ignored_check, | |
1398 | eeh_stats.total_mmio_ffs, | |
1399 | eeh_stats.false_positives, | |
1400 | eeh_stats.slot_resets); | |
1da177e4 LT |
1401 | } |
1402 | ||
1403 | return 0; | |
1404 | } | |
1405 | ||
1406 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1407 | { | |
1408 | return single_open(file, proc_eeh_show, NULL); | |
1409 | } | |
1410 | ||
5dfe4c96 | 1411 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1412 | .open = proc_eeh_open, |
1413 | .read = seq_read, | |
1414 | .llseek = seq_lseek, | |
1415 | .release = single_release, | |
1416 | }; | |
1417 | ||
7f52a526 GS |
1418 | #ifdef CONFIG_DEBUG_FS |
1419 | static int eeh_enable_dbgfs_set(void *data, u64 val) | |
1420 | { | |
1421 | if (val) | |
1422 | eeh_subsystem_flags &= ~EEH_FORCE_DISABLED; | |
1423 | else | |
1424 | eeh_subsystem_flags |= EEH_FORCE_DISABLED; | |
1425 | ||
1426 | /* Notify the backend */ | |
1427 | if (eeh_ops->post_init) | |
1428 | eeh_ops->post_init(); | |
1429 | ||
1430 | return 0; | |
1431 | } | |
1432 | ||
1433 | static int eeh_enable_dbgfs_get(void *data, u64 *val) | |
1434 | { | |
1435 | if (eeh_enabled()) | |
1436 | *val = 0x1ul; | |
1437 | else | |
1438 | *val = 0x0ul; | |
1439 | return 0; | |
1440 | } | |
1441 | ||
1442 | DEFINE_SIMPLE_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get, | |
1443 | eeh_enable_dbgfs_set, "0x%llx\n"); | |
1444 | #endif | |
1445 | ||
1da177e4 LT |
1446 | static int __init eeh_init_proc(void) |
1447 | { | |
7f52a526 | 1448 | if (machine_is(pseries) || machine_is(powernv)) { |
8feaa434 | 1449 | proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations); |
7f52a526 GS |
1450 | #ifdef CONFIG_DEBUG_FS |
1451 | debugfs_create_file("eeh_enable", 0600, | |
1452 | powerpc_debugfs_root, NULL, | |
1453 | &eeh_enable_dbgfs_ops); | |
1454 | #endif | |
1455 | } | |
1456 | ||
1da177e4 LT |
1457 | return 0; |
1458 | } | |
1459 | __initcall(eeh_init_proc); |