Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3c8c90ab LV |
2 | * Copyright IBM Corporation 2001, 2005, 2006 |
3 | * Copyright Dave Engebretsen & Todd Inglett 2001 | |
4 | * Copyright Linas Vepstas 2005, 2006 | |
cb3bc9d0 | 5 | * Copyright 2001-2012 IBM Corporation. |
69376502 | 6 | * |
1da177e4 LT |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
69376502 | 11 | * |
1da177e4 LT |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
69376502 | 16 | * |
1da177e4 LT |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
3c8c90ab LV |
20 | * |
21 | * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> | |
1da177e4 LT |
22 | */ |
23 | ||
6dee3fb9 | 24 | #include <linux/delay.h> |
cb3bc9d0 | 25 | #include <linux/sched.h> |
1da177e4 LT |
26 | #include <linux/init.h> |
27 | #include <linux/list.h> | |
1da177e4 LT |
28 | #include <linux/pci.h> |
29 | #include <linux/proc_fs.h> | |
30 | #include <linux/rbtree.h> | |
66f9af83 | 31 | #include <linux/reboot.h> |
1da177e4 LT |
32 | #include <linux/seq_file.h> |
33 | #include <linux/spinlock.h> | |
66b15db6 | 34 | #include <linux/export.h> |
acaa6176 SR |
35 | #include <linux/of.h> |
36 | ||
60063497 | 37 | #include <linux/atomic.h> |
1da177e4 | 38 | #include <asm/eeh.h> |
172ca926 | 39 | #include <asm/eeh_event.h> |
1da177e4 LT |
40 | #include <asm/io.h> |
41 | #include <asm/machdep.h> | |
172ca926 | 42 | #include <asm/ppc-pci.h> |
1da177e4 | 43 | #include <asm/rtas.h> |
1da177e4 | 44 | |
1da177e4 LT |
45 | |
46 | /** Overview: | |
47 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
48 | * dealing with PCI bus errors that can't be dealt with within the | |
49 | * usual PCI framework, except by check-stopping the CPU. Systems | |
50 | * that are designed for high-availability/reliability cannot afford | |
51 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
52 | * An EEH-capable bridge operates by converting a detected error | |
53 | * into a "slot freeze", taking the PCI adapter off-line, making | |
54 | * the slot behave, from the OS'es point of view, as if the slot | |
55 | * were "empty": all reads return 0xff's and all writes are silently | |
56 | * ignored. EEH slot isolation events can be triggered by parity | |
57 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
58 | * which in turn might be caused by low voltage on the bus, dust, |
59 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
60 | * |
61 | * Note, however, that one of the leading causes of EEH slot | |
62 | * freeze events are buggy device drivers, buggy device microcode, | |
63 | * or buggy device hardware. This is because any attempt by the | |
64 | * device to bus-master data to a memory address that is not | |
65 | * assigned to the device will trigger a slot freeze. (The idea | |
66 | * is to prevent devices-gone-wild from corrupting system memory). | |
67 | * Buggy hardware/drivers will have a miserable time co-existing | |
68 | * with EEH. | |
69 | * | |
70 | * Ideally, a PCI device driver, when suspecting that an isolation | |
25985edc | 71 | * event has occurred (e.g. by reading 0xff's), will then ask EEH |
1da177e4 LT |
72 | * whether this is the case, and then take appropriate steps to |
73 | * reset the PCI slot, the PCI device, and then resume operations. | |
74 | * However, until that day, the checking is done here, with the | |
75 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
76 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
77 | * and sent out for processing. | |
78 | */ | |
79 | ||
5c1344e9 | 80 | /* If a device driver keeps reading an MMIO register in an interrupt |
f36c5227 MM |
81 | * handler after a slot isolation event, it might be broken. |
82 | * This sets the threshold for how many read attempts we allow | |
83 | * before printing an error message. | |
1da177e4 | 84 | */ |
2fd30be8 | 85 | #define EEH_MAX_FAILS 2100000 |
1da177e4 | 86 | |
17213c3b | 87 | /* Time to wait for a PCI slot to report status, in milliseconds */ |
fb48dc22 | 88 | #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000) |
9c547768 | 89 | |
aa1e6374 GS |
90 | /* Platform dependent EEH operations */ |
91 | struct eeh_ops *eeh_ops = NULL; | |
92 | ||
2ec5a0ad | 93 | bool eeh_subsystem_enabled = false; |
1e28a7dd | 94 | EXPORT_SYMBOL(eeh_subsystem_enabled); |
1da177e4 | 95 | |
d7bb8862 GS |
96 | /* |
97 | * EEH probe mode support. The intention is to support multiple | |
98 | * platforms for EEH. Some platforms like pSeries do PCI emunation | |
99 | * based on device tree. However, other platforms like powernv probe | |
100 | * PCI devices from hardware. The flag is used to distinguish that. | |
101 | * In addition, struct eeh_ops::probe would be invoked for particular | |
102 | * OF node or PCI device so that the corresponding PE would be created | |
103 | * there. | |
104 | */ | |
105 | int eeh_probe_mode; | |
106 | ||
fd761fd8 | 107 | /* Lock to avoid races due to multiple reports of an error */ |
4907581d | 108 | DEFINE_RAW_SPINLOCK(confirm_error_lock); |
fd761fd8 | 109 | |
17213c3b LV |
110 | /* Buffer for reporting pci register dumps. Its here in BSS, and |
111 | * not dynamically alloced, so that it ends up in RMO where RTAS | |
112 | * can access it. | |
113 | */ | |
d99bb1db LV |
114 | #define EEH_PCI_REGS_LOG_LEN 4096 |
115 | static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; | |
116 | ||
e575f8db GS |
117 | /* |
118 | * The struct is used to maintain the EEH global statistic | |
119 | * information. Besides, the EEH global statistics will be | |
120 | * exported to user space through procfs | |
121 | */ | |
122 | struct eeh_stats { | |
123 | u64 no_device; /* PCI device not found */ | |
124 | u64 no_dn; /* OF node not found */ | |
125 | u64 no_cfg_addr; /* Config address not found */ | |
126 | u64 ignored_check; /* EEH check skipped */ | |
127 | u64 total_mmio_ffs; /* Total EEH checks */ | |
128 | u64 false_positives; /* Unnecessary EEH checks */ | |
129 | u64 slot_resets; /* PE reset */ | |
130 | }; | |
131 | ||
132 | static struct eeh_stats eeh_stats; | |
1da177e4 | 133 | |
7684b40c LV |
134 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
135 | ||
d99bb1db | 136 | /** |
cce4b2d2 | 137 | * eeh_gather_pci_data - Copy assorted PCI config space registers to buff |
f631acd3 | 138 | * @edev: device to report data for |
d99bb1db LV |
139 | * @buf: point to buffer in which to log |
140 | * @len: amount of room in buffer | |
141 | * | |
142 | * This routine captures assorted PCI configuration space data, | |
143 | * and puts them into a buffer for RTAS error logging. | |
144 | */ | |
f631acd3 | 145 | static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len) |
d99bb1db | 146 | { |
f631acd3 | 147 | struct device_node *dn = eeh_dev_to_of_node(edev); |
d99bb1db | 148 | u32 cfg; |
fcf9892b | 149 | int cap, i; |
d99bb1db LV |
150 | int n = 0; |
151 | ||
f631acd3 | 152 | n += scnprintf(buf+n, len-n, "%s\n", dn->full_name); |
2d86c385 | 153 | pr_warn("EEH: of node=%s\n", dn->full_name); |
fcf9892b | 154 | |
3780444c | 155 | eeh_ops->read_config(dn, PCI_VENDOR_ID, 4, &cfg); |
fcf9892b | 156 | n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); |
2d86c385 | 157 | pr_warn("EEH: PCI device/vendor: %08x\n", cfg); |
fcf9892b | 158 | |
3780444c | 159 | eeh_ops->read_config(dn, PCI_COMMAND, 4, &cfg); |
d99bb1db | 160 | n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); |
2d86c385 | 161 | pr_warn("EEH: PCI cmd/status register: %08x\n", cfg); |
fcf9892b | 162 | |
0b9369f4 | 163 | /* Gather bridge-specific registers */ |
2a18dfc6 | 164 | if (edev->mode & EEH_DEV_BRIDGE) { |
3780444c | 165 | eeh_ops->read_config(dn, PCI_SEC_STATUS, 2, &cfg); |
0b9369f4 | 166 | n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); |
2d86c385 | 167 | pr_warn("EEH: Bridge secondary status: %04x\n", cfg); |
0b9369f4 | 168 | |
3780444c | 169 | eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &cfg); |
0b9369f4 | 170 | n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); |
2d86c385 | 171 | pr_warn("EEH: Bridge control: %04x\n", cfg); |
0b9369f4 LV |
172 | } |
173 | ||
fcf9892b | 174 | /* Dump out the PCI-X command and status regs */ |
2a18dfc6 | 175 | cap = edev->pcix_cap; |
fcf9892b | 176 | if (cap) { |
3780444c | 177 | eeh_ops->read_config(dn, cap, 4, &cfg); |
fcf9892b | 178 | n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); |
2d86c385 | 179 | pr_warn("EEH: PCI-X cmd: %08x\n", cfg); |
fcf9892b | 180 | |
3780444c | 181 | eeh_ops->read_config(dn, cap+4, 4, &cfg); |
fcf9892b | 182 | n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); |
2d86c385 | 183 | pr_warn("EEH: PCI-X status: %08x\n", cfg); |
fcf9892b LV |
184 | } |
185 | ||
2a18dfc6 GS |
186 | /* If PCI-E capable, dump PCI-E cap 10 */ |
187 | cap = edev->pcie_cap; | |
188 | if (cap) { | |
fcf9892b | 189 | n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); |
2d86c385 | 190 | pr_warn("EEH: PCI-E capabilities and status follow:\n"); |
fcf9892b LV |
191 | |
192 | for (i=0; i<=8; i++) { | |
2a18dfc6 | 193 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); |
fcf9892b | 194 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
2d86c385 | 195 | pr_warn("EEH: PCI-E %02x: %08x\n", i, cfg); |
fcf9892b | 196 | } |
2a18dfc6 | 197 | } |
fcf9892b | 198 | |
2a18dfc6 GS |
199 | /* If AER capable, dump it */ |
200 | cap = edev->aer_cap; | |
201 | if (cap) { | |
202 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); | |
203 | pr_warn("EEH: PCI-E AER capability register set follows:\n"); | |
204 | ||
205 | for (i=0; i<14; i++) { | |
206 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); | |
207 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
208 | pr_warn("EEH: PCI-E AER %02x: %08x\n", i, cfg); | |
fcf9892b LV |
209 | } |
210 | } | |
0b9369f4 | 211 | |
d99bb1db LV |
212 | return n; |
213 | } | |
214 | ||
cb3bc9d0 GS |
215 | /** |
216 | * eeh_slot_error_detail - Generate combined log including driver log and error log | |
ff477966 | 217 | * @pe: EEH PE |
cb3bc9d0 GS |
218 | * @severity: temporary or permanent error log |
219 | * | |
220 | * This routine should be called to generate the combined log, which | |
221 | * is comprised of driver log and error log. The driver log is figured | |
222 | * out from the config space of the corresponding PCI device, while | |
223 | * the error log is fetched through platform dependent function call. | |
224 | */ | |
ff477966 | 225 | void eeh_slot_error_detail(struct eeh_pe *pe, int severity) |
d99bb1db LV |
226 | { |
227 | size_t loglen = 0; | |
9feed42e | 228 | struct eeh_dev *edev, *tmp; |
d99bb1db | 229 | |
c35ae179 GS |
230 | /* |
231 | * When the PHB is fenced or dead, it's pointless to collect | |
232 | * the data from PCI config space because it should return | |
233 | * 0xFF's. For ER, we still retrieve the data from the PCI | |
234 | * config space. | |
78954700 GS |
235 | * |
236 | * For pHyp, we have to enable IO for log retrieval. Otherwise, | |
237 | * 0xFF's is always returned from PCI config space. | |
c35ae179 | 238 | */ |
9e049375 | 239 | if (!(pe->type & EEH_PE_PHB)) { |
78954700 GS |
240 | if (eeh_probe_mode_devtree()) |
241 | eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); | |
c35ae179 GS |
242 | eeh_ops->configure_bridge(pe); |
243 | eeh_pe_restore_bars(pe); | |
244 | ||
245 | pci_regs_buf[0] = 0; | |
9feed42e | 246 | eeh_pe_for_each_dev(pe, edev, tmp) { |
c35ae179 GS |
247 | loglen += eeh_gather_pci_data(edev, pci_regs_buf + loglen, |
248 | EEH_PCI_REGS_LOG_LEN - loglen); | |
249 | } | |
250 | } | |
ff477966 GS |
251 | |
252 | eeh_ops->get_log(pe, severity, pci_regs_buf, loglen); | |
d99bb1db LV |
253 | } |
254 | ||
1da177e4 | 255 | /** |
cb3bc9d0 GS |
256 | * eeh_token_to_phys - Convert EEH address token to phys address |
257 | * @token: I/O token, should be address in the form 0xA.... | |
258 | * | |
259 | * This routine should be called to convert virtual I/O address | |
260 | * to physical one. | |
1da177e4 LT |
261 | */ |
262 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
263 | { | |
264 | pte_t *ptep; | |
265 | unsigned long pa; | |
12bc9f6f | 266 | int hugepage_shift; |
1da177e4 | 267 | |
12bc9f6f AK |
268 | /* |
269 | * We won't find hugepages here, iomem | |
270 | */ | |
271 | ptep = find_linux_pte_or_hugepte(init_mm.pgd, token, &hugepage_shift); | |
1da177e4 LT |
272 | if (!ptep) |
273 | return token; | |
12bc9f6f | 274 | WARN_ON(hugepage_shift); |
1da177e4 LT |
275 | pa = pte_pfn(*ptep) << PAGE_SHIFT; |
276 | ||
277 | return pa | (token & (PAGE_SIZE-1)); | |
278 | } | |
279 | ||
b95cd2cd GS |
280 | /* |
281 | * On PowerNV platform, we might already have fenced PHB there. | |
282 | * For that case, it's meaningless to recover frozen PE. Intead, | |
283 | * We have to handle fenced PHB firstly. | |
284 | */ | |
285 | static int eeh_phb_check_failure(struct eeh_pe *pe) | |
286 | { | |
287 | struct eeh_pe *phb_pe; | |
288 | unsigned long flags; | |
289 | int ret; | |
290 | ||
291 | if (!eeh_probe_mode_dev()) | |
292 | return -EPERM; | |
293 | ||
294 | /* Find the PHB PE */ | |
295 | phb_pe = eeh_phb_pe_get(pe->phb); | |
296 | if (!phb_pe) { | |
297 | pr_warning("%s Can't find PE for PHB#%d\n", | |
298 | __func__, pe->phb->global_number); | |
299 | return -EEXIST; | |
300 | } | |
301 | ||
302 | /* If the PHB has been in problematic state */ | |
303 | eeh_serialize_lock(&flags); | |
9e049375 | 304 | if (phb_pe->state & EEH_PE_ISOLATED) { |
b95cd2cd GS |
305 | ret = 0; |
306 | goto out; | |
307 | } | |
308 | ||
309 | /* Check PHB state */ | |
310 | ret = eeh_ops->get_state(phb_pe, NULL); | |
311 | if ((ret < 0) || | |
312 | (ret == EEH_STATE_NOT_SUPPORT) || | |
313 | (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) == | |
314 | (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) { | |
315 | ret = 0; | |
316 | goto out; | |
317 | } | |
318 | ||
319 | /* Isolate the PHB and send event */ | |
320 | eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED); | |
321 | eeh_serialize_unlock(flags); | |
b95cd2cd | 322 | |
56ca4fde GS |
323 | pr_err("EEH: PHB#%x failure detected\n", |
324 | phb_pe->phb->global_number); | |
325 | dump_stack(); | |
5293bf97 | 326 | eeh_send_failure_event(phb_pe); |
b95cd2cd GS |
327 | |
328 | return 1; | |
329 | out: | |
330 | eeh_serialize_unlock(flags); | |
331 | return ret; | |
332 | } | |
333 | ||
1da177e4 | 334 | /** |
f8f7d63f GS |
335 | * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze |
336 | * @edev: eeh device | |
1da177e4 LT |
337 | * |
338 | * Check for an EEH failure for the given device node. Call this | |
339 | * routine if the result of a read was all 0xff's and you want to | |
340 | * find out if this is due to an EEH slot freeze. This routine | |
341 | * will query firmware for the EEH status. | |
342 | * | |
343 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 344 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
345 | * |
346 | * It is safe to call this routine in an interrupt context. | |
347 | */ | |
f8f7d63f | 348 | int eeh_dev_check_failure(struct eeh_dev *edev) |
1da177e4 LT |
349 | { |
350 | int ret; | |
1da177e4 | 351 | unsigned long flags; |
f8f7d63f GS |
352 | struct device_node *dn; |
353 | struct pci_dev *dev; | |
66523d9f | 354 | struct eeh_pe *pe; |
fd761fd8 | 355 | int rc = 0; |
f36c5227 | 356 | const char *location; |
1da177e4 | 357 | |
e575f8db | 358 | eeh_stats.total_mmio_ffs++; |
1da177e4 | 359 | |
2ec5a0ad | 360 | if (!eeh_enabled()) |
1da177e4 LT |
361 | return 0; |
362 | ||
f8f7d63f | 363 | if (!edev) { |
e575f8db | 364 | eeh_stats.no_dn++; |
1da177e4 | 365 | return 0; |
177bc936 | 366 | } |
f8f7d63f GS |
367 | dn = eeh_dev_to_of_node(edev); |
368 | dev = eeh_dev_to_pci_dev(edev); | |
66523d9f | 369 | pe = edev->pe; |
1da177e4 LT |
370 | |
371 | /* Access to IO BARs might get this far and still not want checking. */ | |
66523d9f | 372 | if (!pe) { |
e575f8db | 373 | eeh_stats.ignored_check++; |
66523d9f GS |
374 | pr_debug("EEH: Ignored check for %s %s\n", |
375 | eeh_pci_name(dev), dn->full_name); | |
1da177e4 LT |
376 | return 0; |
377 | } | |
378 | ||
66523d9f | 379 | if (!pe->addr && !pe->config_addr) { |
e575f8db | 380 | eeh_stats.no_cfg_addr++; |
1da177e4 LT |
381 | return 0; |
382 | } | |
383 | ||
b95cd2cd GS |
384 | /* |
385 | * On PowerNV platform, we might already have fenced PHB | |
386 | * there and we need take care of that firstly. | |
387 | */ | |
388 | ret = eeh_phb_check_failure(pe); | |
389 | if (ret > 0) | |
390 | return ret; | |
391 | ||
fd761fd8 LV |
392 | /* If we already have a pending isolation event for this |
393 | * slot, we know it's bad already, we don't need to check. | |
394 | * Do this checking under a lock; as multiple PCI devices | |
395 | * in one slot might report errors simultaneously, and we | |
396 | * only want one error recovery routine running. | |
1da177e4 | 397 | */ |
4907581d | 398 | eeh_serialize_lock(&flags); |
fd761fd8 | 399 | rc = 1; |
66523d9f GS |
400 | if (pe->state & EEH_PE_ISOLATED) { |
401 | pe->check_count++; | |
402 | if (pe->check_count % EEH_MAX_FAILS == 0) { | |
f36c5227 | 403 | location = of_get_property(dn, "ibm,loc-code", NULL); |
cb3bc9d0 | 404 | printk(KERN_ERR "EEH: %d reads ignored for recovering device at " |
f36c5227 | 405 | "location=%s driver=%s pci addr=%s\n", |
66523d9f | 406 | pe->check_count, location, |
778a785f | 407 | eeh_driver_name(dev), eeh_pci_name(dev)); |
cb3bc9d0 | 408 | printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n", |
778a785f | 409 | eeh_driver_name(dev)); |
5c1344e9 | 410 | dump_stack(); |
1da177e4 | 411 | } |
fd761fd8 | 412 | goto dn_unlock; |
1da177e4 LT |
413 | } |
414 | ||
415 | /* | |
416 | * Now test for an EEH failure. This is VERY expensive. | |
417 | * Note that the eeh_config_addr may be a parent device | |
418 | * in the case of a device behind a bridge, or it may be | |
419 | * function zero of a multi-function device. | |
420 | * In any case they must share a common PHB. | |
421 | */ | |
66523d9f | 422 | ret = eeh_ops->get_state(pe, NULL); |
76e6faf7 | 423 | |
39d16e29 | 424 | /* Note that config-io to empty slots may fail; |
cb3bc9d0 | 425 | * they are empty when they don't have children. |
eb594a47 GS |
426 | * We will punt with the following conditions: Failure to get |
427 | * PE's state, EEH not support and Permanently unavailable | |
428 | * state, PE is in good state. | |
cb3bc9d0 | 429 | */ |
eb594a47 GS |
430 | if ((ret < 0) || |
431 | (ret == EEH_STATE_NOT_SUPPORT) || | |
432 | (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) == | |
433 | (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) { | |
e575f8db | 434 | eeh_stats.false_positives++; |
66523d9f | 435 | pe->false_positives++; |
fd761fd8 LV |
436 | rc = 0; |
437 | goto dn_unlock; | |
76e6faf7 LV |
438 | } |
439 | ||
e575f8db | 440 | eeh_stats.slot_resets++; |
a84f273c | 441 | |
fd761fd8 LV |
442 | /* Avoid repeated reports of this failure, including problems |
443 | * with other functions on this device, and functions under | |
cb3bc9d0 GS |
444 | * bridges. |
445 | */ | |
66523d9f | 446 | eeh_pe_state_mark(pe, EEH_PE_ISOLATED); |
4907581d | 447 | eeh_serialize_unlock(flags); |
1da177e4 | 448 | |
1da177e4 LT |
449 | /* Most EEH events are due to device driver bugs. Having |
450 | * a stack trace will help the device-driver authors figure | |
cb3bc9d0 GS |
451 | * out what happened. So print that out. |
452 | */ | |
56ca4fde GS |
453 | pr_err("EEH: Frozen PE#%x detected on PHB#%x\n", |
454 | pe->addr, pe->phb->global_number); | |
455 | dump_stack(); | |
456 | ||
5293bf97 GS |
457 | eeh_send_failure_event(pe); |
458 | ||
fd761fd8 LV |
459 | return 1; |
460 | ||
461 | dn_unlock: | |
4907581d | 462 | eeh_serialize_unlock(flags); |
fd761fd8 | 463 | return rc; |
1da177e4 LT |
464 | } |
465 | ||
f8f7d63f | 466 | EXPORT_SYMBOL_GPL(eeh_dev_check_failure); |
1da177e4 LT |
467 | |
468 | /** | |
cb3bc9d0 GS |
469 | * eeh_check_failure - Check if all 1's data is due to EEH slot freeze |
470 | * @token: I/O token, should be address in the form 0xA.... | |
471 | * @val: value, should be all 1's (XXX why do we need this arg??) | |
1da177e4 | 472 | * |
1da177e4 LT |
473 | * Check for an EEH failure at the given token address. Call this |
474 | * routine if the result of a read was all 0xff's and you want to | |
475 | * find out if this is due to an EEH slot freeze event. This routine | |
476 | * will query firmware for the EEH status. | |
477 | * | |
478 | * Note this routine is safe to call in an interrupt context. | |
479 | */ | |
480 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
481 | { | |
482 | unsigned long addr; | |
f8f7d63f | 483 | struct eeh_dev *edev; |
1da177e4 LT |
484 | |
485 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
486 | addr = eeh_token_to_phys((unsigned long __force) token); | |
3ab96a02 | 487 | edev = eeh_addr_cache_get_dev(addr); |
f8f7d63f | 488 | if (!edev) { |
e575f8db | 489 | eeh_stats.no_device++; |
1da177e4 | 490 | return val; |
177bc936 | 491 | } |
1da177e4 | 492 | |
f8f7d63f | 493 | eeh_dev_check_failure(edev); |
1da177e4 LT |
494 | return val; |
495 | } | |
496 | ||
497 | EXPORT_SYMBOL(eeh_check_failure); | |
498 | ||
6dee3fb9 | 499 | |
47b5c838 | 500 | /** |
cce4b2d2 | 501 | * eeh_pci_enable - Enable MMIO or DMA transfers for this slot |
ff477966 | 502 | * @pe: EEH PE |
cb3bc9d0 GS |
503 | * |
504 | * This routine should be called to reenable frozen MMIO or DMA | |
505 | * so that it would work correctly again. It's useful while doing | |
506 | * recovery or log collection on the indicated device. | |
47b5c838 | 507 | */ |
ff477966 | 508 | int eeh_pci_enable(struct eeh_pe *pe, int function) |
47b5c838 | 509 | { |
78954700 GS |
510 | int rc, flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
511 | ||
512 | /* | |
513 | * pHyp doesn't allow to enable IO or DMA on unfrozen PE. | |
514 | * Also, it's pointless to enable them on unfrozen PE. So | |
515 | * we have the check here. | |
516 | */ | |
517 | if (function == EEH_OPT_THAW_MMIO || | |
518 | function == EEH_OPT_THAW_DMA) { | |
519 | rc = eeh_ops->get_state(pe, NULL); | |
520 | if (rc < 0) | |
521 | return rc; | |
522 | ||
523 | /* Needn't to enable or already enabled */ | |
524 | if ((rc == EEH_STATE_NOT_SUPPORT) || | |
525 | ((rc & flags) == flags)) | |
526 | return 0; | |
527 | } | |
47b5c838 | 528 | |
ff477966 | 529 | rc = eeh_ops->set_option(pe, function); |
47b5c838 | 530 | if (rc) |
78954700 GS |
531 | pr_warn("%s: Unexpected state change %d on " |
532 | "PHB#%d-PE#%x, err=%d\n", | |
533 | __func__, function, pe->phb->global_number, | |
534 | pe->addr, rc); | |
47b5c838 | 535 | |
ff477966 | 536 | rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); |
78954700 GS |
537 | if (rc <= 0) |
538 | return rc; | |
539 | ||
540 | if ((function == EEH_OPT_THAW_MMIO) && | |
541 | (rc & EEH_STATE_MMIO_ENABLED)) | |
542 | return 0; | |
543 | ||
544 | if ((function == EEH_OPT_THAW_DMA) && | |
545 | (rc & EEH_STATE_DMA_ENABLED)) | |
fa1be476 LV |
546 | return 0; |
547 | ||
47b5c838 LV |
548 | return rc; |
549 | } | |
550 | ||
00c2ae35 BK |
551 | /** |
552 | * pcibios_set_pcie_slot_reset - Set PCI-E reset state | |
cb3bc9d0 GS |
553 | * @dev: pci device struct |
554 | * @state: reset state to enter | |
00c2ae35 BK |
555 | * |
556 | * Return value: | |
557 | * 0 if success | |
cb3bc9d0 | 558 | */ |
00c2ae35 BK |
559 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) |
560 | { | |
c270a24c GS |
561 | struct eeh_dev *edev = pci_dev_to_eeh_dev(dev); |
562 | struct eeh_pe *pe = edev->pe; | |
563 | ||
564 | if (!pe) { | |
565 | pr_err("%s: No PE found on PCI device %s\n", | |
566 | __func__, pci_name(dev)); | |
567 | return -EINVAL; | |
568 | } | |
00c2ae35 BK |
569 | |
570 | switch (state) { | |
571 | case pcie_deassert_reset: | |
c270a24c | 572 | eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); |
00c2ae35 BK |
573 | break; |
574 | case pcie_hot_reset: | |
c270a24c | 575 | eeh_ops->reset(pe, EEH_RESET_HOT); |
00c2ae35 BK |
576 | break; |
577 | case pcie_warm_reset: | |
c270a24c | 578 | eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); |
00c2ae35 BK |
579 | break; |
580 | default: | |
581 | return -EINVAL; | |
582 | }; | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
cb5b5624 | 587 | /** |
c270a24c GS |
588 | * eeh_set_pe_freset - Check the required reset for the indicated device |
589 | * @data: EEH device | |
590 | * @flag: return value | |
cb3bc9d0 GS |
591 | * |
592 | * Each device might have its preferred reset type: fundamental or | |
593 | * hot reset. The routine is used to collected the information for | |
594 | * the indicated device and its children so that the bunch of the | |
595 | * devices could be reset properly. | |
596 | */ | |
c270a24c | 597 | static void *eeh_set_dev_freset(void *data, void *flag) |
cb3bc9d0 GS |
598 | { |
599 | struct pci_dev *dev; | |
c270a24c GS |
600 | unsigned int *freset = (unsigned int *)flag; |
601 | struct eeh_dev *edev = (struct eeh_dev *)data; | |
6dee3fb9 | 602 | |
c270a24c | 603 | dev = eeh_dev_to_pci_dev(edev); |
cb3bc9d0 GS |
604 | if (dev) |
605 | *freset |= dev->needs_freset; | |
606 | ||
c270a24c | 607 | return NULL; |
cb3bc9d0 GS |
608 | } |
609 | ||
610 | /** | |
cce4b2d2 | 611 | * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second |
c270a24c | 612 | * @pe: EEH PE |
cb3bc9d0 GS |
613 | * |
614 | * Assert the PCI #RST line for 1/4 second. | |
615 | */ | |
c270a24c | 616 | static void eeh_reset_pe_once(struct eeh_pe *pe) |
6dee3fb9 | 617 | { |
308fc4f8 | 618 | unsigned int freset = 0; |
6e19314c | 619 | |
308fc4f8 RL |
620 | /* Determine type of EEH reset required for |
621 | * Partitionable Endpoint, a hot-reset (1) | |
622 | * or a fundamental reset (3). | |
623 | * A fundamental reset required by any device under | |
624 | * Partitionable Endpoint trumps hot-reset. | |
a84f273c | 625 | */ |
c270a24c | 626 | eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset); |
308fc4f8 RL |
627 | |
628 | if (freset) | |
c270a24c | 629 | eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); |
6e19314c | 630 | else |
c270a24c | 631 | eeh_ops->reset(pe, EEH_RESET_HOT); |
6dee3fb9 LV |
632 | |
633 | /* The PCI bus requires that the reset be held high for at least | |
cb3bc9d0 GS |
634 | * a 100 milliseconds. We wait a bit longer 'just in case'. |
635 | */ | |
6dee3fb9 | 636 | #define PCI_BUS_RST_HOLD_TIME_MSEC 250 |
cb3bc9d0 | 637 | msleep(PCI_BUS_RST_HOLD_TIME_MSEC); |
a84f273c | 638 | |
c270a24c | 639 | eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); |
6dee3fb9 LV |
640 | |
641 | /* After a PCI slot has been reset, the PCI Express spec requires | |
642 | * a 1.5 second idle time for the bus to stabilize, before starting | |
cb3bc9d0 GS |
643 | * up traffic. |
644 | */ | |
6dee3fb9 | 645 | #define PCI_BUS_SETTLE_TIME_MSEC 1800 |
cb3bc9d0 | 646 | msleep(PCI_BUS_SETTLE_TIME_MSEC); |
e1029263 LV |
647 | } |
648 | ||
cb3bc9d0 | 649 | /** |
cce4b2d2 | 650 | * eeh_reset_pe - Reset the indicated PE |
c270a24c | 651 | * @pe: EEH PE |
cb3bc9d0 GS |
652 | * |
653 | * This routine should be called to reset indicated device, including | |
654 | * PE. A PE might include multiple PCI devices and sometimes PCI bridges | |
655 | * might be involved as well. | |
656 | */ | |
c270a24c | 657 | int eeh_reset_pe(struct eeh_pe *pe) |
e1029263 | 658 | { |
326a98ea | 659 | int flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
e1029263 LV |
660 | int i, rc; |
661 | ||
9c547768 LV |
662 | /* Take three shots at resetting the bus */ |
663 | for (i=0; i<3; i++) { | |
c270a24c | 664 | eeh_reset_pe_once(pe); |
6dee3fb9 | 665 | |
78954700 GS |
666 | /* |
667 | * EEH_PE_ISOLATED is expected to be removed after | |
668 | * BAR restore. | |
669 | */ | |
c270a24c | 670 | rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); |
78954700 | 671 | if ((rc & flags) == flags) |
b6495c0c | 672 | return 0; |
e1029263 | 673 | |
e1029263 | 674 | if (rc < 0) { |
c270a24c GS |
675 | pr_err("%s: Unrecoverable slot failure on PHB#%d-PE#%x", |
676 | __func__, pe->phb->global_number, pe->addr); | |
b6495c0c | 677 | return -1; |
e1029263 | 678 | } |
c270a24c GS |
679 | pr_err("EEH: bus reset %d failed on PHB#%d-PE#%x, rc=%d\n", |
680 | i+1, pe->phb->global_number, pe->addr, rc); | |
6dee3fb9 | 681 | } |
b6495c0c | 682 | |
9c547768 | 683 | return -1; |
6dee3fb9 LV |
684 | } |
685 | ||
8b553f32 | 686 | /** |
cb3bc9d0 | 687 | * eeh_save_bars - Save device bars |
f631acd3 | 688 | * @edev: PCI device associated EEH device |
8b553f32 LV |
689 | * |
690 | * Save the values of the device bars. Unlike the restore | |
691 | * routine, this routine is *not* recursive. This is because | |
31116f0b | 692 | * PCI devices are added individually; but, for the restore, |
8b553f32 LV |
693 | * an entire slot is reset at a time. |
694 | */ | |
d7bb8862 | 695 | void eeh_save_bars(struct eeh_dev *edev) |
8b553f32 LV |
696 | { |
697 | int i; | |
f631acd3 | 698 | struct device_node *dn; |
8b553f32 | 699 | |
f631acd3 | 700 | if (!edev) |
8b553f32 | 701 | return; |
f631acd3 | 702 | dn = eeh_dev_to_of_node(edev); |
a84f273c | 703 | |
8b553f32 | 704 | for (i = 0; i < 16; i++) |
3780444c | 705 | eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]); |
bf898ec5 GS |
706 | |
707 | /* | |
708 | * For PCI bridges including root port, we need enable bus | |
709 | * master explicitly. Otherwise, it can't fetch IODA table | |
710 | * entries correctly. So we cache the bit in advance so that | |
711 | * we can restore it after reset, either PHB range or PE range. | |
712 | */ | |
713 | if (edev->mode & EEH_DEV_BRIDGE) | |
714 | edev->config_space[1] |= PCI_COMMAND_MASTER; | |
8b553f32 LV |
715 | } |
716 | ||
aa1e6374 GS |
717 | /** |
718 | * eeh_ops_register - Register platform dependent EEH operations | |
719 | * @ops: platform dependent EEH operations | |
720 | * | |
721 | * Register the platform dependent EEH operation callback | |
722 | * functions. The platform should call this function before | |
723 | * any other EEH operations. | |
724 | */ | |
725 | int __init eeh_ops_register(struct eeh_ops *ops) | |
726 | { | |
727 | if (!ops->name) { | |
728 | pr_warning("%s: Invalid EEH ops name for %p\n", | |
729 | __func__, ops); | |
730 | return -EINVAL; | |
731 | } | |
732 | ||
733 | if (eeh_ops && eeh_ops != ops) { | |
734 | pr_warning("%s: EEH ops of platform %s already existing (%s)\n", | |
735 | __func__, eeh_ops->name, ops->name); | |
736 | return -EEXIST; | |
737 | } | |
738 | ||
739 | eeh_ops = ops; | |
740 | ||
741 | return 0; | |
742 | } | |
743 | ||
744 | /** | |
745 | * eeh_ops_unregister - Unreigster platform dependent EEH operations | |
746 | * @name: name of EEH platform operations | |
747 | * | |
748 | * Unregister the platform dependent EEH operation callback | |
749 | * functions. | |
750 | */ | |
751 | int __exit eeh_ops_unregister(const char *name) | |
752 | { | |
753 | if (!name || !strlen(name)) { | |
754 | pr_warning("%s: Invalid EEH ops name\n", | |
755 | __func__); | |
756 | return -EINVAL; | |
757 | } | |
758 | ||
759 | if (eeh_ops && !strcmp(eeh_ops->name, name)) { | |
760 | eeh_ops = NULL; | |
761 | return 0; | |
762 | } | |
763 | ||
764 | return -EEXIST; | |
765 | } | |
766 | ||
66f9af83 GS |
767 | static int eeh_reboot_notifier(struct notifier_block *nb, |
768 | unsigned long action, void *unused) | |
769 | { | |
770 | eeh_set_enable(false); | |
771 | return NOTIFY_DONE; | |
772 | } | |
773 | ||
774 | static struct notifier_block eeh_reboot_nb = { | |
775 | .notifier_call = eeh_reboot_notifier, | |
776 | }; | |
777 | ||
cb3bc9d0 GS |
778 | /** |
779 | * eeh_init - EEH initialization | |
780 | * | |
1da177e4 LT |
781 | * Initialize EEH by trying to enable it for all of the adapters in the system. |
782 | * As a side effect we can determine here if eeh is supported at all. | |
783 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
784 | * check. If a user turns off EEH for a particular adapter they are really | |
785 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
786 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
787 | * EEH for all slots/all devices. | |
788 | * | |
789 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
790 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
791 | * newer systems can boot. | |
792 | */ | |
eeb6361f | 793 | int eeh_init(void) |
1da177e4 | 794 | { |
1a5c2e63 GS |
795 | struct pci_controller *hose, *tmp; |
796 | struct device_node *phb; | |
51fb5f56 GS |
797 | static int cnt = 0; |
798 | int ret = 0; | |
799 | ||
800 | /* | |
801 | * We have to delay the initialization on PowerNV after | |
802 | * the PCI hierarchy tree has been built because the PEs | |
803 | * are figured out based on PCI devices instead of device | |
804 | * tree nodes | |
805 | */ | |
806 | if (machine_is(powernv) && cnt++ <= 0) | |
807 | return ret; | |
e2af155c | 808 | |
66f9af83 GS |
809 | /* Register reboot notifier */ |
810 | ret = register_reboot_notifier(&eeh_reboot_nb); | |
811 | if (ret) { | |
812 | pr_warn("%s: Failed to register notifier (%d)\n", | |
813 | __func__, ret); | |
814 | return ret; | |
815 | } | |
816 | ||
e2af155c GS |
817 | /* call platform initialization function */ |
818 | if (!eeh_ops) { | |
819 | pr_warning("%s: Platform EEH operation not found\n", | |
820 | __func__); | |
35e5cfe2 | 821 | return -EEXIST; |
e2af155c GS |
822 | } else if ((ret = eeh_ops->init())) { |
823 | pr_warning("%s: Failed to call platform init function (%d)\n", | |
824 | __func__, ret); | |
35e5cfe2 | 825 | return ret; |
e2af155c | 826 | } |
1da177e4 | 827 | |
c8608558 GS |
828 | /* Initialize EEH event */ |
829 | ret = eeh_event_init(); | |
830 | if (ret) | |
831 | return ret; | |
832 | ||
1a5c2e63 | 833 | /* Enable EEH for all adapters */ |
d7bb8862 GS |
834 | if (eeh_probe_mode_devtree()) { |
835 | list_for_each_entry_safe(hose, tmp, | |
836 | &hose_list, list_node) { | |
837 | phb = hose->dn; | |
838 | traverse_pci_devices(phb, eeh_ops->of_probe, NULL); | |
839 | } | |
51fb5f56 GS |
840 | } else if (eeh_probe_mode_dev()) { |
841 | list_for_each_entry_safe(hose, tmp, | |
842 | &hose_list, list_node) | |
843 | pci_walk_bus(hose->bus, eeh_ops->dev_probe, NULL); | |
844 | } else { | |
845 | pr_warning("%s: Invalid probe mode %d\n", | |
846 | __func__, eeh_probe_mode); | |
847 | return -EINVAL; | |
1da177e4 LT |
848 | } |
849 | ||
21fd21f5 GS |
850 | /* |
851 | * Call platform post-initialization. Actually, It's good chance | |
852 | * to inform platform that EEH is ready to supply service if the | |
853 | * I/O cache stuff has been built up. | |
854 | */ | |
855 | if (eeh_ops->post_init) { | |
856 | ret = eeh_ops->post_init(); | |
857 | if (ret) | |
858 | return ret; | |
859 | } | |
860 | ||
2ec5a0ad | 861 | if (eeh_enabled()) |
d7bb8862 | 862 | pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n"); |
1da177e4 | 863 | else |
d7bb8862 | 864 | pr_warning("EEH: No capable adapters found\n"); |
35e5cfe2 GS |
865 | |
866 | return ret; | |
1da177e4 LT |
867 | } |
868 | ||
35e5cfe2 GS |
869 | core_initcall_sync(eeh_init); |
870 | ||
1da177e4 | 871 | /** |
cb3bc9d0 | 872 | * eeh_add_device_early - Enable EEH for the indicated device_node |
1da177e4 LT |
873 | * @dn: device node for which to set up EEH |
874 | * | |
875 | * This routine must be used to perform EEH initialization for PCI | |
876 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
877 | * This routine must be called before any i/o is performed to the | |
878 | * adapter (inluding any config-space i/o). | |
879 | * Whether this actually enables EEH or not for this device depends | |
880 | * on the CEC architecture, type of the device, on earlier boot | |
881 | * command-line arguments & etc. | |
882 | */ | |
f2856491 | 883 | void eeh_add_device_early(struct device_node *dn) |
1da177e4 LT |
884 | { |
885 | struct pci_controller *phb; | |
1da177e4 | 886 | |
26a74850 GS |
887 | /* |
888 | * If we're doing EEH probe based on PCI device, we | |
889 | * would delay the probe until late stage because | |
890 | * the PCI device isn't available this moment. | |
891 | */ | |
892 | if (!eeh_probe_mode_devtree()) | |
893 | return; | |
894 | ||
1e38b714 | 895 | if (!of_node_to_eeh_dev(dn)) |
1da177e4 | 896 | return; |
f631acd3 | 897 | phb = of_node_to_eeh_dev(dn)->phb; |
f751f841 LV |
898 | |
899 | /* USB Bus children of PCI devices will not have BUID's */ | |
900 | if (NULL == phb || 0 == phb->buid) | |
1da177e4 | 901 | return; |
1da177e4 | 902 | |
d7bb8862 | 903 | eeh_ops->of_probe(dn, NULL); |
1da177e4 | 904 | } |
1da177e4 | 905 | |
cb3bc9d0 GS |
906 | /** |
907 | * eeh_add_device_tree_early - Enable EEH for the indicated device | |
908 | * @dn: device node | |
909 | * | |
910 | * This routine must be used to perform EEH initialization for the | |
911 | * indicated PCI device that was added after system boot (e.g. | |
912 | * hotplug, dlpar). | |
913 | */ | |
e2a296ee LV |
914 | void eeh_add_device_tree_early(struct device_node *dn) |
915 | { | |
916 | struct device_node *sib; | |
acaa6176 SR |
917 | |
918 | for_each_child_of_node(dn, sib) | |
e2a296ee LV |
919 | eeh_add_device_tree_early(sib); |
920 | eeh_add_device_early(dn); | |
921 | } | |
922 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
923 | ||
1da177e4 | 924 | /** |
cb3bc9d0 | 925 | * eeh_add_device_late - Perform EEH initialization for the indicated pci device |
1da177e4 LT |
926 | * @dev: pci device for which to set up EEH |
927 | * | |
928 | * This routine must be used to complete EEH initialization for PCI | |
929 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
930 | */ | |
f2856491 | 931 | void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 932 | { |
56b0fca3 | 933 | struct device_node *dn; |
f631acd3 | 934 | struct eeh_dev *edev; |
56b0fca3 | 935 | |
2ec5a0ad | 936 | if (!dev || !eeh_enabled()) |
1da177e4 LT |
937 | return; |
938 | ||
57b066ff | 939 | pr_debug("EEH: Adding device %s\n", pci_name(dev)); |
1da177e4 | 940 | |
56b0fca3 | 941 | dn = pci_device_to_OF_node(dev); |
2ef822c5 | 942 | edev = of_node_to_eeh_dev(dn); |
f631acd3 | 943 | if (edev->pdev == dev) { |
57b066ff BH |
944 | pr_debug("EEH: Already referenced !\n"); |
945 | return; | |
946 | } | |
f5c57710 GS |
947 | |
948 | /* | |
949 | * The EEH cache might not be removed correctly because of | |
950 | * unbalanced kref to the device during unplug time, which | |
951 | * relies on pcibios_release_device(). So we have to remove | |
952 | * that here explicitly. | |
953 | */ | |
954 | if (edev->pdev) { | |
955 | eeh_rmv_from_parent_pe(edev); | |
956 | eeh_addr_cache_rmv_dev(edev->pdev); | |
957 | eeh_sysfs_remove_device(edev->pdev); | |
ab55d218 | 958 | edev->mode &= ~EEH_DEV_SYSFS; |
f5c57710 | 959 | |
f26c7a03 GS |
960 | /* |
961 | * We definitely should have the PCI device removed | |
962 | * though it wasn't correctly. So we needn't call | |
963 | * into error handler afterwards. | |
964 | */ | |
965 | edev->mode |= EEH_DEV_NO_HANDLER; | |
966 | ||
f5c57710 GS |
967 | edev->pdev = NULL; |
968 | dev->dev.archdata.edev = NULL; | |
969 | } | |
57b066ff | 970 | |
f631acd3 GS |
971 | edev->pdev = dev; |
972 | dev->dev.archdata.edev = edev; | |
56b0fca3 | 973 | |
26a74850 GS |
974 | /* |
975 | * We have to do the EEH probe here because the PCI device | |
976 | * hasn't been created yet in the early stage. | |
977 | */ | |
978 | if (eeh_probe_mode_dev()) | |
979 | eeh_ops->dev_probe(dev, NULL); | |
980 | ||
3ab96a02 | 981 | eeh_addr_cache_insert_dev(dev); |
1da177e4 | 982 | } |
794e085e | 983 | |
cb3bc9d0 GS |
984 | /** |
985 | * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus | |
986 | * @bus: PCI bus | |
987 | * | |
988 | * This routine must be used to perform EEH initialization for PCI | |
989 | * devices which are attached to the indicated PCI bus. The PCI bus | |
990 | * is added after system boot through hotplug or dlpar. | |
991 | */ | |
794e085e NF |
992 | void eeh_add_device_tree_late(struct pci_bus *bus) |
993 | { | |
994 | struct pci_dev *dev; | |
995 | ||
996 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
a84f273c GS |
997 | eeh_add_device_late(dev); |
998 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
999 | struct pci_bus *subbus = dev->subordinate; | |
1000 | if (subbus) | |
1001 | eeh_add_device_tree_late(subbus); | |
1002 | } | |
794e085e NF |
1003 | } |
1004 | } | |
1005 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 | 1006 | |
6a040ce7 TLSC |
1007 | /** |
1008 | * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus | |
1009 | * @bus: PCI bus | |
1010 | * | |
1011 | * This routine must be used to add EEH sysfs files for PCI | |
1012 | * devices which are attached to the indicated PCI bus. The PCI bus | |
1013 | * is added after system boot through hotplug or dlpar. | |
1014 | */ | |
1015 | void eeh_add_sysfs_files(struct pci_bus *bus) | |
1016 | { | |
1017 | struct pci_dev *dev; | |
1018 | ||
1019 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1020 | eeh_sysfs_add_device(dev); | |
1021 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1022 | struct pci_bus *subbus = dev->subordinate; | |
1023 | if (subbus) | |
1024 | eeh_add_sysfs_files(subbus); | |
1025 | } | |
1026 | } | |
1027 | } | |
1028 | EXPORT_SYMBOL_GPL(eeh_add_sysfs_files); | |
1029 | ||
1da177e4 | 1030 | /** |
cb3bc9d0 | 1031 | * eeh_remove_device - Undo EEH setup for the indicated pci device |
1da177e4 LT |
1032 | * @dev: pci device to be removed |
1033 | * | |
794e085e NF |
1034 | * This routine should be called when a device is removed from |
1035 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
1036 | * the PCI device from the EEH subsystem. I/O errors affecting | |
1037 | * this device will no longer be detected after this call; thus, | |
1038 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 1039 | */ |
807a827d | 1040 | void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 1041 | { |
f631acd3 GS |
1042 | struct eeh_dev *edev; |
1043 | ||
2ec5a0ad | 1044 | if (!dev || !eeh_enabled()) |
1da177e4 | 1045 | return; |
f631acd3 | 1046 | edev = pci_dev_to_eeh_dev(dev); |
1da177e4 LT |
1047 | |
1048 | /* Unregister the device with the EEH/PCI address search system */ | |
57b066ff | 1049 | pr_debug("EEH: Removing device %s\n", pci_name(dev)); |
56b0fca3 | 1050 | |
f5c57710 | 1051 | if (!edev || !edev->pdev || !edev->pe) { |
57b066ff BH |
1052 | pr_debug("EEH: Not referenced !\n"); |
1053 | return; | |
b055a9e1 | 1054 | } |
f5c57710 GS |
1055 | |
1056 | /* | |
1057 | * During the hotplug for EEH error recovery, we need the EEH | |
1058 | * device attached to the parent PE in order for BAR restore | |
1059 | * a bit later. So we keep it for BAR restore and remove it | |
1060 | * from the parent PE during the BAR resotre. | |
1061 | */ | |
f631acd3 GS |
1062 | edev->pdev = NULL; |
1063 | dev->dev.archdata.edev = NULL; | |
f5c57710 GS |
1064 | if (!(edev->pe->state & EEH_PE_KEEP)) |
1065 | eeh_rmv_from_parent_pe(edev); | |
1066 | else | |
1067 | edev->mode |= EEH_DEV_DISCONNECTED; | |
57b066ff | 1068 | |
f26c7a03 GS |
1069 | /* |
1070 | * We're removing from the PCI subsystem, that means | |
1071 | * the PCI device driver can't support EEH or not | |
1072 | * well. So we rely on hotplug completely to do recovery | |
1073 | * for the specific PCI device. | |
1074 | */ | |
1075 | edev->mode |= EEH_DEV_NO_HANDLER; | |
1076 | ||
3ab96a02 | 1077 | eeh_addr_cache_rmv_dev(dev); |
57b066ff | 1078 | eeh_sysfs_remove_device(dev); |
ab55d218 | 1079 | edev->mode &= ~EEH_DEV_SYSFS; |
1da177e4 | 1080 | } |
1da177e4 LT |
1081 | |
1082 | static int proc_eeh_show(struct seq_file *m, void *v) | |
1083 | { | |
2ec5a0ad | 1084 | if (!eeh_enabled()) { |
1da177e4 | 1085 | seq_printf(m, "EEH Subsystem is globally disabled\n"); |
e575f8db | 1086 | seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs); |
1da177e4 LT |
1087 | } else { |
1088 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 | 1089 | seq_printf(m, |
e575f8db GS |
1090 | "no device=%llu\n" |
1091 | "no device node=%llu\n" | |
1092 | "no config address=%llu\n" | |
1093 | "check not wanted=%llu\n" | |
1094 | "eeh_total_mmio_ffs=%llu\n" | |
1095 | "eeh_false_positives=%llu\n" | |
1096 | "eeh_slot_resets=%llu\n", | |
1097 | eeh_stats.no_device, | |
1098 | eeh_stats.no_dn, | |
1099 | eeh_stats.no_cfg_addr, | |
1100 | eeh_stats.ignored_check, | |
1101 | eeh_stats.total_mmio_ffs, | |
1102 | eeh_stats.false_positives, | |
1103 | eeh_stats.slot_resets); | |
1da177e4 LT |
1104 | } |
1105 | ||
1106 | return 0; | |
1107 | } | |
1108 | ||
1109 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1110 | { | |
1111 | return single_open(file, proc_eeh_show, NULL); | |
1112 | } | |
1113 | ||
5dfe4c96 | 1114 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1115 | .open = proc_eeh_open, |
1116 | .read = seq_read, | |
1117 | .llseek = seq_lseek, | |
1118 | .release = single_release, | |
1119 | }; | |
1120 | ||
1121 | static int __init eeh_init_proc(void) | |
1122 | { | |
144136dd | 1123 | if (machine_is(pseries) || machine_is(powernv)) |
8feaa434 | 1124 | proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations); |
1da177e4 LT |
1125 | return 0; |
1126 | } | |
1127 | __initcall(eeh_init_proc); |