Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3c8c90ab LV |
2 | * Copyright IBM Corporation 2001, 2005, 2006 |
3 | * Copyright Dave Engebretsen & Todd Inglett 2001 | |
4 | * Copyright Linas Vepstas 2005, 2006 | |
cb3bc9d0 | 5 | * Copyright 2001-2012 IBM Corporation. |
69376502 | 6 | * |
1da177e4 LT |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
69376502 | 11 | * |
1da177e4 LT |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
69376502 | 16 | * |
1da177e4 LT |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
3c8c90ab LV |
20 | * |
21 | * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> | |
1da177e4 LT |
22 | */ |
23 | ||
6dee3fb9 | 24 | #include <linux/delay.h> |
7f52a526 | 25 | #include <linux/debugfs.h> |
cb3bc9d0 | 26 | #include <linux/sched.h> |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/list.h> | |
1da177e4 LT |
29 | #include <linux/pci.h> |
30 | #include <linux/proc_fs.h> | |
31 | #include <linux/rbtree.h> | |
66f9af83 | 32 | #include <linux/reboot.h> |
1da177e4 LT |
33 | #include <linux/seq_file.h> |
34 | #include <linux/spinlock.h> | |
66b15db6 | 35 | #include <linux/export.h> |
acaa6176 SR |
36 | #include <linux/of.h> |
37 | ||
60063497 | 38 | #include <linux/atomic.h> |
1e54b938 | 39 | #include <asm/debug.h> |
1da177e4 | 40 | #include <asm/eeh.h> |
172ca926 | 41 | #include <asm/eeh_event.h> |
1da177e4 LT |
42 | #include <asm/io.h> |
43 | #include <asm/machdep.h> | |
172ca926 | 44 | #include <asm/ppc-pci.h> |
1da177e4 | 45 | #include <asm/rtas.h> |
1da177e4 | 46 | |
1da177e4 LT |
47 | |
48 | /** Overview: | |
49 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
50 | * dealing with PCI bus errors that can't be dealt with within the | |
51 | * usual PCI framework, except by check-stopping the CPU. Systems | |
52 | * that are designed for high-availability/reliability cannot afford | |
53 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
54 | * An EEH-capable bridge operates by converting a detected error | |
55 | * into a "slot freeze", taking the PCI adapter off-line, making | |
56 | * the slot behave, from the OS'es point of view, as if the slot | |
57 | * were "empty": all reads return 0xff's and all writes are silently | |
58 | * ignored. EEH slot isolation events can be triggered by parity | |
59 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
60 | * which in turn might be caused by low voltage on the bus, dust, |
61 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
62 | * |
63 | * Note, however, that one of the leading causes of EEH slot | |
64 | * freeze events are buggy device drivers, buggy device microcode, | |
65 | * or buggy device hardware. This is because any attempt by the | |
66 | * device to bus-master data to a memory address that is not | |
67 | * assigned to the device will trigger a slot freeze. (The idea | |
68 | * is to prevent devices-gone-wild from corrupting system memory). | |
69 | * Buggy hardware/drivers will have a miserable time co-existing | |
70 | * with EEH. | |
71 | * | |
72 | * Ideally, a PCI device driver, when suspecting that an isolation | |
25985edc | 73 | * event has occurred (e.g. by reading 0xff's), will then ask EEH |
1da177e4 LT |
74 | * whether this is the case, and then take appropriate steps to |
75 | * reset the PCI slot, the PCI device, and then resume operations. | |
76 | * However, until that day, the checking is done here, with the | |
77 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
78 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
79 | * and sent out for processing. | |
80 | */ | |
81 | ||
5c1344e9 | 82 | /* If a device driver keeps reading an MMIO register in an interrupt |
f36c5227 MM |
83 | * handler after a slot isolation event, it might be broken. |
84 | * This sets the threshold for how many read attempts we allow | |
85 | * before printing an error message. | |
1da177e4 | 86 | */ |
2fd30be8 | 87 | #define EEH_MAX_FAILS 2100000 |
1da177e4 | 88 | |
17213c3b | 89 | /* Time to wait for a PCI slot to report status, in milliseconds */ |
fb48dc22 | 90 | #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000) |
9c547768 | 91 | |
d7bb8862 | 92 | /* |
8a5ad356 GS |
93 | * EEH probe mode support, which is part of the flags, |
94 | * is to support multiple platforms for EEH. Some platforms | |
95 | * like pSeries do PCI emunation based on device tree. | |
96 | * However, other platforms like powernv probe PCI devices | |
97 | * from hardware. The flag is used to distinguish that. | |
98 | * In addition, struct eeh_ops::probe would be invoked for | |
99 | * particular OF node or PCI device so that the corresponding | |
100 | * PE would be created there. | |
d7bb8862 | 101 | */ |
8a5ad356 GS |
102 | int eeh_subsystem_flags; |
103 | EXPORT_SYMBOL(eeh_subsystem_flags); | |
104 | ||
105 | /* Platform dependent EEH operations */ | |
106 | struct eeh_ops *eeh_ops = NULL; | |
d7bb8862 | 107 | |
fd761fd8 | 108 | /* Lock to avoid races due to multiple reports of an error */ |
4907581d | 109 | DEFINE_RAW_SPINLOCK(confirm_error_lock); |
fd761fd8 | 110 | |
17213c3b LV |
111 | /* Buffer for reporting pci register dumps. Its here in BSS, and |
112 | * not dynamically alloced, so that it ends up in RMO where RTAS | |
113 | * can access it. | |
114 | */ | |
d99bb1db LV |
115 | #define EEH_PCI_REGS_LOG_LEN 4096 |
116 | static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; | |
117 | ||
e575f8db GS |
118 | /* |
119 | * The struct is used to maintain the EEH global statistic | |
120 | * information. Besides, the EEH global statistics will be | |
121 | * exported to user space through procfs | |
122 | */ | |
123 | struct eeh_stats { | |
124 | u64 no_device; /* PCI device not found */ | |
125 | u64 no_dn; /* OF node not found */ | |
126 | u64 no_cfg_addr; /* Config address not found */ | |
127 | u64 ignored_check; /* EEH check skipped */ | |
128 | u64 total_mmio_ffs; /* Total EEH checks */ | |
129 | u64 false_positives; /* Unnecessary EEH checks */ | |
130 | u64 slot_resets; /* PE reset */ | |
131 | }; | |
132 | ||
133 | static struct eeh_stats eeh_stats; | |
1da177e4 | 134 | |
7684b40c LV |
135 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
136 | ||
7f52a526 GS |
137 | static int __init eeh_setup(char *str) |
138 | { | |
139 | if (!strcmp(str, "off")) | |
140 | eeh_subsystem_flags |= EEH_FORCE_DISABLED; | |
141 | ||
142 | return 1; | |
143 | } | |
144 | __setup("eeh=", eeh_setup); | |
145 | ||
d99bb1db | 146 | /** |
cce4b2d2 | 147 | * eeh_gather_pci_data - Copy assorted PCI config space registers to buff |
f631acd3 | 148 | * @edev: device to report data for |
d99bb1db LV |
149 | * @buf: point to buffer in which to log |
150 | * @len: amount of room in buffer | |
151 | * | |
152 | * This routine captures assorted PCI configuration space data, | |
153 | * and puts them into a buffer for RTAS error logging. | |
154 | */ | |
f631acd3 | 155 | static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len) |
d99bb1db | 156 | { |
f631acd3 | 157 | struct device_node *dn = eeh_dev_to_of_node(edev); |
d99bb1db | 158 | u32 cfg; |
fcf9892b | 159 | int cap, i; |
d99bb1db LV |
160 | int n = 0; |
161 | ||
f631acd3 | 162 | n += scnprintf(buf+n, len-n, "%s\n", dn->full_name); |
2d86c385 | 163 | pr_warn("EEH: of node=%s\n", dn->full_name); |
fcf9892b | 164 | |
3780444c | 165 | eeh_ops->read_config(dn, PCI_VENDOR_ID, 4, &cfg); |
fcf9892b | 166 | n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); |
2d86c385 | 167 | pr_warn("EEH: PCI device/vendor: %08x\n", cfg); |
fcf9892b | 168 | |
3780444c | 169 | eeh_ops->read_config(dn, PCI_COMMAND, 4, &cfg); |
d99bb1db | 170 | n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); |
2d86c385 | 171 | pr_warn("EEH: PCI cmd/status register: %08x\n", cfg); |
fcf9892b | 172 | |
0b9369f4 | 173 | /* Gather bridge-specific registers */ |
2a18dfc6 | 174 | if (edev->mode & EEH_DEV_BRIDGE) { |
3780444c | 175 | eeh_ops->read_config(dn, PCI_SEC_STATUS, 2, &cfg); |
0b9369f4 | 176 | n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); |
2d86c385 | 177 | pr_warn("EEH: Bridge secondary status: %04x\n", cfg); |
0b9369f4 | 178 | |
3780444c | 179 | eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &cfg); |
0b9369f4 | 180 | n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); |
2d86c385 | 181 | pr_warn("EEH: Bridge control: %04x\n", cfg); |
0b9369f4 LV |
182 | } |
183 | ||
fcf9892b | 184 | /* Dump out the PCI-X command and status regs */ |
2a18dfc6 | 185 | cap = edev->pcix_cap; |
fcf9892b | 186 | if (cap) { |
3780444c | 187 | eeh_ops->read_config(dn, cap, 4, &cfg); |
fcf9892b | 188 | n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); |
2d86c385 | 189 | pr_warn("EEH: PCI-X cmd: %08x\n", cfg); |
fcf9892b | 190 | |
3780444c | 191 | eeh_ops->read_config(dn, cap+4, 4, &cfg); |
fcf9892b | 192 | n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); |
2d86c385 | 193 | pr_warn("EEH: PCI-X status: %08x\n", cfg); |
fcf9892b LV |
194 | } |
195 | ||
2a18dfc6 GS |
196 | /* If PCI-E capable, dump PCI-E cap 10 */ |
197 | cap = edev->pcie_cap; | |
198 | if (cap) { | |
fcf9892b | 199 | n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); |
2d86c385 | 200 | pr_warn("EEH: PCI-E capabilities and status follow:\n"); |
fcf9892b LV |
201 | |
202 | for (i=0; i<=8; i++) { | |
2a18dfc6 | 203 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); |
fcf9892b | 204 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
2d86c385 | 205 | pr_warn("EEH: PCI-E %02x: %08x\n", i, cfg); |
fcf9892b | 206 | } |
2a18dfc6 | 207 | } |
fcf9892b | 208 | |
2a18dfc6 GS |
209 | /* If AER capable, dump it */ |
210 | cap = edev->aer_cap; | |
211 | if (cap) { | |
212 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); | |
213 | pr_warn("EEH: PCI-E AER capability register set follows:\n"); | |
214 | ||
215 | for (i=0; i<14; i++) { | |
216 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); | |
217 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
218 | pr_warn("EEH: PCI-E AER %02x: %08x\n", i, cfg); | |
fcf9892b LV |
219 | } |
220 | } | |
0b9369f4 | 221 | |
d99bb1db LV |
222 | return n; |
223 | } | |
224 | ||
cb3bc9d0 GS |
225 | /** |
226 | * eeh_slot_error_detail - Generate combined log including driver log and error log | |
ff477966 | 227 | * @pe: EEH PE |
cb3bc9d0 GS |
228 | * @severity: temporary or permanent error log |
229 | * | |
230 | * This routine should be called to generate the combined log, which | |
231 | * is comprised of driver log and error log. The driver log is figured | |
232 | * out from the config space of the corresponding PCI device, while | |
233 | * the error log is fetched through platform dependent function call. | |
234 | */ | |
ff477966 | 235 | void eeh_slot_error_detail(struct eeh_pe *pe, int severity) |
d99bb1db LV |
236 | { |
237 | size_t loglen = 0; | |
9feed42e | 238 | struct eeh_dev *edev, *tmp; |
d99bb1db | 239 | |
c35ae179 GS |
240 | /* |
241 | * When the PHB is fenced or dead, it's pointless to collect | |
242 | * the data from PCI config space because it should return | |
243 | * 0xFF's. For ER, we still retrieve the data from the PCI | |
244 | * config space. | |
78954700 GS |
245 | * |
246 | * For pHyp, we have to enable IO for log retrieval. Otherwise, | |
247 | * 0xFF's is always returned from PCI config space. | |
c35ae179 | 248 | */ |
9e049375 | 249 | if (!(pe->type & EEH_PE_PHB)) { |
78954700 GS |
250 | if (eeh_probe_mode_devtree()) |
251 | eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); | |
c35ae179 GS |
252 | eeh_ops->configure_bridge(pe); |
253 | eeh_pe_restore_bars(pe); | |
254 | ||
255 | pci_regs_buf[0] = 0; | |
9feed42e | 256 | eeh_pe_for_each_dev(pe, edev, tmp) { |
c35ae179 GS |
257 | loglen += eeh_gather_pci_data(edev, pci_regs_buf + loglen, |
258 | EEH_PCI_REGS_LOG_LEN - loglen); | |
259 | } | |
260 | } | |
ff477966 GS |
261 | |
262 | eeh_ops->get_log(pe, severity, pci_regs_buf, loglen); | |
d99bb1db LV |
263 | } |
264 | ||
1da177e4 | 265 | /** |
cb3bc9d0 GS |
266 | * eeh_token_to_phys - Convert EEH address token to phys address |
267 | * @token: I/O token, should be address in the form 0xA.... | |
268 | * | |
269 | * This routine should be called to convert virtual I/O address | |
270 | * to physical one. | |
1da177e4 LT |
271 | */ |
272 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
273 | { | |
274 | pte_t *ptep; | |
275 | unsigned long pa; | |
12bc9f6f | 276 | int hugepage_shift; |
1da177e4 | 277 | |
12bc9f6f AK |
278 | /* |
279 | * We won't find hugepages here, iomem | |
280 | */ | |
281 | ptep = find_linux_pte_or_hugepte(init_mm.pgd, token, &hugepage_shift); | |
1da177e4 LT |
282 | if (!ptep) |
283 | return token; | |
12bc9f6f | 284 | WARN_ON(hugepage_shift); |
1da177e4 LT |
285 | pa = pte_pfn(*ptep) << PAGE_SHIFT; |
286 | ||
287 | return pa | (token & (PAGE_SIZE-1)); | |
288 | } | |
289 | ||
b95cd2cd GS |
290 | /* |
291 | * On PowerNV platform, we might already have fenced PHB there. | |
292 | * For that case, it's meaningless to recover frozen PE. Intead, | |
293 | * We have to handle fenced PHB firstly. | |
294 | */ | |
295 | static int eeh_phb_check_failure(struct eeh_pe *pe) | |
296 | { | |
297 | struct eeh_pe *phb_pe; | |
298 | unsigned long flags; | |
299 | int ret; | |
300 | ||
301 | if (!eeh_probe_mode_dev()) | |
302 | return -EPERM; | |
303 | ||
304 | /* Find the PHB PE */ | |
305 | phb_pe = eeh_phb_pe_get(pe->phb); | |
306 | if (!phb_pe) { | |
307 | pr_warning("%s Can't find PE for PHB#%d\n", | |
308 | __func__, pe->phb->global_number); | |
309 | return -EEXIST; | |
310 | } | |
311 | ||
312 | /* If the PHB has been in problematic state */ | |
313 | eeh_serialize_lock(&flags); | |
9e049375 | 314 | if (phb_pe->state & EEH_PE_ISOLATED) { |
b95cd2cd GS |
315 | ret = 0; |
316 | goto out; | |
317 | } | |
318 | ||
319 | /* Check PHB state */ | |
320 | ret = eeh_ops->get_state(phb_pe, NULL); | |
321 | if ((ret < 0) || | |
322 | (ret == EEH_STATE_NOT_SUPPORT) || | |
323 | (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) == | |
324 | (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) { | |
325 | ret = 0; | |
326 | goto out; | |
327 | } | |
328 | ||
329 | /* Isolate the PHB and send event */ | |
330 | eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED); | |
331 | eeh_serialize_unlock(flags); | |
b95cd2cd | 332 | |
357b2f3d GS |
333 | pr_err("EEH: PHB#%x failure detected, location: %s\n", |
334 | phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe)); | |
56ca4fde | 335 | dump_stack(); |
5293bf97 | 336 | eeh_send_failure_event(phb_pe); |
b95cd2cd GS |
337 | |
338 | return 1; | |
339 | out: | |
340 | eeh_serialize_unlock(flags); | |
341 | return ret; | |
342 | } | |
343 | ||
1da177e4 | 344 | /** |
f8f7d63f GS |
345 | * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze |
346 | * @edev: eeh device | |
1da177e4 LT |
347 | * |
348 | * Check for an EEH failure for the given device node. Call this | |
349 | * routine if the result of a read was all 0xff's and you want to | |
350 | * find out if this is due to an EEH slot freeze. This routine | |
351 | * will query firmware for the EEH status. | |
352 | * | |
353 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 354 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
355 | * |
356 | * It is safe to call this routine in an interrupt context. | |
357 | */ | |
f8f7d63f | 358 | int eeh_dev_check_failure(struct eeh_dev *edev) |
1da177e4 LT |
359 | { |
360 | int ret; | |
1ad7a72c | 361 | int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
1da177e4 | 362 | unsigned long flags; |
f8f7d63f GS |
363 | struct device_node *dn; |
364 | struct pci_dev *dev; | |
357b2f3d | 365 | struct eeh_pe *pe, *parent_pe, *phb_pe; |
fd761fd8 | 366 | int rc = 0; |
f36c5227 | 367 | const char *location; |
1da177e4 | 368 | |
e575f8db | 369 | eeh_stats.total_mmio_ffs++; |
1da177e4 | 370 | |
2ec5a0ad | 371 | if (!eeh_enabled()) |
1da177e4 LT |
372 | return 0; |
373 | ||
f8f7d63f | 374 | if (!edev) { |
e575f8db | 375 | eeh_stats.no_dn++; |
1da177e4 | 376 | return 0; |
177bc936 | 377 | } |
f8f7d63f GS |
378 | dn = eeh_dev_to_of_node(edev); |
379 | dev = eeh_dev_to_pci_dev(edev); | |
66523d9f | 380 | pe = edev->pe; |
1da177e4 LT |
381 | |
382 | /* Access to IO BARs might get this far and still not want checking. */ | |
66523d9f | 383 | if (!pe) { |
e575f8db | 384 | eeh_stats.ignored_check++; |
66523d9f GS |
385 | pr_debug("EEH: Ignored check for %s %s\n", |
386 | eeh_pci_name(dev), dn->full_name); | |
1da177e4 LT |
387 | return 0; |
388 | } | |
389 | ||
66523d9f | 390 | if (!pe->addr && !pe->config_addr) { |
e575f8db | 391 | eeh_stats.no_cfg_addr++; |
1da177e4 LT |
392 | return 0; |
393 | } | |
394 | ||
b95cd2cd GS |
395 | /* |
396 | * On PowerNV platform, we might already have fenced PHB | |
397 | * there and we need take care of that firstly. | |
398 | */ | |
399 | ret = eeh_phb_check_failure(pe); | |
400 | if (ret > 0) | |
401 | return ret; | |
402 | ||
05ec424e GS |
403 | /* |
404 | * If the PE isn't owned by us, we shouldn't check the | |
405 | * state. Instead, let the owner handle it if the PE has | |
406 | * been frozen. | |
407 | */ | |
408 | if (eeh_pe_passed(pe)) | |
409 | return 0; | |
410 | ||
fd761fd8 LV |
411 | /* If we already have a pending isolation event for this |
412 | * slot, we know it's bad already, we don't need to check. | |
413 | * Do this checking under a lock; as multiple PCI devices | |
414 | * in one slot might report errors simultaneously, and we | |
415 | * only want one error recovery routine running. | |
1da177e4 | 416 | */ |
4907581d | 417 | eeh_serialize_lock(&flags); |
fd761fd8 | 418 | rc = 1; |
66523d9f GS |
419 | if (pe->state & EEH_PE_ISOLATED) { |
420 | pe->check_count++; | |
421 | if (pe->check_count % EEH_MAX_FAILS == 0) { | |
f36c5227 | 422 | location = of_get_property(dn, "ibm,loc-code", NULL); |
cb3bc9d0 | 423 | printk(KERN_ERR "EEH: %d reads ignored for recovering device at " |
f36c5227 | 424 | "location=%s driver=%s pci addr=%s\n", |
66523d9f | 425 | pe->check_count, location, |
778a785f | 426 | eeh_driver_name(dev), eeh_pci_name(dev)); |
cb3bc9d0 | 427 | printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n", |
778a785f | 428 | eeh_driver_name(dev)); |
5c1344e9 | 429 | dump_stack(); |
1da177e4 | 430 | } |
fd761fd8 | 431 | goto dn_unlock; |
1da177e4 LT |
432 | } |
433 | ||
434 | /* | |
435 | * Now test for an EEH failure. This is VERY expensive. | |
436 | * Note that the eeh_config_addr may be a parent device | |
437 | * in the case of a device behind a bridge, or it may be | |
438 | * function zero of a multi-function device. | |
439 | * In any case they must share a common PHB. | |
440 | */ | |
66523d9f | 441 | ret = eeh_ops->get_state(pe, NULL); |
76e6faf7 | 442 | |
39d16e29 | 443 | /* Note that config-io to empty slots may fail; |
cb3bc9d0 | 444 | * they are empty when they don't have children. |
eb594a47 GS |
445 | * We will punt with the following conditions: Failure to get |
446 | * PE's state, EEH not support and Permanently unavailable | |
447 | * state, PE is in good state. | |
cb3bc9d0 | 448 | */ |
eb594a47 GS |
449 | if ((ret < 0) || |
450 | (ret == EEH_STATE_NOT_SUPPORT) || | |
1ad7a72c | 451 | ((ret & active_flags) == active_flags)) { |
e575f8db | 452 | eeh_stats.false_positives++; |
66523d9f | 453 | pe->false_positives++; |
fd761fd8 LV |
454 | rc = 0; |
455 | goto dn_unlock; | |
76e6faf7 LV |
456 | } |
457 | ||
1ad7a72c GS |
458 | /* |
459 | * It should be corner case that the parent PE has been | |
460 | * put into frozen state as well. We should take care | |
461 | * that at first. | |
462 | */ | |
463 | parent_pe = pe->parent; | |
464 | while (parent_pe) { | |
465 | /* Hit the ceiling ? */ | |
466 | if (parent_pe->type & EEH_PE_PHB) | |
467 | break; | |
468 | ||
469 | /* Frozen parent PE ? */ | |
470 | ret = eeh_ops->get_state(parent_pe, NULL); | |
471 | if (ret > 0 && | |
472 | (ret & active_flags) != active_flags) | |
473 | pe = parent_pe; | |
474 | ||
475 | /* Next parent level */ | |
476 | parent_pe = parent_pe->parent; | |
477 | } | |
478 | ||
e575f8db | 479 | eeh_stats.slot_resets++; |
a84f273c | 480 | |
fd761fd8 LV |
481 | /* Avoid repeated reports of this failure, including problems |
482 | * with other functions on this device, and functions under | |
cb3bc9d0 GS |
483 | * bridges. |
484 | */ | |
66523d9f | 485 | eeh_pe_state_mark(pe, EEH_PE_ISOLATED); |
4907581d | 486 | eeh_serialize_unlock(flags); |
1da177e4 | 487 | |
1da177e4 LT |
488 | /* Most EEH events are due to device driver bugs. Having |
489 | * a stack trace will help the device-driver authors figure | |
cb3bc9d0 GS |
490 | * out what happened. So print that out. |
491 | */ | |
357b2f3d GS |
492 | phb_pe = eeh_phb_pe_get(pe->phb); |
493 | pr_err("EEH: Frozen PHB#%x-PE#%x detected\n", | |
494 | pe->phb->global_number, pe->addr); | |
495 | pr_err("EEH: PE location: %s, PHB location: %s\n", | |
496 | eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe)); | |
56ca4fde GS |
497 | dump_stack(); |
498 | ||
5293bf97 GS |
499 | eeh_send_failure_event(pe); |
500 | ||
fd761fd8 LV |
501 | return 1; |
502 | ||
503 | dn_unlock: | |
4907581d | 504 | eeh_serialize_unlock(flags); |
fd761fd8 | 505 | return rc; |
1da177e4 LT |
506 | } |
507 | ||
f8f7d63f | 508 | EXPORT_SYMBOL_GPL(eeh_dev_check_failure); |
1da177e4 LT |
509 | |
510 | /** | |
cb3bc9d0 GS |
511 | * eeh_check_failure - Check if all 1's data is due to EEH slot freeze |
512 | * @token: I/O token, should be address in the form 0xA.... | |
513 | * @val: value, should be all 1's (XXX why do we need this arg??) | |
1da177e4 | 514 | * |
1da177e4 LT |
515 | * Check for an EEH failure at the given token address. Call this |
516 | * routine if the result of a read was all 0xff's and you want to | |
517 | * find out if this is due to an EEH slot freeze event. This routine | |
518 | * will query firmware for the EEH status. | |
519 | * | |
520 | * Note this routine is safe to call in an interrupt context. | |
521 | */ | |
522 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
523 | { | |
524 | unsigned long addr; | |
f8f7d63f | 525 | struct eeh_dev *edev; |
1da177e4 LT |
526 | |
527 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
528 | addr = eeh_token_to_phys((unsigned long __force) token); | |
3ab96a02 | 529 | edev = eeh_addr_cache_get_dev(addr); |
f8f7d63f | 530 | if (!edev) { |
e575f8db | 531 | eeh_stats.no_device++; |
1da177e4 | 532 | return val; |
177bc936 | 533 | } |
1da177e4 | 534 | |
f8f7d63f | 535 | eeh_dev_check_failure(edev); |
1da177e4 LT |
536 | return val; |
537 | } | |
538 | ||
539 | EXPORT_SYMBOL(eeh_check_failure); | |
540 | ||
6dee3fb9 | 541 | |
47b5c838 | 542 | /** |
cce4b2d2 | 543 | * eeh_pci_enable - Enable MMIO or DMA transfers for this slot |
ff477966 | 544 | * @pe: EEH PE |
cb3bc9d0 GS |
545 | * |
546 | * This routine should be called to reenable frozen MMIO or DMA | |
547 | * so that it would work correctly again. It's useful while doing | |
548 | * recovery or log collection on the indicated device. | |
47b5c838 | 549 | */ |
ff477966 | 550 | int eeh_pci_enable(struct eeh_pe *pe, int function) |
47b5c838 | 551 | { |
78954700 GS |
552 | int rc, flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
553 | ||
554 | /* | |
555 | * pHyp doesn't allow to enable IO or DMA on unfrozen PE. | |
556 | * Also, it's pointless to enable them on unfrozen PE. So | |
557 | * we have the check here. | |
558 | */ | |
559 | if (function == EEH_OPT_THAW_MMIO || | |
560 | function == EEH_OPT_THAW_DMA) { | |
561 | rc = eeh_ops->get_state(pe, NULL); | |
562 | if (rc < 0) | |
563 | return rc; | |
564 | ||
565 | /* Needn't to enable or already enabled */ | |
566 | if ((rc == EEH_STATE_NOT_SUPPORT) || | |
567 | ((rc & flags) == flags)) | |
568 | return 0; | |
569 | } | |
47b5c838 | 570 | |
ff477966 | 571 | rc = eeh_ops->set_option(pe, function); |
47b5c838 | 572 | if (rc) |
78954700 GS |
573 | pr_warn("%s: Unexpected state change %d on " |
574 | "PHB#%d-PE#%x, err=%d\n", | |
575 | __func__, function, pe->phb->global_number, | |
576 | pe->addr, rc); | |
47b5c838 | 577 | |
ff477966 | 578 | rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); |
78954700 GS |
579 | if (rc <= 0) |
580 | return rc; | |
581 | ||
582 | if ((function == EEH_OPT_THAW_MMIO) && | |
583 | (rc & EEH_STATE_MMIO_ENABLED)) | |
584 | return 0; | |
585 | ||
586 | if ((function == EEH_OPT_THAW_DMA) && | |
587 | (rc & EEH_STATE_DMA_ENABLED)) | |
fa1be476 LV |
588 | return 0; |
589 | ||
47b5c838 LV |
590 | return rc; |
591 | } | |
592 | ||
00c2ae35 BK |
593 | /** |
594 | * pcibios_set_pcie_slot_reset - Set PCI-E reset state | |
cb3bc9d0 GS |
595 | * @dev: pci device struct |
596 | * @state: reset state to enter | |
00c2ae35 BK |
597 | * |
598 | * Return value: | |
599 | * 0 if success | |
cb3bc9d0 | 600 | */ |
00c2ae35 BK |
601 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) |
602 | { | |
c270a24c GS |
603 | struct eeh_dev *edev = pci_dev_to_eeh_dev(dev); |
604 | struct eeh_pe *pe = edev->pe; | |
605 | ||
606 | if (!pe) { | |
607 | pr_err("%s: No PE found on PCI device %s\n", | |
608 | __func__, pci_name(dev)); | |
609 | return -EINVAL; | |
610 | } | |
00c2ae35 BK |
611 | |
612 | switch (state) { | |
613 | case pcie_deassert_reset: | |
c270a24c | 614 | eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); |
00c2ae35 BK |
615 | break; |
616 | case pcie_hot_reset: | |
c270a24c | 617 | eeh_ops->reset(pe, EEH_RESET_HOT); |
00c2ae35 BK |
618 | break; |
619 | case pcie_warm_reset: | |
c270a24c | 620 | eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); |
00c2ae35 BK |
621 | break; |
622 | default: | |
623 | return -EINVAL; | |
624 | }; | |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
cb5b5624 | 629 | /** |
c270a24c GS |
630 | * eeh_set_pe_freset - Check the required reset for the indicated device |
631 | * @data: EEH device | |
632 | * @flag: return value | |
cb3bc9d0 GS |
633 | * |
634 | * Each device might have its preferred reset type: fundamental or | |
635 | * hot reset. The routine is used to collected the information for | |
636 | * the indicated device and its children so that the bunch of the | |
637 | * devices could be reset properly. | |
638 | */ | |
c270a24c | 639 | static void *eeh_set_dev_freset(void *data, void *flag) |
cb3bc9d0 GS |
640 | { |
641 | struct pci_dev *dev; | |
c270a24c GS |
642 | unsigned int *freset = (unsigned int *)flag; |
643 | struct eeh_dev *edev = (struct eeh_dev *)data; | |
6dee3fb9 | 644 | |
c270a24c | 645 | dev = eeh_dev_to_pci_dev(edev); |
cb3bc9d0 GS |
646 | if (dev) |
647 | *freset |= dev->needs_freset; | |
648 | ||
c270a24c | 649 | return NULL; |
cb3bc9d0 GS |
650 | } |
651 | ||
652 | /** | |
cce4b2d2 | 653 | * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second |
c270a24c | 654 | * @pe: EEH PE |
cb3bc9d0 GS |
655 | * |
656 | * Assert the PCI #RST line for 1/4 second. | |
657 | */ | |
c270a24c | 658 | static void eeh_reset_pe_once(struct eeh_pe *pe) |
6dee3fb9 | 659 | { |
308fc4f8 | 660 | unsigned int freset = 0; |
6e19314c | 661 | |
308fc4f8 RL |
662 | /* Determine type of EEH reset required for |
663 | * Partitionable Endpoint, a hot-reset (1) | |
664 | * or a fundamental reset (3). | |
665 | * A fundamental reset required by any device under | |
666 | * Partitionable Endpoint trumps hot-reset. | |
a84f273c | 667 | */ |
c270a24c | 668 | eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset); |
308fc4f8 RL |
669 | |
670 | if (freset) | |
c270a24c | 671 | eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); |
6e19314c | 672 | else |
c270a24c | 673 | eeh_ops->reset(pe, EEH_RESET_HOT); |
6dee3fb9 | 674 | |
c270a24c | 675 | eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); |
e1029263 LV |
676 | } |
677 | ||
cb3bc9d0 | 678 | /** |
cce4b2d2 | 679 | * eeh_reset_pe - Reset the indicated PE |
c270a24c | 680 | * @pe: EEH PE |
cb3bc9d0 GS |
681 | * |
682 | * This routine should be called to reset indicated device, including | |
683 | * PE. A PE might include multiple PCI devices and sometimes PCI bridges | |
684 | * might be involved as well. | |
685 | */ | |
c270a24c | 686 | int eeh_reset_pe(struct eeh_pe *pe) |
e1029263 | 687 | { |
326a98ea | 688 | int flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
e1029263 LV |
689 | int i, rc; |
690 | ||
9c547768 LV |
691 | /* Take three shots at resetting the bus */ |
692 | for (i=0; i<3; i++) { | |
c270a24c | 693 | eeh_reset_pe_once(pe); |
6dee3fb9 | 694 | |
78954700 GS |
695 | /* |
696 | * EEH_PE_ISOLATED is expected to be removed after | |
697 | * BAR restore. | |
698 | */ | |
c270a24c | 699 | rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); |
78954700 | 700 | if ((rc & flags) == flags) |
b6495c0c | 701 | return 0; |
e1029263 | 702 | |
e1029263 | 703 | if (rc < 0) { |
c270a24c GS |
704 | pr_err("%s: Unrecoverable slot failure on PHB#%d-PE#%x", |
705 | __func__, pe->phb->global_number, pe->addr); | |
b6495c0c | 706 | return -1; |
e1029263 | 707 | } |
c270a24c GS |
708 | pr_err("EEH: bus reset %d failed on PHB#%d-PE#%x, rc=%d\n", |
709 | i+1, pe->phb->global_number, pe->addr, rc); | |
6dee3fb9 | 710 | } |
b6495c0c | 711 | |
9c547768 | 712 | return -1; |
6dee3fb9 LV |
713 | } |
714 | ||
8b553f32 | 715 | /** |
cb3bc9d0 | 716 | * eeh_save_bars - Save device bars |
f631acd3 | 717 | * @edev: PCI device associated EEH device |
8b553f32 LV |
718 | * |
719 | * Save the values of the device bars. Unlike the restore | |
720 | * routine, this routine is *not* recursive. This is because | |
31116f0b | 721 | * PCI devices are added individually; but, for the restore, |
8b553f32 LV |
722 | * an entire slot is reset at a time. |
723 | */ | |
d7bb8862 | 724 | void eeh_save_bars(struct eeh_dev *edev) |
8b553f32 LV |
725 | { |
726 | int i; | |
f631acd3 | 727 | struct device_node *dn; |
8b553f32 | 728 | |
f631acd3 | 729 | if (!edev) |
8b553f32 | 730 | return; |
f631acd3 | 731 | dn = eeh_dev_to_of_node(edev); |
a84f273c | 732 | |
8b553f32 | 733 | for (i = 0; i < 16; i++) |
3780444c | 734 | eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]); |
bf898ec5 GS |
735 | |
736 | /* | |
737 | * For PCI bridges including root port, we need enable bus | |
738 | * master explicitly. Otherwise, it can't fetch IODA table | |
739 | * entries correctly. So we cache the bit in advance so that | |
740 | * we can restore it after reset, either PHB range or PE range. | |
741 | */ | |
742 | if (edev->mode & EEH_DEV_BRIDGE) | |
743 | edev->config_space[1] |= PCI_COMMAND_MASTER; | |
8b553f32 LV |
744 | } |
745 | ||
aa1e6374 GS |
746 | /** |
747 | * eeh_ops_register - Register platform dependent EEH operations | |
748 | * @ops: platform dependent EEH operations | |
749 | * | |
750 | * Register the platform dependent EEH operation callback | |
751 | * functions. The platform should call this function before | |
752 | * any other EEH operations. | |
753 | */ | |
754 | int __init eeh_ops_register(struct eeh_ops *ops) | |
755 | { | |
756 | if (!ops->name) { | |
757 | pr_warning("%s: Invalid EEH ops name for %p\n", | |
758 | __func__, ops); | |
759 | return -EINVAL; | |
760 | } | |
761 | ||
762 | if (eeh_ops && eeh_ops != ops) { | |
763 | pr_warning("%s: EEH ops of platform %s already existing (%s)\n", | |
764 | __func__, eeh_ops->name, ops->name); | |
765 | return -EEXIST; | |
766 | } | |
767 | ||
768 | eeh_ops = ops; | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
773 | /** | |
774 | * eeh_ops_unregister - Unreigster platform dependent EEH operations | |
775 | * @name: name of EEH platform operations | |
776 | * | |
777 | * Unregister the platform dependent EEH operation callback | |
778 | * functions. | |
779 | */ | |
780 | int __exit eeh_ops_unregister(const char *name) | |
781 | { | |
782 | if (!name || !strlen(name)) { | |
783 | pr_warning("%s: Invalid EEH ops name\n", | |
784 | __func__); | |
785 | return -EINVAL; | |
786 | } | |
787 | ||
788 | if (eeh_ops && !strcmp(eeh_ops->name, name)) { | |
789 | eeh_ops = NULL; | |
790 | return 0; | |
791 | } | |
792 | ||
793 | return -EEXIST; | |
794 | } | |
795 | ||
66f9af83 GS |
796 | static int eeh_reboot_notifier(struct notifier_block *nb, |
797 | unsigned long action, void *unused) | |
798 | { | |
799 | eeh_set_enable(false); | |
800 | return NOTIFY_DONE; | |
801 | } | |
802 | ||
803 | static struct notifier_block eeh_reboot_nb = { | |
804 | .notifier_call = eeh_reboot_notifier, | |
805 | }; | |
806 | ||
cb3bc9d0 GS |
807 | /** |
808 | * eeh_init - EEH initialization | |
809 | * | |
1da177e4 LT |
810 | * Initialize EEH by trying to enable it for all of the adapters in the system. |
811 | * As a side effect we can determine here if eeh is supported at all. | |
812 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
813 | * check. If a user turns off EEH for a particular adapter they are really | |
814 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
815 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
816 | * EEH for all slots/all devices. | |
817 | * | |
818 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
819 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
820 | * newer systems can boot. | |
821 | */ | |
eeb6361f | 822 | int eeh_init(void) |
1da177e4 | 823 | { |
1a5c2e63 GS |
824 | struct pci_controller *hose, *tmp; |
825 | struct device_node *phb; | |
51fb5f56 GS |
826 | static int cnt = 0; |
827 | int ret = 0; | |
828 | ||
829 | /* | |
830 | * We have to delay the initialization on PowerNV after | |
831 | * the PCI hierarchy tree has been built because the PEs | |
832 | * are figured out based on PCI devices instead of device | |
833 | * tree nodes | |
834 | */ | |
835 | if (machine_is(powernv) && cnt++ <= 0) | |
836 | return ret; | |
e2af155c | 837 | |
66f9af83 GS |
838 | /* Register reboot notifier */ |
839 | ret = register_reboot_notifier(&eeh_reboot_nb); | |
840 | if (ret) { | |
841 | pr_warn("%s: Failed to register notifier (%d)\n", | |
842 | __func__, ret); | |
843 | return ret; | |
844 | } | |
845 | ||
e2af155c GS |
846 | /* call platform initialization function */ |
847 | if (!eeh_ops) { | |
848 | pr_warning("%s: Platform EEH operation not found\n", | |
849 | __func__); | |
35e5cfe2 | 850 | return -EEXIST; |
e2af155c GS |
851 | } else if ((ret = eeh_ops->init())) { |
852 | pr_warning("%s: Failed to call platform init function (%d)\n", | |
853 | __func__, ret); | |
35e5cfe2 | 854 | return ret; |
e2af155c | 855 | } |
1da177e4 | 856 | |
c8608558 GS |
857 | /* Initialize EEH event */ |
858 | ret = eeh_event_init(); | |
859 | if (ret) | |
860 | return ret; | |
861 | ||
1a5c2e63 | 862 | /* Enable EEH for all adapters */ |
d7bb8862 GS |
863 | if (eeh_probe_mode_devtree()) { |
864 | list_for_each_entry_safe(hose, tmp, | |
865 | &hose_list, list_node) { | |
866 | phb = hose->dn; | |
867 | traverse_pci_devices(phb, eeh_ops->of_probe, NULL); | |
868 | } | |
51fb5f56 GS |
869 | } else if (eeh_probe_mode_dev()) { |
870 | list_for_each_entry_safe(hose, tmp, | |
871 | &hose_list, list_node) | |
872 | pci_walk_bus(hose->bus, eeh_ops->dev_probe, NULL); | |
873 | } else { | |
8a5ad356 GS |
874 | pr_warn("%s: Invalid probe mode %x", |
875 | __func__, eeh_subsystem_flags); | |
51fb5f56 | 876 | return -EINVAL; |
1da177e4 LT |
877 | } |
878 | ||
21fd21f5 GS |
879 | /* |
880 | * Call platform post-initialization. Actually, It's good chance | |
881 | * to inform platform that EEH is ready to supply service if the | |
882 | * I/O cache stuff has been built up. | |
883 | */ | |
884 | if (eeh_ops->post_init) { | |
885 | ret = eeh_ops->post_init(); | |
886 | if (ret) | |
887 | return ret; | |
888 | } | |
889 | ||
2ec5a0ad | 890 | if (eeh_enabled()) |
d7bb8862 | 891 | pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n"); |
1da177e4 | 892 | else |
d7bb8862 | 893 | pr_warning("EEH: No capable adapters found\n"); |
35e5cfe2 GS |
894 | |
895 | return ret; | |
1da177e4 LT |
896 | } |
897 | ||
35e5cfe2 GS |
898 | core_initcall_sync(eeh_init); |
899 | ||
1da177e4 | 900 | /** |
cb3bc9d0 | 901 | * eeh_add_device_early - Enable EEH for the indicated device_node |
1da177e4 LT |
902 | * @dn: device node for which to set up EEH |
903 | * | |
904 | * This routine must be used to perform EEH initialization for PCI | |
905 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
906 | * This routine must be called before any i/o is performed to the | |
907 | * adapter (inluding any config-space i/o). | |
908 | * Whether this actually enables EEH or not for this device depends | |
909 | * on the CEC architecture, type of the device, on earlier boot | |
910 | * command-line arguments & etc. | |
911 | */ | |
f2856491 | 912 | void eeh_add_device_early(struct device_node *dn) |
1da177e4 LT |
913 | { |
914 | struct pci_controller *phb; | |
1da177e4 | 915 | |
26a74850 GS |
916 | /* |
917 | * If we're doing EEH probe based on PCI device, we | |
918 | * would delay the probe until late stage because | |
919 | * the PCI device isn't available this moment. | |
920 | */ | |
921 | if (!eeh_probe_mode_devtree()) | |
922 | return; | |
923 | ||
1e38b714 | 924 | if (!of_node_to_eeh_dev(dn)) |
1da177e4 | 925 | return; |
f631acd3 | 926 | phb = of_node_to_eeh_dev(dn)->phb; |
f751f841 LV |
927 | |
928 | /* USB Bus children of PCI devices will not have BUID's */ | |
929 | if (NULL == phb || 0 == phb->buid) | |
1da177e4 | 930 | return; |
1da177e4 | 931 | |
d7bb8862 | 932 | eeh_ops->of_probe(dn, NULL); |
1da177e4 | 933 | } |
1da177e4 | 934 | |
cb3bc9d0 GS |
935 | /** |
936 | * eeh_add_device_tree_early - Enable EEH for the indicated device | |
937 | * @dn: device node | |
938 | * | |
939 | * This routine must be used to perform EEH initialization for the | |
940 | * indicated PCI device that was added after system boot (e.g. | |
941 | * hotplug, dlpar). | |
942 | */ | |
e2a296ee LV |
943 | void eeh_add_device_tree_early(struct device_node *dn) |
944 | { | |
945 | struct device_node *sib; | |
acaa6176 SR |
946 | |
947 | for_each_child_of_node(dn, sib) | |
e2a296ee LV |
948 | eeh_add_device_tree_early(sib); |
949 | eeh_add_device_early(dn); | |
950 | } | |
951 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
952 | ||
1da177e4 | 953 | /** |
cb3bc9d0 | 954 | * eeh_add_device_late - Perform EEH initialization for the indicated pci device |
1da177e4 LT |
955 | * @dev: pci device for which to set up EEH |
956 | * | |
957 | * This routine must be used to complete EEH initialization for PCI | |
958 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
959 | */ | |
f2856491 | 960 | void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 961 | { |
56b0fca3 | 962 | struct device_node *dn; |
f631acd3 | 963 | struct eeh_dev *edev; |
56b0fca3 | 964 | |
2ec5a0ad | 965 | if (!dev || !eeh_enabled()) |
1da177e4 LT |
966 | return; |
967 | ||
57b066ff | 968 | pr_debug("EEH: Adding device %s\n", pci_name(dev)); |
1da177e4 | 969 | |
56b0fca3 | 970 | dn = pci_device_to_OF_node(dev); |
2ef822c5 | 971 | edev = of_node_to_eeh_dev(dn); |
f631acd3 | 972 | if (edev->pdev == dev) { |
57b066ff BH |
973 | pr_debug("EEH: Already referenced !\n"); |
974 | return; | |
975 | } | |
f5c57710 GS |
976 | |
977 | /* | |
978 | * The EEH cache might not be removed correctly because of | |
979 | * unbalanced kref to the device during unplug time, which | |
980 | * relies on pcibios_release_device(). So we have to remove | |
981 | * that here explicitly. | |
982 | */ | |
983 | if (edev->pdev) { | |
984 | eeh_rmv_from_parent_pe(edev); | |
985 | eeh_addr_cache_rmv_dev(edev->pdev); | |
986 | eeh_sysfs_remove_device(edev->pdev); | |
ab55d218 | 987 | edev->mode &= ~EEH_DEV_SYSFS; |
f5c57710 | 988 | |
f26c7a03 GS |
989 | /* |
990 | * We definitely should have the PCI device removed | |
991 | * though it wasn't correctly. So we needn't call | |
992 | * into error handler afterwards. | |
993 | */ | |
994 | edev->mode |= EEH_DEV_NO_HANDLER; | |
995 | ||
f5c57710 GS |
996 | edev->pdev = NULL; |
997 | dev->dev.archdata.edev = NULL; | |
998 | } | |
57b066ff | 999 | |
f631acd3 GS |
1000 | edev->pdev = dev; |
1001 | dev->dev.archdata.edev = edev; | |
56b0fca3 | 1002 | |
26a74850 GS |
1003 | /* |
1004 | * We have to do the EEH probe here because the PCI device | |
1005 | * hasn't been created yet in the early stage. | |
1006 | */ | |
1007 | if (eeh_probe_mode_dev()) | |
1008 | eeh_ops->dev_probe(dev, NULL); | |
1009 | ||
3ab96a02 | 1010 | eeh_addr_cache_insert_dev(dev); |
1da177e4 | 1011 | } |
794e085e | 1012 | |
cb3bc9d0 GS |
1013 | /** |
1014 | * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus | |
1015 | * @bus: PCI bus | |
1016 | * | |
1017 | * This routine must be used to perform EEH initialization for PCI | |
1018 | * devices which are attached to the indicated PCI bus. The PCI bus | |
1019 | * is added after system boot through hotplug or dlpar. | |
1020 | */ | |
794e085e NF |
1021 | void eeh_add_device_tree_late(struct pci_bus *bus) |
1022 | { | |
1023 | struct pci_dev *dev; | |
1024 | ||
1025 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
a84f273c GS |
1026 | eeh_add_device_late(dev); |
1027 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1028 | struct pci_bus *subbus = dev->subordinate; | |
1029 | if (subbus) | |
1030 | eeh_add_device_tree_late(subbus); | |
1031 | } | |
794e085e NF |
1032 | } |
1033 | } | |
1034 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 | 1035 | |
6a040ce7 TLSC |
1036 | /** |
1037 | * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus | |
1038 | * @bus: PCI bus | |
1039 | * | |
1040 | * This routine must be used to add EEH sysfs files for PCI | |
1041 | * devices which are attached to the indicated PCI bus. The PCI bus | |
1042 | * is added after system boot through hotplug or dlpar. | |
1043 | */ | |
1044 | void eeh_add_sysfs_files(struct pci_bus *bus) | |
1045 | { | |
1046 | struct pci_dev *dev; | |
1047 | ||
1048 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1049 | eeh_sysfs_add_device(dev); | |
1050 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1051 | struct pci_bus *subbus = dev->subordinate; | |
1052 | if (subbus) | |
1053 | eeh_add_sysfs_files(subbus); | |
1054 | } | |
1055 | } | |
1056 | } | |
1057 | EXPORT_SYMBOL_GPL(eeh_add_sysfs_files); | |
1058 | ||
1da177e4 | 1059 | /** |
cb3bc9d0 | 1060 | * eeh_remove_device - Undo EEH setup for the indicated pci device |
1da177e4 LT |
1061 | * @dev: pci device to be removed |
1062 | * | |
794e085e NF |
1063 | * This routine should be called when a device is removed from |
1064 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
1065 | * the PCI device from the EEH subsystem. I/O errors affecting | |
1066 | * this device will no longer be detected after this call; thus, | |
1067 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 1068 | */ |
807a827d | 1069 | void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 1070 | { |
f631acd3 GS |
1071 | struct eeh_dev *edev; |
1072 | ||
2ec5a0ad | 1073 | if (!dev || !eeh_enabled()) |
1da177e4 | 1074 | return; |
f631acd3 | 1075 | edev = pci_dev_to_eeh_dev(dev); |
1da177e4 LT |
1076 | |
1077 | /* Unregister the device with the EEH/PCI address search system */ | |
57b066ff | 1078 | pr_debug("EEH: Removing device %s\n", pci_name(dev)); |
56b0fca3 | 1079 | |
f5c57710 | 1080 | if (!edev || !edev->pdev || !edev->pe) { |
57b066ff BH |
1081 | pr_debug("EEH: Not referenced !\n"); |
1082 | return; | |
b055a9e1 | 1083 | } |
f5c57710 GS |
1084 | |
1085 | /* | |
1086 | * During the hotplug for EEH error recovery, we need the EEH | |
1087 | * device attached to the parent PE in order for BAR restore | |
1088 | * a bit later. So we keep it for BAR restore and remove it | |
1089 | * from the parent PE during the BAR resotre. | |
1090 | */ | |
f631acd3 GS |
1091 | edev->pdev = NULL; |
1092 | dev->dev.archdata.edev = NULL; | |
f5c57710 GS |
1093 | if (!(edev->pe->state & EEH_PE_KEEP)) |
1094 | eeh_rmv_from_parent_pe(edev); | |
1095 | else | |
1096 | edev->mode |= EEH_DEV_DISCONNECTED; | |
57b066ff | 1097 | |
f26c7a03 GS |
1098 | /* |
1099 | * We're removing from the PCI subsystem, that means | |
1100 | * the PCI device driver can't support EEH or not | |
1101 | * well. So we rely on hotplug completely to do recovery | |
1102 | * for the specific PCI device. | |
1103 | */ | |
1104 | edev->mode |= EEH_DEV_NO_HANDLER; | |
1105 | ||
3ab96a02 | 1106 | eeh_addr_cache_rmv_dev(dev); |
57b066ff | 1107 | eeh_sysfs_remove_device(dev); |
ab55d218 | 1108 | edev->mode &= ~EEH_DEV_SYSFS; |
1da177e4 | 1109 | } |
1da177e4 LT |
1110 | |
1111 | static int proc_eeh_show(struct seq_file *m, void *v) | |
1112 | { | |
2ec5a0ad | 1113 | if (!eeh_enabled()) { |
1da177e4 | 1114 | seq_printf(m, "EEH Subsystem is globally disabled\n"); |
e575f8db | 1115 | seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs); |
1da177e4 LT |
1116 | } else { |
1117 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 | 1118 | seq_printf(m, |
e575f8db GS |
1119 | "no device=%llu\n" |
1120 | "no device node=%llu\n" | |
1121 | "no config address=%llu\n" | |
1122 | "check not wanted=%llu\n" | |
1123 | "eeh_total_mmio_ffs=%llu\n" | |
1124 | "eeh_false_positives=%llu\n" | |
1125 | "eeh_slot_resets=%llu\n", | |
1126 | eeh_stats.no_device, | |
1127 | eeh_stats.no_dn, | |
1128 | eeh_stats.no_cfg_addr, | |
1129 | eeh_stats.ignored_check, | |
1130 | eeh_stats.total_mmio_ffs, | |
1131 | eeh_stats.false_positives, | |
1132 | eeh_stats.slot_resets); | |
1da177e4 LT |
1133 | } |
1134 | ||
1135 | return 0; | |
1136 | } | |
1137 | ||
1138 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1139 | { | |
1140 | return single_open(file, proc_eeh_show, NULL); | |
1141 | } | |
1142 | ||
5dfe4c96 | 1143 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1144 | .open = proc_eeh_open, |
1145 | .read = seq_read, | |
1146 | .llseek = seq_lseek, | |
1147 | .release = single_release, | |
1148 | }; | |
1149 | ||
7f52a526 GS |
1150 | #ifdef CONFIG_DEBUG_FS |
1151 | static int eeh_enable_dbgfs_set(void *data, u64 val) | |
1152 | { | |
1153 | if (val) | |
1154 | eeh_subsystem_flags &= ~EEH_FORCE_DISABLED; | |
1155 | else | |
1156 | eeh_subsystem_flags |= EEH_FORCE_DISABLED; | |
1157 | ||
1158 | /* Notify the backend */ | |
1159 | if (eeh_ops->post_init) | |
1160 | eeh_ops->post_init(); | |
1161 | ||
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | static int eeh_enable_dbgfs_get(void *data, u64 *val) | |
1166 | { | |
1167 | if (eeh_enabled()) | |
1168 | *val = 0x1ul; | |
1169 | else | |
1170 | *val = 0x0ul; | |
1171 | return 0; | |
1172 | } | |
1173 | ||
1174 | DEFINE_SIMPLE_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get, | |
1175 | eeh_enable_dbgfs_set, "0x%llx\n"); | |
1176 | #endif | |
1177 | ||
1da177e4 LT |
1178 | static int __init eeh_init_proc(void) |
1179 | { | |
7f52a526 | 1180 | if (machine_is(pseries) || machine_is(powernv)) { |
8feaa434 | 1181 | proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations); |
7f52a526 GS |
1182 | #ifdef CONFIG_DEBUG_FS |
1183 | debugfs_create_file("eeh_enable", 0600, | |
1184 | powerpc_debugfs_root, NULL, | |
1185 | &eeh_enable_dbgfs_ops); | |
1186 | #endif | |
1187 | } | |
1188 | ||
1da177e4 LT |
1189 | return 0; |
1190 | } | |
1191 | __initcall(eeh_init_proc); |