[linux-2.6-block.git] / arch / powerpc / include / asm / reg_8xx.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Contains register definitions common to PowerPC 8xx CPUs.  Notice
 */
#ifndef _ASM_POWERPC_REG_8xx_H
#define _ASM_POWERPC_REG_8xx_H

#include <asm/mmu.h>

/* Cache control on the MPC8xx is provided through some additional
 * special purpose registers.
 */
#define SPRN_IC_CST	560	/* Instruction cache control/status */
#define SPRN_IC_ADR	561	/* Address needed for some commands */
#define SPRN_IC_DAT	562	/* Read-only data register */
#define SPRN_DC_CST	568	/* Data cache control/status */
#define SPRN_DC_ADR	569	/* Address needed for some commands */
#define SPRN_DC_DAT	570	/* Read-only data register */

/* Misc Debug */
#define SPRN_DPDR	630
#define SPRN_MI_CAM	816
#define SPRN_MI_RAM0	817
#define SPRN_MI_RAM1	818
#define SPRN_MD_CAM	824
#define SPRN_MD_RAM0	825
#define SPRN_MD_RAM1	826

/* Special MSR manipulation registers */
#define SPRN_EIE	80	/* External interrupt enable (EE=1, RI=1) */
#define SPRN_EID	81	/* External interrupt disable (EE=0, RI=1) */
#define SPRN_NRI	82	/* Non recoverable interrupt (EE=0, RI=0) */

/* Debug registers */
#define SPRN_CMPA	144
#define SPRN_COUNTA	150
#define SPRN_CMPE	152
#define SPRN_CMPF	153
#define SPRN_LCTRL1	156
#define SPRN_LCTRL2	157
#define SPRN_ICTRL	158
#define SPRN_BAR	159

/* Commands.  Only the first few are available to the instruction cache.
*/
#define	IDC_ENABLE	0x02000000	/* Cache enable */
#define IDC_DISABLE	0x04000000	/* Cache disable */
#define IDC_LDLCK	0x06000000	/* Load and lock */
#define IDC_UNLINE	0x08000000	/* Unlock line */
#define IDC_UNALL	0x0a000000	/* Unlock all */
#define IDC_INVALL	0x0c000000	/* Invalidate all */

#define DC_FLINE	0x0e000000	/* Flush data cache line */
#define DC_SFWT		0x01000000	/* Set forced writethrough mode */
#define DC_CFWT		0x03000000	/* Clear forced writethrough mode */
#define DC_SLES		0x05000000	/* Set little endian swap mode */
#define DC_CLES		0x07000000	/* Clear little endian swap mode */

/* Status.
*/
#define IDC_ENABLED	0x80000000	/* Cache is enabled */
#define IDC_CERR1	0x00200000	/* Cache error 1 */
#define IDC_CERR2	0x00100000	/* Cache error 2 */
#define IDC_CERR3	0x00080000	/* Cache error 3 */

#define DC_DFWT		0x40000000	/* Data cache is forced write through */
#define DC_LES		0x20000000	/* Caches are little endian mode */

#endif /* _ASM_POWERPC_REG_8xx_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1da177e4	2	/*
26ef5c09	3	* Contains register definitions common to PowerPC 8xx CPUs. Notice
1da177e4	4	*/
26ef5c09 DG	5	#ifndef _ASM_POWERPC_REG_8xx_H
26ef5c09 DG	6	#define _ASM_POWERPC_REG_8xx_H
1da177e4	7
4b914286	8	#include <asm/mmu.h>
7ee5cf6b	9
1da177e4 LT	10	/* Cache control on the MPC8xx is provided through some additional
	11	* special purpose registers.
	12	*/
	13	#define SPRN_IC_CST 560 /* Instruction cache control/status */
	14	#define SPRN_IC_ADR 561 /* Address needed for some commands */
	15	#define SPRN_IC_DAT 562 /* Read-only data register */
	16	#define SPRN_DC_CST 568 /* Data cache control/status */
	17	#define SPRN_DC_ADR 569 /* Address needed for some commands */
	18	#define SPRN_DC_DAT 570 /* Read-only data register */
	19
7ee5cf6b CL	20	/* Misc Debug */
	21	#define SPRN_DPDR 630
	22	#define SPRN_MI_CAM 816
	23	#define SPRN_MI_RAM0 817
	24	#define SPRN_MI_RAM1 818
	25	#define SPRN_MD_CAM 824
	26	#define SPRN_MD_RAM0 825
	27	#define SPRN_MD_RAM1 826
	28
834e5a69 CL	29	/* Special MSR manipulation registers */
	30	#define SPRN_EIE 80 /* External interrupt enable (EE=1, RI=1) */
	31	#define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
75b82472	32	#define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */
834e5a69	33
4ad8622d	34	/* Debug registers */
75b82472 CL	35	#define SPRN_CMPA 144
75b82472 CL	36	#define SPRN_COUNTA 150
4ad8622d CL	37	#define SPRN_CMPE 152
	38	#define SPRN_CMPF 153
	39	#define SPRN_LCTRL1 156
	40	#define SPRN_LCTRL2 157
75b82472	41	#define SPRN_ICTRL 158
4ad8622d CL	42	#define SPRN_BAR 159
4ad8622d CL	43
1da177e4 LT	44	/* Commands. Only the first few are available to the instruction cache.
	45	*/
	46	#define IDC_ENABLE 0x02000000 /* Cache enable */
	47	#define IDC_DISABLE 0x04000000 /* Cache disable */
	48	#define IDC_LDLCK 0x06000000 /* Load and lock */
	49	#define IDC_UNLINE 0x08000000 /* Unlock line */
	50	#define IDC_UNALL 0x0a000000 /* Unlock all */
	51	#define IDC_INVALL 0x0c000000 /* Invalidate all */
	52
	53	#define DC_FLINE 0x0e000000 /* Flush data cache line */
	54	#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
	55	#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
	56	#define DC_SLES 0x05000000 /* Set little endian swap mode */
	57	#define DC_CLES 0x07000000 /* Clear little endian swap mode */
	58
	59	/* Status.
	60	*/
	61	#define IDC_ENABLED 0x80000000 /* Cache is enabled */
	62	#define IDC_CERR1 0x00200000 /* Cache error 1 */
	63	#define IDC_CERR2 0x00100000 /* Cache error 2 */
	64	#define IDC_CERR3 0x00080000 /* Cache error 3 */
	65
	66	#define DC_DFWT 0x40000000 /* Data cache is forced write through */
	67	#define DC_LES 0x20000000 /* Caches are little endian mode */
1da177e4	68
26ef5c09	69	#endif /* _ASM_POWERPC_REG_8xx_H */