[linux-2.6-block.git] / arch / powerpc / include / asm / paca.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * This control block defines the PACA which defines the processor
 * specific data for each logical processor on the system.
 * There are some pointers defined that are utilized by PLIC.
 *
 * C 2001 PPC 64 Team, IBM Corp
 */
#ifndef _ASM_POWERPC_PACA_H
#define _ASM_POWERPC_PACA_H
#ifdef __KERNEL__

#ifdef CONFIG_PPC64

#include <linux/string.h>
#include <asm/types.h>
#include <asm/lppaca.h>
#include <asm/mmu.h>
#include <asm/page.h>
#ifdef CONFIG_PPC_BOOK3E
#include <asm/exception-64e.h>
#else
#include <asm/exception-64s.h>
#endif
#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
#include <asm/kvm_book3s_asm.h>
#endif
#include <asm/accounting.h>
#include <asm/hmi.h>
#include <asm/cpuidle.h>
#include <asm/atomic.h>

#include <asm-generic/mmiowb_types.h>

register struct paca_struct *local_paca asm("r13");

#if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
/*
 * Add standard checks that preemption cannot occur when using get_paca():
 * otherwise the paca_struct it points to may be the wrong one just after.
 */
#define get_paca()	((void) debug_smp_processor_id(), local_paca)
#else
#define get_paca()	local_paca
#endif

#ifdef CONFIG_PPC_PSERIES
#define get_lppaca()	(get_paca()->lppaca_ptr)
#endif

#define get_slb_shadow()	(get_paca()->slb_shadow_ptr)

struct task_struct;

/*
 * Defines the layout of the paca.
 *
 * This structure is not directly accessed by firmware or the service
 * processor.
 */
struct paca_struct {
#ifdef CONFIG_PPC_PSERIES
	/*
	 * Because hw_cpu_id, unlike other paca fields, is accessed
	 * routinely from other CPUs (from the IRQ code), we stick to
	 * read-only (after boot) fields in the first cacheline to
	 * avoid cacheline bouncing.
	 */

	struct lppaca *lppaca_ptr;	/* Pointer to LpPaca for PLIC */
#endif /* CONFIG_PPC_PSERIES */

	/*
	 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c 
	 * load lock_token and paca_index with a single lwz
	 * instruction.  They must travel together and be properly
	 * aligned.
	 */
#ifdef __BIG_ENDIAN__
	u16 lock_token;			/* Constant 0x8000, used in locks */
	u16 paca_index;			/* Logical processor number */
#else
	u16 paca_index;			/* Logical processor number */
	u16 lock_token;			/* Constant 0x8000, used in locks */
#endif

	u64 kernel_toc;			/* Kernel TOC address */
	u64 kernelbase;			/* Base address of kernel */
	u64 kernel_msr;			/* MSR while running in kernel */
	void *emergency_sp;		/* pointer to emergency stack */
	u64 data_offset;		/* per cpu data offset */
	s16 hw_cpu_id;			/* Physical processor number */
	u8 cpu_start;			/* At startup, processor spins until */
					/* this becomes non-zero. */
	u8 kexec_state;		/* set when kexec down has irqs off */
#ifdef CONFIG_PPC_BOOK3S_64
	struct slb_shadow *slb_shadow_ptr;
	struct dtl_entry *dispatch_log;
	struct dtl_entry *dispatch_log_end;
#endif
	u64 dscr_default;		/* per-CPU default DSCR */

#ifdef CONFIG_PPC_BOOK3S_64
	/*
	 * Now, starting in cacheline 2, the exception save areas
	 */
	/* used for most interrupts/exceptions */
	u64 exgen[EX_SIZE] __attribute__((aligned(0x80)));
	u64 exslb[EX_SIZE];	/* used for SLB/segment table misses
 				 * on the linear mapping */
	/* SLB related definitions */
	u16 vmalloc_sllp;
	u8 slb_cache_ptr;
	u8 stab_rr;			/* stab/slb round-robin counter */
#ifdef CONFIG_DEBUG_VM
	u8 in_kernel_slb_handler;
#endif
	u32 slb_used_bitmap;		/* Bitmaps for first 32 SLB entries. */
	u32 slb_kern_bitmap;
	u32 slb_cache[SLB_CACHE_ENTRIES];
#endif /* CONFIG_PPC_BOOK3S_64 */

#ifdef CONFIG_PPC_BOOK3E
	u64 exgen[8] __aligned(0x40);
	/* Keep pgd in the same cacheline as the start of extlb */
	pgd_t *pgd __aligned(0x40); /* Current PGD */
	pgd_t *kernel_pgd;		/* Kernel PGD */

	/* Shared by all threads of a core -- points to tcd of first thread */
	struct tlb_core_data *tcd_ptr;

	/*
	 * We can have up to 3 levels of reentrancy in the TLB miss handler,
	 * in each of four exception levels (normal, crit, mcheck, debug).
	 */
	u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
	u64 exmc[8];		/* used for machine checks */
	u64 excrit[8];		/* used for crit interrupts */
	u64 exdbg[8];		/* used for debug interrupts */

	/* Kernel stack pointers for use by special exceptions */
	void *mc_kstack;
	void *crit_kstack;
	void *dbg_kstack;

	struct tlb_core_data tcd;
#endif /* CONFIG_PPC_BOOK3E */

#ifdef CONFIG_PPC_BOOK3S
	mm_context_id_t mm_ctx_id;
#ifdef CONFIG_PPC_MM_SLICES
	unsigned char mm_ctx_low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE];
	unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE];
	unsigned long mm_ctx_slb_addr_limit;
#else
	u16 mm_ctx_user_psize;
	u16 mm_ctx_sllp;
#endif
#endif

	/*
	 * then miscellaneous read-write fields
	 */
	struct task_struct *__current;	/* Pointer to current */
	u64 kstack;			/* Saved Kernel stack addr */
	u64 saved_r1;			/* r1 save for RTAS calls or PM or EE=0 */
	u64 saved_msr;			/* MSR saved here by enter_rtas */
#ifdef CONFIG_PPC_BOOK3E
	u16 trap_save;			/* Used when bad stack is encountered */
#endif
	u8 irq_soft_mask;		/* mask for irq soft masking */
	u8 irq_happened;		/* irq happened while soft-disabled */
	u8 irq_work_pending;		/* IRQ_WORK interrupt while soft-disable */
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	u8 pmcregs_in_use;		/* pseries puts this in lppaca */
#endif
	u64 sprg_vdso;			/* Saved user-visible sprg */
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
	u64 tm_scratch;                 /* TM scratch area for reclaim */
#endif

#ifdef CONFIG_PPC_POWERNV
	/* PowerNV idle fields */
	/* PNV_CORE_IDLE_* bits, all siblings work on thread 0 paca */
	unsigned long idle_state;
	union {
		/* P7/P8 specific fields */
		struct {
			/* PNV_THREAD_RUNNING/NAP/SLEEP	*/
			u8 thread_idle_state;
			/* Mask to denote subcore sibling threads */
			u8 subcore_sibling_mask;
		};

		/* P9 specific fields */
		struct {
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
			/* The PSSCR value that the kernel requested before going to stop */
			u64 requested_psscr;
			/* Flag to request this thread not to stop */
			atomic_t dont_stop;
#endif
		};
	};
#endif

#ifdef CONFIG_PPC_BOOK3S_64
	/* Non-maskable exceptions that are not performance critical */
	u64 exnmi[EX_SIZE];	/* used for system reset (nmi) */
	u64 exmc[EX_SIZE];	/* used for machine checks */
#endif
#ifdef CONFIG_PPC_BOOK3S_64
	/* Exclusive stacks for system reset and machine check exception. */
	void *nmi_emergency_sp;
	void *mc_emergency_sp;

	u16 in_nmi;			/* In nmi handler */

	/*
	 * Flag to check whether we are in machine check early handler
	 * and already using emergency stack.
	 */
	u16 in_mce;
	u8 hmi_event_available;		/* HMI event is available */
	u8 hmi_p9_special_emu;		/* HMI P9 special emulation */
#endif
	u8 ftrace_enabled;		/* Hard disable ftrace */

	/* Stuff for accurate time accounting */
	struct cpu_accounting_data accounting;
	u64 dtl_ridx;			/* read index in dispatch log */
	struct dtl_entry *dtl_curr;	/* pointer corresponding to dtl_ridx */

#ifdef CONFIG_KVM_BOOK3S_HANDLER
#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
	/* We use this to store guest state in */
	struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
#endif
	struct kvmppc_host_state kvm_hstate;
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	/*
	 * Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for
	 * more details
	 */
	struct sibling_subcore_state *sibling_subcore_state;
#endif
#endif
#ifdef CONFIG_PPC_BOOK3S_64
	/*
	 * rfi fallback flush must be in its own cacheline to prevent
	 * other paca data leaking into the L1d
	 */
	u64 exrfi[EX_SIZE] __aligned(0x80);
	void *rfi_flush_fallback_area;
	u64 l1d_flush_size;
#endif
#ifdef CONFIG_PPC_PSERIES
	u8 *mce_data_buf;		/* buffer to hold per cpu rtas errlog */
#endif /* CONFIG_PPC_PSERIES */

#ifdef CONFIG_PPC_BOOK3S_64
	/* Capture SLB related old contents in MCE handler. */
	struct slb_entry *mce_faulty_slbs;
	u16 slb_save_cache_ptr;
#endif /* CONFIG_PPC_BOOK3S_64 */
#ifdef CONFIG_STACKPROTECTOR
	unsigned long canary;
#endif
#ifdef CONFIG_MMIOWB
	struct mmiowb_state mmiowb_state;
#endif
} ____cacheline_aligned;

extern void copy_mm_to_paca(struct mm_struct *mm);
extern struct paca_struct **paca_ptrs;
extern void initialise_paca(struct paca_struct *new_paca, int cpu);
extern void setup_paca(struct paca_struct *new_paca);
extern void allocate_paca_ptrs(void);
extern void allocate_paca(int cpu);
extern void free_unused_pacas(void);

#else /* CONFIG_PPC64 */

static inline void allocate_paca_ptrs(void) { };
static inline void allocate_paca(int cpu) { };
static inline void free_unused_pacas(void) { };

#endif /* CONFIG_PPC64 */

#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PACA_H */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
1da177e4	2	/*
8882a4da DG	3	* This control block defines the PACA which defines the processor
8882a4da DG	4	* specific data for each logical processor on the system.
1da177e4 LT	5	* There are some pointers defined that are utilized by PLIC.
	6	*
	7	* C 2001 PPC 64 Team, IBM Corp
8882a4da DG	8	*/
	9	#ifndef _ASM_POWERPC_PACA_H
	10	#define _ASM_POWERPC_PACA_H
88ced031	11	#ifdef __KERNEL__
1da177e4	12
1426d5a3 ME	13	#ifdef CONFIG_PPC64
1426d5a3 ME	14
2fc251a8	15	#include <linux/string.h>
dce6670a BH	16	#include <asm/types.h>
	17	#include <asm/lppaca.h>
	18	#include <asm/mmu.h>
	19	#include <asm/page.h>
8c388514	20	#ifdef CONFIG_PPC_BOOK3E
dce6670a	21	#include <asm/exception-64e.h>
8c388514 NP	22	#else
	23	#include <asm/exception-64s.h>
	24	#endif
7e57cba0	25	#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
2191d657	26	#include <asm/kvm_book3s_asm.h>
7e57cba0	27	#endif
c223c903	28	#include <asm/accounting.h>
fd7bacbc	29	#include <asm/hmi.h>
e1c1cfed	30	#include <asm/cpuidle.h>
7672691a	31	#include <asm/atomic.h>
1da177e4	32
420af155 WD	33	#include <asm-generic/mmiowb_types.h>
420af155 WD	34
1da177e4	35	register struct paca_struct *local_paca asm("r13");
048c8bc9 HD	36
	37	#if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
	38	extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
	39	/*
	40	* Add standard checks that preemption cannot occur when using get_paca():
	41	* otherwise the paca_struct it points to may be the wrong one just after.
	42	*/
	43	#define get_paca() ((void) debug_smp_processor_id(), local_paca)
	44	#else
1da177e4	45	#define get_paca() local_paca
048c8bc9 HD	46	#endif
048c8bc9 HD	47
8e0b634b	48	#ifdef CONFIG_PPC_PSERIES
3356bb9f	49	#define get_lppaca() (get_paca()->lppaca_ptr)
8e0b634b NP	50	#endif
8e0b634b NP	51
2f6093c8	52	#define get_slb_shadow() (get_paca()->slb_shadow_ptr)
1da177e4 LT	53
1da177e4 LT	54	struct task_struct;
1da177e4 LT	55
	56	/*
	57	* Defines the layout of the paca.
	58	*
	59	* This structure is not directly accessed by firmware or the service
30ff2e87	60	* processor.
1da177e4 LT	61	*/
1da177e4 LT	62	struct paca_struct {
8e0b634b	63	#ifdef CONFIG_PPC_PSERIES
1da177e4 LT	64	/*
	65	* Because hw_cpu_id, unlike other paca fields, is accessed
	66	* routinely from other CPUs (from the IRQ code), we stick to
	67	* read-only (after boot) fields in the first cacheline to
	68	* avoid cacheline bouncing.
	69	*/
	70
1da177e4	71	struct lppaca lppaca_ptr; / Pointer to LpPaca for PLIC */
8e0b634b NP	72	#endif /* CONFIG_PPC_PSERIES */
8e0b634b NP	73
1da177e4	74	/*
2ef9481e	75	* MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
1da177e4 LT	76	* load lock_token and paca_index with a single lwz
	77	* instruction. They must travel together and be properly
	78	* aligned.
	79	*/
54bb7f4b	80	#ifdef __BIG_ENDIAN__
1da177e4 LT	81	u16 lock_token; /* Constant 0x8000, used in locks */
1da177e4 LT	82	u16 paca_index; /* Logical processor number */
54bb7f4b AB	83	#else
	84	u16 paca_index; /* Logical processor number */
	85	u16 lock_token; /* Constant 0x8000, used in locks */
	86	#endif
1da177e4	87
1da177e4	88	u64 kernel_toc; /* Kernel TOC address */
1f6a93e4 PM	89	u64 kernelbase; /* Base address of kernel */
1f6a93e4 PM	90	u64 kernel_msr; /* MSR while running in kernel */
1da177e4	91	void emergency_sp; / pointer to emergency stack */
7a0268fa	92	u64 data_offset; /* per cpu data offset */
1da177e4 LT	93	s16 hw_cpu_id; /* Physical processor number */
	94	u8 cpu_start; /* At startup, processor spins until */
	95	/* this becomes non-zero. */
1fc711f7	96	u8 kexec_state; /* set when kexec down has irqs off */
4e003747	97	#ifdef CONFIG_PPC_BOOK3S_64
e91948fd	98	struct slb_shadow *slb_shadow_ptr;
cf9efce0 PM	99	struct dtl_entry *dispatch_log;
cf9efce0 PM	100	struct dtl_entry *dispatch_log_end;
4e003747	101	#endif
1739ea9e	102	u64 dscr_default; /* per-CPU default DSCR */
1da177e4	103
4e003747	104	#ifdef CONFIG_PPC_BOOK3S_64
1da177e4 LT	105	/*
	106	* Now, starting in cacheline 2, the exception save areas
	107	*/
3c726f8d	108	/* used for most interrupts/exceptions */
8c388514 NP	109	u64 exgen[EX_SIZE] __attribute__((aligned(0x80)));
8c388514 NP	110	u64 exslb[EX_SIZE]; /* used for SLB/segment table misses
3c726f8d	111	* on the linear mapping */
91c60b5b	112	/* SLB related definitions */
bf72aeba	113	u16 vmalloc_sllp;
126b11b2 NP	114	u8 slb_cache_ptr;
126b11b2 NP	115	u8 stab_rr; /* stab/slb round-robin counter */
e15a4fea NP	116	#ifdef CONFIG_DEBUG_VM
	117	u8 in_kernel_slb_handler;
	118	#endif
126b11b2 NP	119	u32 slb_used_bitmap; /* Bitmaps for first 32 SLB entries. */
126b11b2 NP	120	u32 slb_kern_bitmap;
735cafc3	121	u32 slb_cache[SLB_CACHE_ENTRIES];
4e003747	122	#endif /* CONFIG_PPC_BOOK3S_64 */
91c60b5b	123
dce6670a	124	#ifdef CONFIG_PPC_BOOK3E
016f8cf0	125	u64 exgen[8] __aligned(0x40);
f67f4ef5	126	/* Keep pgd in the same cacheline as the start of extlb */
016f8cf0	127	pgd_t pgd __aligned(0x40); / Current PGD */
f67f4ef5	128	pgd_t kernel_pgd; / Kernel PGD */
28efc35f SW	129
	130	/* Shared by all threads of a core -- points to tcd of first thread */
	131	struct tlb_core_data *tcd_ptr;
	132
609af38f SW	133	/*
	134	* We can have up to 3 levels of reentrancy in the TLB miss handler,
	135	* in each of four exception levels (normal, crit, mcheck, debug).
	136	*/
	137	u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
dce6670a BH	138	u64 exmc[8]; /* used for machine checks */
	139	u64 excrit[8]; /* used for crit interrupts */
	140	u64 exdbg[8]; /* used for debug interrupts */
	141
	142	/* Kernel stack pointers for use by special exceptions */
	143	void *mc_kstack;
	144	void *crit_kstack;
	145	void *dbg_kstack;
28efc35f SW	146
28efc35f SW	147	struct tlb_core_data tcd;
dce6670a BH	148	#endif /* CONFIG_PPC_BOOK3E */
dce6670a BH	149
54be0b9c ME	150	#ifdef CONFIG_PPC_BOOK3S
	151	mm_context_id_t mm_ctx_id;
	152	#ifdef CONFIG_PPC_MM_SLICES
	153	unsigned char mm_ctx_low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE];
	154	unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE];
	155	unsigned long mm_ctx_slb_addr_limit;
	156	#else
	157	u16 mm_ctx_user_psize;
	158	u16 mm_ctx_sllp;
	159	#endif
	160	#endif
	161
1da177e4 LT	162	/*
	163	* then miscellaneous read-write fields
	164	*/
	165	struct task_struct __current; / Pointer to current */
	166	u64 kstack; /* Saved Kernel stack addr */
7b08729c	167	u64 saved_r1; /* r1 save for RTAS calls or PM or EE=0 */
1da177e4	168	u64 saved_msr; /* MSR saved here by enter_rtas */
0a882e28	169	#ifdef CONFIG_PPC_BOOK3E
68730401	170	u16 trap_save; /* Used when bad stack is encountered */
0a882e28	171	#endif
4e26bc4a	172	u8 irq_soft_mask; /* mask for irq soft masking */
7230c564	173	u8 irq_happened; /* irq happened while soft-disabled */
e360adbe	174	u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
8e0b634b NP	175	#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	176	u8 pmcregs_in_use; /* pseries puts this in lppaca */
	177	#endif
9d378dfa	178	u64 sprg_vdso; /* Saved user-visible sprg */
afc07701 MN	179	#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
	180	u64 tm_scratch; /* TM scratch area for reclaim */
	181	#endif
c6622f63	182
7cba160a	183	#ifdef CONFIG_PPC_POWERNV
10d91611 NP	184	/* PowerNV idle fields */
	185	/* PNV_CORE_IDLE_* bits, all siblings work on thread 0 paca */
	186	unsigned long idle_state;
	187	union {
	188	/* P7/P8 specific fields */
	189	struct {
	190	/* PNV_THREAD_RUNNING/NAP/SLEEP */
	191	u8 thread_idle_state;
	192	/* Mask to denote subcore sibling threads */
	193	u8 subcore_sibling_mask;
	194	};
	195
	196	/* P9 specific fields */
	197	struct {
	198	#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	199	/* The PSSCR value that the kernel requested before going to stop */
	200	u64 requested_psscr;
	201	/* Flag to request this thread not to stop */
	202	atomic_t dont_stop;
	203	#endif
	204	};
	205	};
7cba160a SP	206	#endif
7cba160a SP	207
4e003747	208	#ifdef CONFIG_PPC_BOOK3S_64
a3d96f70	209	/* Non-maskable exceptions that are not performance critical */
8c388514 NP	210	u64 exnmi[EX_SIZE]; /* used for system reset (nmi) */
8c388514 NP	211	u64 exmc[EX_SIZE]; /* used for machine checks */
a3d96f70	212	#endif
729b0f71	213	#ifdef CONFIG_PPC_BOOK3S_64
b1ee8a3d NP	214	/* Exclusive stacks for system reset and machine check exception. */
b1ee8a3d NP	215	void *nmi_emergency_sp;
729b0f71	216	void *mc_emergency_sp;
c4f3b52c NP	217
	218	u16 in_nmi; /* In nmi handler */
	219
729b0f71 MS	220	/*
	221	* Flag to check whether we are in machine check early handler
	222	* and already using emergency stack.
	223	*/
	224	u16 in_mce;
c4f3b52c	225	u8 hmi_event_available; /* HMI event is available */
5080332c	226	u8 hmi_p9_special_emu; /* HMI P9 special emulation */
729b0f71	227	#endif
ea678ac6	228	u8 ftrace_enabled; /* Hard disable ftrace */
ed79ba9e	229
c6622f63	230	/* Stuff for accurate time accounting */
c223c903	231	struct cpu_accounting_data accounting;
cf9efce0 PM	232	u64 dtl_ridx; /* read index in dispatch log */
cf9efce0 PM	233	struct dtl_entry dtl_curr; / pointer corresponding to dtl_ridx */
4b7ae55d	234
c14dea04	235	#ifdef CONFIG_KVM_BOOK3S_HANDLER
7aa79938	236	#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
7e57cba0 AG	237	/* We use this to store guest state in */
7e57cba0 AG	238	struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
de56a948	239	#endif
3c42bf8a	240	struct kvmppc_host_state kvm_hstate;
7c379526 PB	241	#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	242	/*
	243	* Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for
	244	* more details
	245	*/
	246	struct sibling_subcore_state *sibling_subcore_state;
	247	#endif
4b7ae55d	248	#endif
aa8a5e00 ME	249	#ifdef CONFIG_PPC_BOOK3S_64
	250	/*
	251	* rfi fallback flush must be in its own cacheline to prevent
	252	* other paca data leaking into the L1d
	253	*/
	254	u64 exrfi[EX_SIZE] __aligned(0x80);
	255	void *rfi_flush_fallback_area;
bdcb1aef	256	u64 l1d_flush_size;
aa8a5e00	257	#endif
94675cce MS	258	#ifdef CONFIG_PPC_PSERIES
	259	u8 mce_data_buf; / buffer to hold per cpu rtas errlog */
	260	#endif /* CONFIG_PPC_PSERIES */
c6d15258 MS	261
	262	#ifdef CONFIG_PPC_BOOK3S_64
	263	/* Capture SLB related old contents in MCE handler. */
	264	struct slb_entry *mce_faulty_slbs;
	265	u16 slb_save_cache_ptr;
	266	#endif /* CONFIG_PPC_BOOK3S_64 */
06ec27ae CL	267	#ifdef CONFIG_STACKPROTECTOR
	268	unsigned long canary;
	269	#endif
420af155 WD	270	#ifdef CONFIG_MMIOWB
	271	struct mmiowb_state mmiowb_state;
	272	#endif
d2e60075	273	} ____cacheline_aligned;
1da177e4	274
54be0b9c	275	extern void copy_mm_to_paca(struct mm_struct *mm);
d2e60075	276	extern struct paca_struct **paca_ptrs;
1426d5a3	277	extern void initialise_paca(struct paca_struct *new_paca, int cpu);
fc53b420	278	extern void setup_paca(struct paca_struct *new_paca);
59f57774 NP	279	extern void allocate_paca_ptrs(void);
59f57774 NP	280	extern void allocate_paca(int cpu);
1426d5a3 ME	281	extern void free_unused_pacas(void);
	282
	283	#else /* CONFIG_PPC64 */
	284
59f57774 NP	285	static inline void allocate_paca_ptrs(void) { };
59f57774 NP	286	static inline void allocate_paca(int cpu) { };
1426d5a3 ME	287	static inline void free_unused_pacas(void) { };
	288
	289	#endif /* CONFIG_PPC64 */
1da177e4	290
88ced031	291	#endif /* __KERNEL__ */
8882a4da	292	#endif /* _ASM_POWERPC_PACA_H */