[linux-2.6-block.git] / arch / powerpc / include / asm / immap_cpm2.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * CPM2 Internal Memory Map
 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
 *
 * The Internal Memory Map for devices with CPM2 on them.  This
 * is the superset of all CPM2 devices (8260, 8266, 8280, 8272,
 * 8560).
 */
#ifdef __KERNEL__
#ifndef __IMMAP_CPM2__
#define __IMMAP_CPM2__

#include <linux/types.h>

/* System configuration registers.
*/
typedef	struct sys_82xx_conf {
	u32	sc_siumcr;
	u32	sc_sypcr;
	u8	res1[6];
	u16	sc_swsr;
	u8	res2[20];
	u32	sc_bcr;
	u8	sc_ppc_acr;
	u8	res3[3];
	u32	sc_ppc_alrh;
	u32	sc_ppc_alrl;
	u8	sc_lcl_acr;
	u8	res4[3];
	u32	sc_lcl_alrh;
	u32	sc_lcl_alrl;
	u32	sc_tescr1;
	u32	sc_tescr2;
	u32	sc_ltescr1;
	u32	sc_ltescr2;
	u32	sc_pdtea;
	u8	sc_pdtem;
	u8	res5[3];
	u32	sc_ldtea;
	u8	sc_ldtem;
	u8	res6[163];
} sysconf_82xx_cpm2_t;

typedef	struct sys_85xx_conf {
	u32	sc_cear;
	u16	sc_ceer;
	u16	sc_cemr;
	u8	res1[70];
	u32	sc_smaer;
	u8	res2[4];
	u32	sc_smevr;
	u32	sc_smctr;
	u32	sc_lmaer;
	u8	res3[4];
	u32	sc_lmevr;
	u32	sc_lmctr;
	u8	res4[144];
} sysconf_85xx_cpm2_t;

typedef union sys_conf {
	sysconf_82xx_cpm2_t	siu_82xx;
	sysconf_85xx_cpm2_t	siu_85xx;
} sysconf_cpm2_t;


/* Memory controller registers.
*/
typedef struct	mem_ctlr {
	u32	memc_br0;
	u32	memc_or0;
	u32	memc_br1;
	u32	memc_or1;
	u32	memc_br2;
	u32	memc_or2;
	u32	memc_br3;
	u32	memc_or3;
	u32	memc_br4;
	u32	memc_or4;
	u32	memc_br5;
	u32	memc_or5;
	u32	memc_br6;
	u32	memc_or6;
	u32	memc_br7;
	u32	memc_or7;
	u32	memc_br8;
	u32	memc_or8;
	u32	memc_br9;
	u32	memc_or9;
	u32	memc_br10;
	u32	memc_or10;
	u32	memc_br11;
	u32	memc_or11;
	u8	res1[8];
	u32	memc_mar;
	u8	res2[4];
	u32	memc_mamr;
	u32	memc_mbmr;
	u32	memc_mcmr;
	u8	res3[8];
	u16	memc_mptpr;
	u8	res4[2];
	u32	memc_mdr;
	u8	res5[4];
	u32	memc_psdmr;
	u32	memc_lsdmr;
	u8	memc_purt;
	u8	res6[3];
	u8	memc_psrt;
	u8	res7[3];
	u8	memc_lurt;
	u8	res8[3];
	u8	memc_lsrt;
	u8	res9[3];
	u32	memc_immr;
	u32	memc_pcibr0;
	u32	memc_pcibr1;
	u8	res10[16];
	u32	memc_pcimsk0;
	u32	memc_pcimsk1;
	u8	res11[52];
} memctl_cpm2_t;

/* System Integration Timers.
*/
typedef struct	sys_int_timers {
	u8	res1[32];
	u16	sit_tmcntsc;
	u8	res2[2];
	u32	sit_tmcnt;
	u8	res3[4];
	u32	sit_tmcntal;
	u8	res4[16];
	u16	sit_piscr;
	u8	res5[2];
	u32	sit_pitc;
	u32	sit_pitr;
	u8      res6[94];
	u8	res7[390];
} sit_cpm2_t;

#define PISCR_PIRQ_MASK		((u16)0xff00)
#define PISCR_PS		((u16)0x0080)
#define PISCR_PIE		((u16)0x0004)
#define PISCR_PTF		((u16)0x0002)
#define PISCR_PTE		((u16)0x0001)

/* PCI Controller.
*/
typedef struct pci_ctlr {
	u32	pci_omisr;
	u32	pci_omimr;
	u8	res1[8];
	u32	pci_ifqpr;
	u32	pci_ofqpr;
	u8	res2[8];
	u32	pci_imr0;
	u32	pci_imr1;
	u32	pci_omr0;
	u32	pci_omr1;
	u32	pci_odr;
	u8	res3[4];
	u32	pci_idr;
	u8	res4[20];
	u32	pci_imisr;
	u32	pci_imimr;
	u8	res5[24];
	u32	pci_ifhpr;
	u8	res6[4];
	u32	pci_iftpr;
	u8	res7[4];
	u32	pci_iphpr;
	u8	res8[4];
	u32	pci_iptpr;
	u8	res9[4];
	u32	pci_ofhpr;
	u8	res10[4];
	u32	pci_oftpr;
	u8	res11[4];
	u32	pci_ophpr;
	u8	res12[4];
	u32	pci_optpr;
	u8	res13[8];
	u32	pci_mucr;
	u8	res14[8];
	u32	pci_qbar;
	u8	res15[12];
	u32	pci_dmamr0;
	u32	pci_dmasr0;
	u32	pci_dmacdar0;
	u8	res16[4];
	u32	pci_dmasar0;
	u8	res17[4];
	u32	pci_dmadar0;
	u8	res18[4];
	u32	pci_dmabcr0;
	u32	pci_dmandar0;
	u8	res19[86];
	u32	pci_dmamr1;
	u32	pci_dmasr1;
	u32	pci_dmacdar1;
	u8	res20[4];
	u32	pci_dmasar1;
	u8	res21[4];
	u32	pci_dmadar1;
	u8	res22[4];
	u32	pci_dmabcr1;
	u32	pci_dmandar1;
	u8	res23[88];
	u32	pci_dmamr2;
	u32	pci_dmasr2;
	u32	pci_dmacdar2;
	u8	res24[4];
	u32	pci_dmasar2;
	u8	res25[4];
	u32	pci_dmadar2;
	u8	res26[4];
	u32	pci_dmabcr2;
	u32	pci_dmandar2;
	u8	res27[88];
	u32	pci_dmamr3;
	u32	pci_dmasr3;
	u32	pci_dmacdar3;
	u8	res28[4];
	u32	pci_dmasar3;
	u8	res29[4];
	u32	pci_dmadar3;
	u8	res30[4];
	u32	pci_dmabcr3;
	u32	pci_dmandar3;
	u8	res31[344];
	u32	pci_potar0;
	u8	res32[4];
	u32	pci_pobar0;
	u8	res33[4];
	u32	pci_pocmr0;
	u8	res34[4];
	u32	pci_potar1;
	u8	res35[4];
	u32	pci_pobar1;
	u8	res36[4];
	u32	pci_pocmr1;
	u8	res37[4];
	u32	pci_potar2;
	u8	res38[4];
	u32	pci_pobar2;
	u8	res39[4];
	u32	pci_pocmr2;
	u8	res40[50];
	u32	pci_ptcr;
	u32	pci_gpcr;
	u32	pci_gcr;
	u32	pci_esr;
	u32	pci_emr;
	u32	pci_ecr;
	u32	pci_eacr;
	u8	res41[4];
	u32	pci_edcr;
	u8	res42[4];
	u32	pci_eccr;
	u8	res43[44];
	u32	pci_pitar1;
	u8	res44[4];
	u32	pci_pibar1;
	u8	res45[4];
	u32	pci_picmr1;
	u8	res46[4];
	u32	pci_pitar0;
	u8	res47[4];
	u32	pci_pibar0;
	u8	res48[4];
	u32	pci_picmr0;
	u8	res49[4];
	u32	pci_cfg_addr;
	u32	pci_cfg_data;
	u32	pci_int_ack;
	u8	res50[756];
} pci_cpm2_t;

/* Interrupt Controller.
*/
typedef struct interrupt_controller {
	u16	ic_sicr;
	u8	res1[2];
	u32	ic_sivec;
	u32	ic_sipnrh;
	u32	ic_sipnrl;
	u32	ic_siprr;
	u32	ic_scprrh;
	u32	ic_scprrl;
	u32	ic_simrh;
	u32	ic_simrl;
	u32	ic_siexr;
	u8	res2[88];
} intctl_cpm2_t;

/* Clocks and Reset.
*/
typedef struct clk_and_reset {
	u32	car_sccr;
	u8	res1[4];
	u32	car_scmr;
	u8	res2[4];
	u32	car_rsr;
	u32	car_rmr;
	u8	res[104];
} car_cpm2_t;

/* Input/Output Port control/status registers.
 * Names consistent with processor manual, although they are different
 * from the original 8xx names.......
 */
typedef struct io_port {
	u32	iop_pdira;
	u32	iop_ppara;
	u32	iop_psora;
	u32	iop_podra;
	u32	iop_pdata;
	u8	res1[12];
	u32	iop_pdirb;
	u32	iop_pparb;
	u32	iop_psorb;
	u32	iop_podrb;
	u32	iop_pdatb;
	u8	res2[12];
	u32	iop_pdirc;
	u32	iop_pparc;
	u32	iop_psorc;
	u32	iop_podrc;
	u32	iop_pdatc;
	u8	res3[12];
	u32	iop_pdird;
	u32	iop_ppard;
	u32	iop_psord;
	u32	iop_podrd;
	u32	iop_pdatd;
	u8	res4[12];
} iop_cpm2_t;

/* Communication Processor Module Timers
*/
typedef struct cpm_timers {
	u8	cpmt_tgcr1;
	u8	res1[3];
	u8	cpmt_tgcr2;
	u8	res2[11];
	u16	cpmt_tmr1;
	u16	cpmt_tmr2;
	u16	cpmt_trr1;
	u16	cpmt_trr2;
	u16	cpmt_tcr1;
	u16	cpmt_tcr2;
	u16	cpmt_tcn1;
	u16	cpmt_tcn2;
	u16	cpmt_tmr3;
	u16	cpmt_tmr4;
	u16	cpmt_trr3;
	u16	cpmt_trr4;
	u16	cpmt_tcr3;
	u16	cpmt_tcr4;
	u16	cpmt_tcn3;
	u16	cpmt_tcn4;
	u16	cpmt_ter1;
	u16	cpmt_ter2;
	u16	cpmt_ter3;
	u16	cpmt_ter4;
	u8	res3[584];
} cpmtimer_cpm2_t;

/* DMA control/status registers.
*/
typedef struct sdma_csr {
	u8	res0[24];
	u8	sdma_sdsr;
	u8	res1[3];
	u8	sdma_sdmr;
	u8	res2[3];
	u8	sdma_idsr1;
	u8	res3[3];
	u8	sdma_idmr1;
	u8	res4[3];
	u8	sdma_idsr2;
	u8	res5[3];
	u8	sdma_idmr2;
	u8	res6[3];
	u8	sdma_idsr3;
	u8	res7[3];
	u8	sdma_idmr3;
	u8	res8[3];
	u8	sdma_idsr4;
	u8	res9[3];
	u8	sdma_idmr4;
	u8	res10[707];
} sdma_cpm2_t;

/* Fast controllers
*/
typedef struct fcc {
	u32	fcc_gfmr;
	u32	fcc_fpsmr;
	u16	fcc_ftodr;
	u8	res1[2];
	u16	fcc_fdsr;
	u8	res2[2];
	u16	fcc_fcce;
	u8	res3[2];
	u16	fcc_fccm;
	u8	res4[2];
	u8	fcc_fccs;
	u8	res5[3];
	u8	fcc_ftirr_phy[4];
} fcc_t;

/* Fast controllers continued
 */
typedef struct fcc_c {
	u32	fcc_firper;
	u32	fcc_firer;
	u32	fcc_firsr_hi;
	u32	fcc_firsr_lo;
	u8	fcc_gfemr;
	u8	res1[15];
} fcc_c_t;

/* TC Layer
 */
typedef struct tclayer {
	u16	tc_tcmode;
	u16	tc_cdsmr;
	u16	tc_tcer;
	u16	tc_rcc;
	u16	tc_tcmr;
	u16	tc_fcc;
	u16	tc_ccc;
	u16	tc_icc;
	u16	tc_tcc;
	u16	tc_ecc;
	u8	res1[12];
} tclayer_t;


/* I2C
*/
typedef struct i2c {
	u8	i2c_i2mod;
	u8	res1[3];
	u8	i2c_i2add;
	u8	res2[3];
	u8	i2c_i2brg;
	u8	res3[3];
	u8	i2c_i2com;
	u8	res4[3];
	u8	i2c_i2cer;
	u8	res5[3];
	u8	i2c_i2cmr;
	u8	res6[331];
} i2c_cpm2_t;

typedef struct scc {		/* Serial communication channels */
	u32	scc_gsmrl;
	u32	scc_gsmrh;
	u16	scc_psmr;
	u8	res1[2];
	u16	scc_todr;
	u16	scc_dsr;
	u16	scc_scce;
	u8	res2[2];
	u16	scc_sccm;
	u8	res3;
	u8	scc_sccs;
	u8	res4[8];
} scc_t;

typedef struct smc {		/* Serial management channels */
	u8	res1[2];
	u16	smc_smcmr;
	u8	res2[2];
	u8	smc_smce;
	u8	res3[3];
	u8	smc_smcm;
	u8	res4[5];
} smc_t;

/* Serial Peripheral Interface.
*/
typedef struct spi_ctrl {
	u16	spi_spmode;
	u8	res1[4];
	u8	spi_spie;
	u8	res2[3];
	u8	spi_spim;
	u8	res3[2];
	u8	spi_spcom;
	u8	res4[82];
} spictl_cpm2_t;

/* CPM Mux.
*/
typedef struct cpmux {
	u8	cmx_si1cr;
	u8	res1;
	u8	cmx_si2cr;
	u8	res2;
	u32	cmx_fcr;
	u32	cmx_scr;
	u8	cmx_smr;
	u8	res3;
	u16	cmx_uar;
	u8	res4[16];
} cpmux_t;

/* SIRAM control
*/
typedef struct siram {
	u16	si_amr;
	u16	si_bmr;
	u16	si_cmr;
	u16	si_dmr;
	u8	si_gmr;
	u8	res1;
	u8	si_cmdr;
	u8	res2;
	u8	si_str;
	u8	res3;
	u16	si_rsr;
} siramctl_t;

typedef struct mcc {
	u16	mcc_mcce;
	u8	res1[2];
	u16	mcc_mccm;
	u8	res2[2];
	u8	mcc_mccf;
	u8	res3[7];
} mcc_t;

typedef struct comm_proc {
	u32	cp_cpcr;
	u32	cp_rccr;
	u8	res1[14];
	u16	cp_rter;
	u8	res2[2];
	u16	cp_rtmr;
	u16	cp_rtscr;
	u8	res3[2];
	u32	cp_rtsr;
	u8	res4[12];
} cpm_cpm2_t;

/* USB Controller.
*/
typedef struct cpm_usb_ctlr {
	u8	usb_usmod;
	u8	usb_usadr;
	u8	usb_uscom;
	u8	res1[1];
	__be16  usb_usep[4];
	u8	res2[4];
	__be16  usb_usber;
	u8	res3[2];
	__be16  usb_usbmr;
	u8	usb_usbs;
	u8	res4[7];
} usb_cpm2_t;

/* ...and the whole thing wrapped up....
*/

typedef struct immap {
	/* Some references are into the unique and known dpram spaces,
	 * others are from the generic base.
	 */
#define im_dprambase	im_dpram1
	u8		im_dpram1[16*1024];
	u8		res1[16*1024];
	u8		im_dpram2[4*1024];
	u8		res2[8*1024];
	u8		im_dpram3[4*1024];
	u8		res3[16*1024];

	sysconf_cpm2_t	im_siu_conf;	/* SIU Configuration */
	memctl_cpm2_t	im_memctl;	/* Memory Controller */
	sit_cpm2_t	im_sit;		/* System Integration Timers */
	pci_cpm2_t	im_pci;		/* PCI Controller */
	intctl_cpm2_t	im_intctl;	/* Interrupt Controller */
	car_cpm2_t	im_clkrst;	/* Clocks and reset */
	iop_cpm2_t	im_ioport;	/* IO Port control/status */
	cpmtimer_cpm2_t	im_cpmtimer;	/* CPM timers */
	sdma_cpm2_t	im_sdma;	/* SDMA control/status */

	fcc_t		im_fcc[3];	/* Three FCCs */
	u8		res4z[32];
	fcc_c_t		im_fcc_c[3];	/* Continued FCCs */

	u8		res4[32];

	tclayer_t	im_tclayer[8];	/* Eight TCLayers */
	u16		tc_tcgsr;
	u16		tc_tcger;

	/* First set of baud rate generators.
	*/
	u8		res[236];
	u32		im_brgc5;
	u32		im_brgc6;
	u32		im_brgc7;
	u32		im_brgc8;

	u8		res5[608];

	i2c_cpm2_t	im_i2c;		/* I2C control/status */
	cpm_cpm2_t	im_cpm;		/* Communication processor */

	/* Second set of baud rate generators.
	*/
	u32		im_brgc1;
	u32		im_brgc2;
	u32		im_brgc3;
	u32		im_brgc4;

	scc_t		im_scc[4];	/* Four SCCs */
	smc_t		im_smc[2];	/* Couple of SMCs */
	spictl_cpm2_t	im_spi;		/* A SPI */
	cpmux_t		im_cpmux;	/* CPM clock route mux */
	siramctl_t	im_siramctl1;	/* First SI RAM Control */
	mcc_t		im_mcc1;	/* First MCC */
	siramctl_t	im_siramctl2;	/* Second SI RAM Control */
	mcc_t		im_mcc2;	/* Second MCC */
	usb_cpm2_t	im_usb;		/* USB Controller */

	u8		res6[1153];

	u16		im_si1txram[256];
	u8		res7[512];
	u16		im_si1rxram[256];
	u8		res8[512];
	u16		im_si2txram[256];
	u8		res9[512];
	u16		im_si2rxram[256];
	u8		res10[512];
	u8		res11[4096];
} cpm2_map_t;

extern cpm2_map_t __iomem *cpm2_immr;

#endif /* __IMMAP_CPM2__ */
#endif /* __KERNEL__ */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
33d71d26 KG	2	/*
	3	* CPM2 Internal Memory Map
	4	* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
	5	*
	6	* The Internal Memory Map for devices with CPM2 on them. This
	7	* is the superset of all CPM2 devices (8260, 8266, 8280, 8272,
	8	* 8560).
	9	*/
	10	#ifdef __KERNEL__
	11	#ifndef __IMMAP_CPM2__
	12	#define __IMMAP_CPM2__
	13
449012da SW	14	#include <linux/types.h>
449012da SW	15
33d71d26 KG	16	/* System configuration registers.
	17	*/
	18	typedef struct sys_82xx_conf {
	19	u32 sc_siumcr;
	20	u32 sc_sypcr;
	21	u8 res1[6];
	22	u16 sc_swsr;
	23	u8 res2[20];
	24	u32 sc_bcr;
	25	u8 sc_ppc_acr;
	26	u8 res3[3];
	27	u32 sc_ppc_alrh;
	28	u32 sc_ppc_alrl;
	29	u8 sc_lcl_acr;
	30	u8 res4[3];
	31	u32 sc_lcl_alrh;
	32	u32 sc_lcl_alrl;
	33	u32 sc_tescr1;
	34	u32 sc_tescr2;
	35	u32 sc_ltescr1;
	36	u32 sc_ltescr2;
	37	u32 sc_pdtea;
	38	u8 sc_pdtem;
	39	u8 res5[3];
	40	u32 sc_ldtea;
	41	u8 sc_ldtem;
	42	u8 res6[163];
	43	} sysconf_82xx_cpm2_t;
	44
	45	typedef struct sys_85xx_conf {
	46	u32 sc_cear;
	47	u16 sc_ceer;
	48	u16 sc_cemr;
	49	u8 res1[70];
	50	u32 sc_smaer;
	51	u8 res2[4];
	52	u32 sc_smevr;
	53	u32 sc_smctr;
	54	u32 sc_lmaer;
	55	u8 res3[4];
	56	u32 sc_lmevr;
	57	u32 sc_lmctr;
	58	u8 res4[144];
	59	} sysconf_85xx_cpm2_t;
	60
	61	typedef union sys_conf {
	62	sysconf_82xx_cpm2_t siu_82xx;
	63	sysconf_85xx_cpm2_t siu_85xx;
	64	} sysconf_cpm2_t;
	65
	66
	67
	68	/* Memory controller registers.
	69	*/
	70	typedef struct mem_ctlr {
	71	u32 memc_br0;
	72	u32 memc_or0;
	73	u32 memc_br1;
	74	u32 memc_or1;
	75	u32 memc_br2;
	76	u32 memc_or2;
	77	u32 memc_br3;
	78	u32 memc_or3;
	79	u32 memc_br4;
80	u32 memc_or4;
81	u32 memc_br5;
82	u32 memc_or5;
83	u32 memc_br6;
84	u32 memc_or6;
85	u32 memc_br7;
86	u32 memc_or7;
87	u32 memc_br8;
88	u32 memc_or8;
89	u32 memc_br9;
90	u32 memc_or9;
91	u32 memc_br10;
92	u32 memc_or10;
93	u32 memc_br11;
94	u32 memc_or11;
95	u8 res1[8];
96	u32 memc_mar;
97	u8 res2[4];
98	u32 memc_mamr;
99	u32 memc_mbmr;
100	u32 memc_mcmr;
101	u8 res3[8];
102	u16 memc_mptpr;
103	u8 res4[2];
104	u32 memc_mdr;
105	u8 res5[4];
106	u32 memc_psdmr;
107	u32 memc_lsdmr;
108	u8 memc_purt;
109	u8 res6[3];
110	u8 memc_psrt;
111	u8 res7[3];
112	u8 memc_lurt;
113	u8 res8[3];
114	u8 memc_lsrt;
115	u8 res9[3];
116	u32 memc_immr;
117	u32 memc_pcibr0;
118	u32 memc_pcibr1;
119	u8 res10[16];
120	u32 memc_pcimsk0;
121	u32 memc_pcimsk1;
122	u8 res11[52];
123	} memctl_cpm2_t;
124
125	/* System Integration Timers.
126	*/
127	typedef struct sys_int_timers {
128	u8 res1[32];
129	u16 sit_tmcntsc;
130	u8 res2[2];
131	u32 sit_tmcnt;
132	u8 res3[4];
133	u32 sit_tmcntal;
134	u8 res4[16];
135	u16 sit_piscr;
136	u8 res5[2];
137	u32 sit_pitc;
138	u32 sit_pitr;
139	u8 res6[94];
140	u8 res7[390];
141	} sit_cpm2_t;
142
143	#define PISCR_PIRQ_MASK ((u16)0xff00)
144	#define PISCR_PS ((u16)0x0080)
145	#define PISCR_PIE ((u16)0x0004)
146	#define PISCR_PTF ((u16)0x0002)
147	#define PISCR_PTE ((u16)0x0001)
148
149	/* PCI Controller.
150	*/
151	typedef struct pci_ctlr {
152	u32 pci_omisr;
153	u32 pci_omimr;
154	u8 res1[8];
155	u32 pci_ifqpr;
156	u32 pci_ofqpr;
157	u8 res2[8];
158	u32 pci_imr0;
159	u32 pci_imr1;
160	u32 pci_omr0;
161	u32 pci_omr1;
162	u32 pci_odr;
163	u8 res3[4];
164	u32 pci_idr;
165	u8 res4[20];
166	u32 pci_imisr;
167	u32 pci_imimr;
168	u8 res5[24];
169	u32 pci_ifhpr;
170	u8 res6[4];
171	u32 pci_iftpr;
172	u8 res7[4];
173	u32 pci_iphpr;
174	u8 res8[4];
175	u32 pci_iptpr;
176	u8 res9[4];
177	u32 pci_ofhpr;
178	u8 res10[4];
179	u32 pci_oftpr;
180	u8 res11[4];
181	u32 pci_ophpr;
182	u8 res12[4];
183	u32 pci_optpr;
184	u8 res13[8];
185	u32 pci_mucr;
186	u8 res14[8];
187	u32 pci_qbar;
188	u8 res15[12];
189	u32 pci_dmamr0;
190	u32 pci_dmasr0;
191	u32 pci_dmacdar0;
192	u8 res16[4];
193	u32 pci_dmasar0;
194	u8 res17[4];
195	u32 pci_dmadar0;
196	u8 res18[4];
197	u32 pci_dmabcr0;
198	u32 pci_dmandar0;
199	u8 res19[86];
200	u32 pci_dmamr1;
201	u32 pci_dmasr1;
202	u32 pci_dmacdar1;
203	u8 res20[4];
204	u32 pci_dmasar1;
205	u8 res21[4];
206	u32 pci_dmadar1;
207	u8 res22[4];
208	u32 pci_dmabcr1;
209	u32 pci_dmandar1;
210	u8 res23[88];
211	u32 pci_dmamr2;
212	u32 pci_dmasr2;
213	u32 pci_dmacdar2;
214	u8 res24[4];
215	u32 pci_dmasar2;
216	u8 res25[4];
217	u32 pci_dmadar2;
218	u8 res26[4];
219	u32 pci_dmabcr2;
220	u32 pci_dmandar2;
221	u8 res27[88];
222	u32 pci_dmamr3;
223	u32 pci_dmasr3;
224	u32 pci_dmacdar3;
225	u8 res28[4];
226	u32 pci_dmasar3;
227	u8 res29[4];
228	u32 pci_dmadar3;
229	u8 res30[4];
230	u32 pci_dmabcr3;
231	u32 pci_dmandar3;
232	u8 res31[344];
233	u32 pci_potar0;
234	u8 res32[4];
235	u32 pci_pobar0;
236	u8 res33[4];
237	u32 pci_pocmr0;
238	u8 res34[4];
239	u32 pci_potar1;
240	u8 res35[4];
241	u32 pci_pobar1;
242	u8 res36[4];
243	u32 pci_pocmr1;
244	u8 res37[4];
245	u32 pci_potar2;
246	u8 res38[4];
247	u32 pci_pobar2;
248	u8 res39[4];
249	u32 pci_pocmr2;
250	u8 res40[50];
251	u32 pci_ptcr;
252	u32 pci_gpcr;
253	u32 pci_gcr;
254	u32 pci_esr;
255	u32 pci_emr;
256	u32 pci_ecr;
257	u32 pci_eacr;
258	u8 res41[4];
259	u32 pci_edcr;
260	u8 res42[4];
261	u32 pci_eccr;
262	u8 res43[44];
263	u32 pci_pitar1;
264	u8 res44[4];
265	u32 pci_pibar1;
266	u8 res45[4];
267	u32 pci_picmr1;
268	u8 res46[4];
269	u32 pci_pitar0;
270	u8 res47[4];
271	u32 pci_pibar0;
272	u8 res48[4];
273	u32 pci_picmr0;
274	u8 res49[4];
275	u32 pci_cfg_addr;
276	u32 pci_cfg_data;
277	u32 pci_int_ack;
278	u8 res50[756];
279	} pci_cpm2_t;
280
281	/* Interrupt Controller.
282	*/
283	typedef struct interrupt_controller {
284	u16 ic_sicr;
285	u8 res1[2];
286	u32 ic_sivec;
287	u32 ic_sipnrh;
288	u32 ic_sipnrl;
289	u32 ic_siprr;
290	u32 ic_scprrh;
291	u32 ic_scprrl;
292	u32 ic_simrh;
293	u32 ic_simrl;
294	u32 ic_siexr;
295	u8 res2[88];
296	} intctl_cpm2_t;
297
298	/* Clocks and Reset.
299	*/
300	typedef struct clk_and_reset {
301	u32 car_sccr;
302	u8 res1[4];
303	u32 car_scmr;
304	u8 res2[4];
305	u32 car_rsr;
306	u32 car_rmr;
307	u8 res[104];
308	} car_cpm2_t;
309
310	/* Input/Output Port control/status registers.
311	* Names consistent with processor manual, although they are different
312	* from the original 8xx names.......
313	*/
314	typedef struct io_port {
315	u32 iop_pdira;
316	u32 iop_ppara;
317	u32 iop_psora;
318	u32 iop_podra;
319	u32 iop_pdata;
320	u8 res1[12];
321	u32 iop_pdirb;
322	u32 iop_pparb;
323	u32 iop_psorb;
324	u32 iop_podrb;
325	u32 iop_pdatb;
326	u8 res2[12];
327	u32 iop_pdirc;
328	u32 iop_pparc;
329	u32 iop_psorc;
330	u32 iop_podrc;
331	u32 iop_pdatc;
332	u8 res3[12];
333	u32 iop_pdird;
334	u32 iop_ppard;
335	u32 iop_psord;
336	u32 iop_podrd;
337	u32 iop_pdatd;
338	u8 res4[12];
339	} iop_cpm2_t;
340
341	/* Communication Processor Module Timers
342	*/
343	typedef struct cpm_timers {
344	u8 cpmt_tgcr1;
345	u8 res1[3];
346	u8 cpmt_tgcr2;
347	u8 res2[11];
348	u16 cpmt_tmr1;
349	u16 cpmt_tmr2;
350	u16 cpmt_trr1;
351	u16 cpmt_trr2;
352	u16 cpmt_tcr1;
353	u16 cpmt_tcr2;
354	u16 cpmt_tcn1;
355	u16 cpmt_tcn2;
356	u16 cpmt_tmr3;
357	u16 cpmt_tmr4;
358	u16 cpmt_trr3;
359	u16 cpmt_trr4;
360	u16 cpmt_tcr3;
361	u16 cpmt_tcr4;
362	u16 cpmt_tcn3;
363	u16 cpmt_tcn4;
364	u16 cpmt_ter1;
365	u16 cpmt_ter2;
366	u16 cpmt_ter3;
367	u16 cpmt_ter4;
368	u8 res3[584];
369	} cpmtimer_cpm2_t;
370
371	/* DMA control/status registers.
372	*/
373	typedef struct sdma_csr {
374	u8 res0[24];
375	u8 sdma_sdsr;
376	u8 res1[3];
377	u8 sdma_sdmr;
378	u8 res2[3];
379	u8 sdma_idsr1;
380	u8 res3[3];
381	u8 sdma_idmr1;
382	u8 res4[3];
383	u8 sdma_idsr2;
384	u8 res5[3];
385	u8 sdma_idmr2;
386	u8 res6[3];
387	u8 sdma_idsr3;
388	u8 res7[3];
389	u8 sdma_idmr3;
390	u8 res8[3];
391	u8 sdma_idsr4;
392	u8 res9[3];
393	u8 sdma_idmr4;
394	u8 res10[707];
395	} sdma_cpm2_t;
396
397	/* Fast controllers
398	*/
399	typedef struct fcc {
400	u32 fcc_gfmr;
401	u32 fcc_fpsmr;
402	u16 fcc_ftodr;
403	u8 res1[2];
404	u16 fcc_fdsr;
405	u8 res2[2];
406	u16 fcc_fcce;
407	u8 res3[2];
408	u16 fcc_fccm;
409	u8 res4[2];
410	u8 fcc_fccs;
411	u8 res5[3];
412	u8 fcc_ftirr_phy[4];
413	} fcc_t;
414
415	/* Fast controllers continued
416	*/
417	typedef struct fcc_c {
418	u32 fcc_firper;
419	u32 fcc_firer;
420	u32 fcc_firsr_hi;
421	u32 fcc_firsr_lo;
422	u8 fcc_gfemr;
423	u8 res1[15];
424	} fcc_c_t;
425
426	/* TC Layer
427	*/
428	typedef struct tclayer {
429	u16 tc_tcmode;
430	u16 tc_cdsmr;
431	u16 tc_tcer;
432	u16 tc_rcc;
433	u16 tc_tcmr;
434	u16 tc_fcc;
435	u16 tc_ccc;
436	u16 tc_icc;
437	u16 tc_tcc;
438	u16 tc_ecc;
439	u8 res1[12];
440	} tclayer_t;
441
442
443	/* I2C
444	*/
445	typedef struct i2c {
446	u8 i2c_i2mod;
447	u8 res1[3];
448	u8 i2c_i2add;
449	u8 res2[3];
450	u8 i2c_i2brg;
451	u8 res3[3];
452	u8 i2c_i2com;
453	u8 res4[3];
454	u8 i2c_i2cer;
455	u8 res5[3];
456	u8 i2c_i2cmr;
457	u8 res6[331];
458	} i2c_cpm2_t;
459
460	typedef struct scc { /* Serial communication channels */
461	u32 scc_gsmrl;
462	u32 scc_gsmrh;
463	u16 scc_psmr;
464	u8 res1[2];
465	u16 scc_todr;
466	u16 scc_dsr;
467	u16 scc_scce;
468	u8 res2[2];
469	u16 scc_sccm;
470	u8 res3;
471	u8 scc_sccs;
472	u8 res4[8];
473	} scc_t;
474
475	typedef struct smc { /* Serial management channels */
476	u8 res1[2];
477	u16 smc_smcmr;
478	u8 res2[2];
479	u8 smc_smce;
480	u8 res3[3];
481	u8 smc_smcm;
482	u8 res4[5];
483	} smc_t;
484
485	/* Serial Peripheral Interface.
486	*/
487	typedef struct spi_ctrl {
488	u16 spi_spmode;
489	u8 res1[4];
490	u8 spi_spie;
491	u8 res2[3];
492	u8 spi_spim;
493	u8 res3[2];
494	u8 spi_spcom;
495	u8 res4[82];
496	} spictl_cpm2_t;
497
498	/* CPM Mux.
499	*/
500	typedef struct cpmux {
501	u8 cmx_si1cr;
502	u8 res1;
503	u8 cmx_si2cr;
504	u8 res2;
505	u32 cmx_fcr;
506	u32 cmx_scr;
507	u8 cmx_smr;
508	u8 res3;
509	u16 cmx_uar;
510	u8 res4[16];
511	} cpmux_t;
512
513	/* SIRAM control
514	*/
515	typedef struct siram {
516	u16 si_amr;
517	u16 si_bmr;
518	u16 si_cmr;
519	u16 si_dmr;
520	u8 si_gmr;
521	u8 res1;
522	u8 si_cmdr;
523	u8 res2;
524	u8 si_str;
525	u8 res3;
526	u16 si_rsr;
527	} siramctl_t;
528
529	typedef struct mcc {
530	u16 mcc_mcce;
531	u8 res1[2];
532	u16 mcc_mccm;
533	u8 res2[2];
534	u8 mcc_mccf;
535	u8 res3[7];
536	} mcc_t;
537
538	typedef struct comm_proc {
539	u32 cp_cpcr;
540	u32 cp_rccr;
541	u8 res1[14];
542	u16 cp_rter;
543	u8 res2[2];
544	u16 cp_rtmr;
545	u16 cp_rtscr;
546	u8 res3[2];
547	u32 cp_rtsr;
548	u8 res4[12];
549	} cpm_cpm2_t;
550
551	/* USB Controller.
552	*/
80952988	553	typedef struct cpm_usb_ctlr {
33d71d26 KG	554	u8 usb_usmod;
	555	u8 usb_usadr;
	556	u8 usb_uscom;
	557	u8 res1[1];
2b487065	558	__be16 usb_usep[4];
33d71d26	559	u8 res2[4];
2b487065	560	__be16 usb_usber;
33d71d26	561	u8 res3[2];
2b487065	562	__be16 usb_usbmr;
33d71d26 KG	563	u8 usb_usbs;
	564	u8 res4[7];
	565	} usb_cpm2_t;
	566
	567	/* ...and the whole thing wrapped up....
	568	*/
	569
	570	typedef struct immap {
	571	/* Some references are into the unique and known dpram spaces,
	572	* others are from the generic base.
	573	*/
	574	#define im_dprambase im_dpram1
	575	u8 im_dpram1[16*1024];
	576	u8 res1[16*1024];
	577	u8 im_dpram2[4*1024];
	578	u8 res2[8*1024];
	579	u8 im_dpram3[4*1024];
	580	u8 res3[16*1024];
	581
	582	sysconf_cpm2_t im_siu_conf; /* SIU Configuration */
	583	memctl_cpm2_t im_memctl; /* Memory Controller */
	584	sit_cpm2_t im_sit; /* System Integration Timers */
	585	pci_cpm2_t im_pci; /* PCI Controller */
	586	intctl_cpm2_t im_intctl; /* Interrupt Controller */
	587	car_cpm2_t im_clkrst; /* Clocks and reset */
	588	iop_cpm2_t im_ioport; /* IO Port control/status */
	589	cpmtimer_cpm2_t im_cpmtimer; /* CPM timers */
	590	sdma_cpm2_t im_sdma; /* SDMA control/status */
	591
	592	fcc_t im_fcc[3]; /* Three FCCs */
	593	u8 res4z[32];
	594	fcc_c_t im_fcc_c[3]; /* Continued FCCs */
	595
	596	u8 res4[32];
	597
	598	tclayer_t im_tclayer[8]; /* Eight TCLayers */
	599	u16 tc_tcgsr;
	600	u16 tc_tcger;
	601
	602	/* First set of baud rate generators.
	603	*/
	604	u8 res[236];
	605	u32 im_brgc5;
	606	u32 im_brgc6;
	607	u32 im_brgc7;
	608	u32 im_brgc8;
	609
	610	u8 res5[608];
	611
	612	i2c_cpm2_t im_i2c; /* I2C control/status */
	613	cpm_cpm2_t im_cpm; /* Communication processor */
	614
	615	/* Second set of baud rate generators.
	616	*/
	617	u32 im_brgc1;
	618	u32 im_brgc2;
	619	u32 im_brgc3;
	620	u32 im_brgc4;
	621
	622	scc_t im_scc[4]; /* Four SCCs */
	623	smc_t im_smc[2]; /* Couple of SMCs */
	624	spictl_cpm2_t im_spi; /* A SPI */
	625	cpmux_t im_cpmux; /* CPM clock route mux */
	626	siramctl_t im_siramctl1; /* First SI RAM Control */
627	mcc_t im_mcc1; /* First MCC */
628	siramctl_t im_siramctl2; /* Second SI RAM Control */
629	mcc_t im_mcc2; /* Second MCC */
630	usb_cpm2_t im_usb; /* USB Controller */
631
632	u8 res6[1153];
633
634	u16 im_si1txram[256];
635	u8 res7[512];
636	u16 im_si1rxram[256];
637	u8 res8[512];
638	u16 im_si2txram[256];
639	u8 res9[512];
640	u16 im_si2rxram[256];
641	u8 res10[512];
642	u8 res11[4096];
643	} cpm2_map_t;
644
449012da	645	extern cpm2_map_t __iomem *cpm2_immr;
33d71d26 KG	646
	647	#endif /* __IMMAP_CPM2__ */
	648	#endif /* __KERNEL__ */