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powerpc/power8: Update denormalization handler
[linux-2.6-block.git] / arch / powerpc / include / asm / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
d1cdcf22
AB		 4
5#include <asm/asm-compat.h>
c5157e58 6#include <asm/feature-fixups.h>
c3617f72 7#include <uapi/asm/cputable.h>
d1cdcf22 8
10b35d99
KG		 9#ifndef __ASSEMBLY__
10
11/* This structure can grow, it's real size is used by head.S code
12 * via the mkdefs mechanism.
13 */
14struct cpu_spec;
10b35d99 15
10b35d99 16typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 17typedef void (*cpu_restore_t)(void);
10b35d99 18
32a33994 19enum powerpc_oprofile_type {
7a45fb19
AW		 20 PPC_OPROFILE_INVALID = 0,
21 PPC_OPROFILE_RS64 = 1,
22 PPC_OPROFILE_POWER4 = 2,
23 PPC_OPROFILE_G4 = 3,
39aef685 24 PPC_OPROFILE_FSL_EMB = 4,
18f2190d 25 PPC_OPROFILE_CELL = 5,
25fc530e 26 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 27};
28
1bd2e5ae
OJ		 29enum powerpc_pmc_type {
30 PPC_PMC_DEFAULT = 0,
31 PPC_PMC_IBM = 1,
32 PPC_PMC_PA6T = 2,
b950bdd0 33 PPC_PMC_G4 = 3,
1bd2e5ae
OJ		 34};
35
47c0bd1a
BH		 36struct pt_regs;
37
38extern int machine_check_generic(struct pt_regs *regs);
39extern int machine_check_4xx(struct pt_regs *regs);
40extern int machine_check_440A(struct pt_regs *regs);
fe04b112 41extern int machine_check_e500mc(struct pt_regs *regs);
47c0bd1a
BH		 42extern int machine_check_e500(struct pt_regs *regs);
43extern int machine_check_e200(struct pt_regs *regs);
fc5e7097 44extern int machine_check_47x(struct pt_regs *regs);
47c0bd1a 45
87a72f9e 46/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 47struct cpu_spec {
48 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
49 unsigned int pvr_mask;
50 unsigned int pvr_value;
51
52 char *cpu_name;
53 unsigned long cpu_features; /* Kernel features */
54 unsigned int cpu_user_features; /* Userland features */
2171364d 55 unsigned int cpu_user_features2; /* Userland features v2 */
7c03d653 56 unsigned int mmu_features; /* MMU features */
10b35d99
KG		 57
58 /* cache line sizes */
59 unsigned int icache_bsize;
60 unsigned int dcache_bsize;
61
62 /* number of performance monitor counters */
63 unsigned int num_pmcs;
1bd2e5ae 64 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 65
66 /* this is called to initialize various CPU bits like L1 cache,
67 * BHT, SPD, etc... from head.S before branching to identify_machine
68 */
69 cpu_setup_t cpu_setup;
f39b7a55
OJ		 70 /* Used to restore cpu setup on secondary processors and at resume */
71 cpu_restore_t cpu_restore;
10b35d99
KG		 72
73 /* Used by oprofile userspace to select the right counters */
74 char *oprofile_cpu_type;
75
76 /* Processor specific oprofile operations */
32a33994 77 enum powerpc_oprofile_type oprofile_type;
80f15dc7 78
e78dbc80
MN		 79 /* Bit locations inside the mmcra change */
80 unsigned long oprofile_mmcra_sihv;
81 unsigned long oprofile_mmcra_sipr;
82
83 /* Bits to clear during an oprofile exception */
84 unsigned long oprofile_mmcra_clear;
85
80f15dc7
PM		 86 /* Name of processor class, for the ELF AT_PLATFORM entry */
87 char *platform;
47c0bd1a
BH		 88
89 /* Processor specific machine check handling. Return negative
90 * if the error is fatal, 1 if it was fully recovered and 0 to
91 * pass up (not CPU originated) */
92 int (*machine_check)(struct pt_regs *regs);
10b35d99
KG		 93};
94
10b35d99 95extern struct cpu_spec *cur_cpu_spec;
10b35d99 96
42c4aaad
BH		 97extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
98
974a76f5 99extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
0909c8c2
BH		 100extern void do_feature_fixups(unsigned long value, void *fixup_start,
101 void *fixup_end);
9b6b563c 102
9115d134
NL		 103extern const char *powerpc_base_platform;
104
10b35d99
KG		 105#endif /* __ASSEMBLY__ */
106
107/* CPU kernel features */
108
109/* Retain the 32b definitions all use bottom half of word */
cde4d494
MN		 110#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
111#define CPU_FTR_L2CR ASM_CONST(0x00000002)
112#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
113#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
114#define CPU_FTR_TAU ASM_CONST(0x00000010)
115#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
116#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
117#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
118#define CPU_FTR_601 ASM_CONST(0x00000100)
119#define CPU_FTR_DBELL ASM_CONST(0x00000200)
120#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
121#define CPU_FTR_L3CR ASM_CONST(0x00000800)
122#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
123#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
124#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
125#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
126#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
127#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
128#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
129#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
130#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
131#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
132#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
133#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
134#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
135#define CPU_FTR_SPE ASM_CONST(0x02000000)
136#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
137#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
138#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
139#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
140#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
10b35d99 141
3965f8c5
PM		 142/*
143 * Add the 64-bit processor unique features in the top half of the word;
144 * on 32-bit, make the names available but defined to be 0.
145 */
10b35d99 146#ifdef __powerpc64__
3965f8c5 147#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 148#else
3965f8c5 149#define LONG_ASM_CONST(x) 0
10b35d99
KG		 150#endif
151
1580b3b8
MN		 152#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
153#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
154#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
1de2bd4e 155#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000)
1580b3b8
MN		 156#define CPU_FTR_IABR LONG_ASM_CONST(0x0000001000000000)
157#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
158#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
159#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
160#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
161#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
162#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
163#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
164#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
165#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
166#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
167#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
168#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
169#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
170#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
171#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
172#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
173#define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
174#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
175#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
1de2bd4e 176#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
1580b3b8 177#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
79879c17 178#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
3965f8c5 179
10b35d99
KG		 180#ifndef __ASSEMBLY__
181
44ae3ab3
ME		 182#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
183
184#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
185 MMU_FTR_16M_PAGE)
10b35d99
KG		 186
187/* We only set the altivec features if the kernel was compiled with altivec
188 * support
189 */
190#ifdef CONFIG_ALTIVEC
191#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
192#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
193#else
194#define CPU_FTR_ALTIVEC_COMP 0
195#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
196#endif
197
b962ce9d
MN		 198/* We only set the VSX features if the kernel was compiled with VSX
199 * support
200 */
201#ifdef CONFIG_VSX
202#define CPU_FTR_VSX_COMP CPU_FTR_VSX
203#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
204#else
205#define CPU_FTR_VSX_COMP 0
206#define PPC_FEATURE_HAS_VSX_COMP 0
207#endif
208
5e14d21e
KG		 209/* We only set the spe features if the kernel was compiled with spe
210 * support
211 */
212#ifdef CONFIG_SPE
213#define CPU_FTR_SPE_COMP CPU_FTR_SPE
214#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
215#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
216#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
217#else
218#define CPU_FTR_SPE_COMP 0
219#define PPC_FEATURE_HAS_SPE_COMP 0
220#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
221#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
222#endif
223
6a6d541f
MN		 224/* We only set the TM feature if the kernel was compiled with TM supprt */
225#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
226#define CPU_FTR_TM_COMP CPU_FTR_TM
cbbc6f1b 227#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
6a6d541f
MN		 228#else
229#define CPU_FTR_TM_COMP 0
cbbc6f1b 230#define PPC_FEATURE2_HTM_COMP 0
6a6d541f
MN		 231#endif
232
11af1192
SW		 233/* We need to mark all pages as being coherent if we're SMP or we have a
234 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
235 * require it for PCI "streaming/prefetch" to work properly.
c9310920 236 * This is also required by 52xx family.
10b35d99 237 */
1775dbbc 238#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
c9310920
PZ		 239 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
240 || defined(CONFIG_PPC_MPC52xx)
10b35d99
KG		 241#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
242#else
243#define CPU_FTR_COMMON 0
244#endif
245
246/* The powersave features NAP & DOZE seems to confuse BDI when
247 debugging. So if a BDI is used, disable theses
248 */
249#ifndef CONFIG_BDI_SWITCH
250#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
251#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
252#else
253#define CPU_FTR_MAYBE_CAN_DOZE 0
254#define CPU_FTR_MAYBE_CAN_NAP 0
255#endif
256
257#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
258 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
259 !defined(CONFIG_BOOKE))
260
7c03d653 261#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
4508dc21
DG		 262 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
263#define CPU_FTRS_603 (CPU_FTR_COMMON | \
7c92943c 264 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 265 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 266#define CPU_FTRS_604 (CPU_FTR_COMMON | \
7c03d653 267 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
4508dc21 268#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
7c92943c 269 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 270 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 271#define CPU_FTRS_740 (CPU_FTR_COMMON | \
7c92943c 272 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 273 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 274 CPU_FTR_PPC_LE)
4508dc21 275#define CPU_FTRS_750 (CPU_FTR_COMMON | \
7c92943c 276 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 277 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 278 CPU_FTR_PPC_LE)
7c03d653 279#define CPU_FTRS_750CL (CPU_FTRS_750)
b6f41cc8
JB		 280#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
281#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
7c03d653 282#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
b6f41cc8 283#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 284#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
7c92943c 285 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 286 CPU_FTR_ALTIVEC_COMP | \
fab5db97 287 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 288#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
7c92943c 289 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 290 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
fab5db97 291 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 292#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
7c92943c 293 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 294 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
b64f87c1 295 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 296#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c
SR		 297 CPU_FTR_USE_TB | \
298 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 299 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 300 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 301 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 302#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
b64f87c1 303 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 304 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 305 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
fab5db97 306 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 307#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
b64f87c1 308 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 309 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
7c03d653 310 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 311#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
b64f87c1 312 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 313 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 314 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 315 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
7c03d653 316 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 317#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c
SR		 318 CPU_FTR_USE_TB | \
319 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 320 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 321 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 322#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c
SR		 323 CPU_FTR_USE_TB | \
324 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 325 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1
BB		 326 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
327 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 328#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c
SR		 329 CPU_FTR_USE_TB | \
330 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 331 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 332 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 333#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c
SR		 334 CPU_FTR_USE_TB | \
335 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 336 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 337 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 338#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548
JY		 339 CPU_FTR_USE_TB | \
340 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 341 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 342 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 343#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
7c92943c 344 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
11af1192 345#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 346 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
4508dc21 347#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 348 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
7c92943c 349 CPU_FTR_COMMON)
4508dc21 350#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 351 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
aa42c69c 352 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
7c03d653 353#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
4508dc21 354#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
8309ce72
BH		 355#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
356#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
6d2170be
BH		 357#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
358 CPU_FTR_INDEXED_DCR)
e7f75ad0 359#define CPU_FTRS_47X (CPU_FTRS_440x6)
5e14d21e
KG		 360#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
361 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
52b066fa
SW		 362 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
363 CPU_FTR_DEBUG_LVL_EXC)
fc4033b2 364#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
8309ce72
BH		 365 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
366 CPU_FTR_NOEXECUTE)
fc4033b2 367#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
7c03d653 368 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
8309ce72 369 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
d51ad915 370#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
620165f9 371 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
73196cd3 372 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
11ed0db9
KG		 373#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
374 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
d36b4c4f 375 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
73196cd3 376 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
10241842
KG		 377#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
378 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
379 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
cd66cc2e 380 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP)
7c92943c 381#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 382
383/* 64-bit CPUs */
5a0e9b57 384#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
7c03d653 385 CPU_FTR_IABR | CPU_FTR_PPC_LE)
5a0e9b57 386#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
7c03d653 387 CPU_FTR_IABR | \
7c92943c 388 CPU_FTR_MMCRA | CPU_FTR_CTRL)
2d1b2027 389#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 390 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
f89451fb
AB		 391 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
392 CPU_FTR_STCX_CHECKS_ADDRESS)
2d1b2027 393#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
969391c5 394 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
2a929436 395 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
969391c5
PM		 396 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
397 CPU_FTR_HVMODE)
2d1b2027 398#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 399 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 400 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3
ME		 401 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
402 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
2d1b2027 403#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 404 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51 405 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 406 CPU_FTR_COHERENT_ICACHE | \
4c198557 407 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 408 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
48404f2e 409 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
2d1b2027 410#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
969391c5 411 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
e952e6c4 412 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 413 CPU_FTR_COHERENT_ICACHE | \
e952e6c4 414 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 415 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
851d2e2f 416 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d2613868
HM		 417 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
418 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR)
71e18497
MN		 419#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
420 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
421 CPU_FTR_MMCRA | CPU_FTR_SMT | \
422 CPU_FTR_COHERENT_ICACHE | \
423 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
424 CPU_FTR_DSCR | CPU_FTR_SAO | \
425 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
e5e84f0a 426 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
1de2bd4e
ME		 427 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
428 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
2d1b2027 429#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 430 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 431 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 432 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
4ec577a2 433 CPU_FTR_UNALIGNED_LD_STD)
2d1b2027 434#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
44ae3ab3
ME		 435 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
436 CPU_FTR_PURR | CPU_FTR_REAL_LE)
7c03d653 437#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 438
76b4eda8 439#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
fac26ad4 440 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
76b4eda8 441
2406f606 442#ifdef __powerpc64__
11ed0db9 443#ifdef CONFIG_PPC_BOOK3E
10241842 444#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
11ed0db9 445#else
7c92943c
SR		 446#define CPU_FTRS_POSSIBLE \
447 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
03054d51 448 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
71e18497
MN		 449 CPU_FTRS_POWER7 | CPU_FTRS_POWER8 | CPU_FTRS_CELL | \
450 CPU_FTRS_PA6T | CPU_FTR_VSX)
11ed0db9 451#endif
2406f606 452#else
7c92943c
SR		 453enum {
454 CPU_FTRS_POSSIBLE =
10b35d99
KG		 455#if CLASSIC_PPC
456 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
457 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
458 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
459 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
460 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
461 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
462 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 463 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
464 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 465#else
466 CPU_FTRS_GENERIC_32 |
467#endif
10b35d99
KG		 468#ifdef CONFIG_8xx
469 CPU_FTRS_8XX |
470#endif
471#ifdef CONFIG_40x
472 CPU_FTRS_40X |
473#endif
474#ifdef CONFIG_44x
6d2170be 475 CPU_FTRS_44X | CPU_FTRS_440x6 |
10b35d99 476#endif
e7f75ad0 477#ifdef CONFIG_PPC_47x
c48d0dba 478 CPU_FTRS_47X | CPU_FTR_476_DD2 |
e7f75ad0 479#endif
10b35d99
KG		 480#ifdef CONFIG_E200
481 CPU_FTRS_E200 |
482#endif
483#ifdef CONFIG_E500
06aae867
SW		 484 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
485#endif
486#ifdef CONFIG_PPC_E500MC
487 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
10b35d99 488#endif
10b35d99 489 0,
7c92943c
SR		 490};
491#endif /* __powerpc64__ */
10b35d99 492
2406f606 493#ifdef __powerpc64__
11ed0db9 494#ifdef CONFIG_PPC_BOOK3E
10241842 495#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
11ed0db9 496#else
7c92943c
SR		 497#define CPU_FTRS_ALWAYS \
498 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
03054d51 499 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
e952e6c4 500 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
11ed0db9 501#endif
2406f606 502#else
7c92943c
SR		 503enum {
504 CPU_FTRS_ALWAYS =
10b35d99
KG		 505#if CLASSIC_PPC
506 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
507 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
508 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
509 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
510 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
511 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
512 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 513 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
514 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 515#else
516 CPU_FTRS_GENERIC_32 &
517#endif
10b35d99
KG		 518#ifdef CONFIG_8xx
519 CPU_FTRS_8XX &
520#endif
521#ifdef CONFIG_40x
522 CPU_FTRS_40X &
523#endif
524#ifdef CONFIG_44x
6d2170be 525 CPU_FTRS_44X & CPU_FTRS_440x6 &
10b35d99
KG		 526#endif
527#ifdef CONFIG_E200
528 CPU_FTRS_E200 &
529#endif
530#ifdef CONFIG_E500
06aae867
SW		 531 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
532#endif
533#ifdef CONFIG_PPC_E500MC
534 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
10b35d99 535#endif
73196cd3 536 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
10b35d99
KG		 537 CPU_FTRS_POSSIBLE,
538};
7c92943c 539#endif /* __powerpc64__ */
10b35d99
KG		 540
541static inline int cpu_has_feature(unsigned long feature)
542{
543 return (CPU_FTRS_ALWAYS & feature) ||
544 (CPU_FTRS_POSSIBLE
10b35d99 545 & cur_cpu_spec->cpu_features
10b35d99
KG		 546 & feature);
547}
548
5aae8a53 549#define HBP_NUM 1
5aae8a53 550
10b35d99
KG		 551#endif /* !__ASSEMBLY__ */
552
10b35d99 553#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux 6.x block layer and io_uring tree(s)